///***************************************** // Copyright (C) 2009-2019 // ITE Tech. Inc. All Rights Reserved // Proprietary and Confidential ///***************************************** // @file // @author Jau-Chih.Tseng@ite.com.tw // @date 2019/01/03 // @fileversion: ITE_HDMITX_SAMPLE_3.27 //******************************************/ #ifndef _HDMITX_DRV_H_ #define _HDMITX_DRV_H_ //#define EXTERN_HDCPROM ///////////////////////////////////////// // DDC Address ///////////////////////////////////////// #define DDC_HDCP_ADDRESS 0x74 #define DDC_EDID_ADDRESS 0xA0 #define DDC_FIFO_MAXREQ 0x20 // I2C address #define _80MHz 80000000 #define HDMI_TX_I2C_SLAVE_ADDR 0x98 #define CEC_I2C_SLAVE_ADDR 0x9C /////////////////////////////////////////////////////////////////////// // Register offset /////////////////////////////////////////////////////////////////////// #define REG_TX_VENDOR_ID0 0x00 #define REG_TX_VENDOR_ID1 0x01 #define REG_TX_DEVICE_ID0 0x02 #define REG_TX_DEVICE_ID1 0x03 #define O_TX_DEVID 0 #define M_TX_DEVID 0xF #define O_TX_REVID 4 #define M_TX_REVID 0xF #define REG_TX_SW_RST 0x04 #define B_TX_ENTEST (1<<7) #define B_TX_REF_RST_HDMITX (1<<5) #define B_TX_AREF_RST (1<<4) #define B_HDMITX_VID_RST (1<<3) #define B_HDMITX_AUD_RST (1<<2) #define B_TX_HDMI_RST (1<<1) #define B_TX_HDCP_RST_HDMITX (1<<0) #define REG_TX_INT_CTRL 0x05 #define B_TX_INTPOL_ACTL 0 #define B_TX_INTPOL_ACTH (1<<7) #define B_TX_INT_PUSHPULL 0 #define B_TX_INT_OPENDRAIN (1<<6) #define REG_TX_INT_STAT1 0x06 #define B_TX_INT_AUD_OVERFLOW (1<<7) #define B_TX_INT_ROMACQ_NOACK (1<<6) #define B_TX_INT_RDDC_NOACK (1<<5) #define B_TX_INT_DDCFIFO_ERR (1<<4) #define B_TX_INT_ROMACQ_BUS_HANG (1<<3) #define B_TX_INT_DDC_BUS_HANG (1<<2) #define B_TX_INT_RX_SENSE (1<<1) #define B_TX_INT_HPD_PLUG (1<<0) #define REG_TX_INT_STAT2 0x07 #define B_TX_INT_HDCP_SYNC_DET_FAIL (1<<7) #define B_TX_INT_VID_UNSTABLE (1<<6) #define B_TX_INT_PKTACP (1<<5) #define B_TX_INT_PKTNULL (1<<4) #define B_TX_INT_PKTGENERAL (1<<3) #define B_TX_INT_KSVLIST_CHK (1<<2) #define B_TX_INT_AUTH_DONE (1<<1) #define B_TX_INT_AUTH_FAIL (1<<0) #define REG_TX_INT_STAT3 0x08 #define B_TX_INT_AUD_CTS (1<<6) #define B_TX_INT_VSYNC (1<<5) #define B_TX_INT_VIDSTABLE (1<<4) #define B_TX_INT_PKTMPG (1<<3) #define B_TX_INT_PKTSPD (1<<2) #define B_TX_INT_PKTAUD (1<<1) #define B_TX_INT_PKTAVI (1<<0) #define REG_TX_INT_MASK1 0x09 #define B_TX_AUDIO_OVFLW_MASK (1<<7) #define B_TX_DDC_NOACK_MASK (1<<5) #define B_TX_DDC_FIFO_ERR_MASK (1<<4) #define B_TX_DDC_BUS_HANG_MASK (1<<2) #define B_TX_RXSEN_MASK (1<<1) #define B_TX_HPD_MASK (1<<0) #define REG_TX_INT_MASK2 0x0A #define B_TX_PKT_AVI_MASK (1<<7) #define B_TX_PKT_VID_UNSTABLE_MASK (1<<6) #define B_TX_PKT_ACP_MASK (1<<5) #define B_TX_PKT_NULL_MASK (1<<4) #define B_TX_PKT_GEN_MASK (1<<3) #define B_TX_KSVLISTCHK_MASK (1<<2) #define B_TX_AUTH_DONE_MASK (1<<1) #define B_TX_AUTH_FAIL_MASK (1<<0) #define REG_TX_INT_MASK3 0x0B #define B_TX_HDCP_SYNC_DET_FAIL_MASK (1<<6) #define B_TX_AUDCTS_MASK (1<<5) #define B_TX_VSYNC_MASK (1<<4) #define B_TX_VIDSTABLE_MASK (1<<3) #define B_TX_PKT_MPG_MASK (1<<2) #define B_TX_PKT_SPD_MASK (1<<1) #define B_TX_PKT_AUD_MASK (1<<0) #define REG_TX_INT_CLR0 0x0C #define B_TX_CLR_PKTACP (1<<7) #define B_TX_CLR_PKTNULL (1<<6) #define B_TX_CLR_PKTGENERAL (1<<5) #define B_TX_CLR_KSVLISTCHK (1<<4) #define B_TX_CLR_AUTH_DONE (1<<3) #define B_TX_CLR_AUTH_FAIL (1<<2) #define B_TX_CLR_RXSENSE (1<<1) #define B_TX_CLR_HPD (1<<0) #define REG_TX_INT_CLR1 0x0D #define B_TX_CLR_VSYNC (1<<7) #define B_TX_CLR_VIDSTABLE (1<<6) #define B_TX_CLR_PKTMPG (1<<5) #define B_TX_CLR_PKTSPD (1<<4) #define B_TX_CLR_PKTAUD (1<<3) #define B_TX_CLR_PKTAVI (1<<2) #define B_TX_CLR_HDCP_SYNC_DET_FAIL (1<<1) #define B_TX_CLR_VID_UNSTABLE (1<<0) #define REG_TX_SYS_STATUS 0x0E // readonly #define B_TX_INT_ACTIVE (1<<7) #define B_TX_HPDETECT (1<<6) #define B_TX_RXSENDETECT (1<<5) #define B_TXVIDSTABLE (1<<4) // read/write #define O_TX_CTSINTSTEP 2 #define M_TX_CTSINTSTEP (3<<2) #define B_TX_CLR_AUD_CTS (1<<1) #define B_TX_INTACTDONE (1<<0) #define REG_TX_BANK_CTRL 0x0F #define B_TX_BANK0 0 #define B_TX_BANK1 1 // DDC #define REG_TX_DDC_MASTER_CTRL 0x10 #define B_TX_MASTERROM (1<<1) #define B_TX_MASTERDDC (0<<1) #define B_TX_MASTERHOST (1<<0) #define B_TX_MASTERHDCP (0<<0) #define REG_TX_DDC_HEADER 0x11 #define REG_TX_DDC_REQOFF 0x12 #define REG_TX_DDC_REQCOUNT 0x13 #define REG_TX_DDC_EDIDSEG 0x14 #define REG_TX_DDC_CMD 0x15 #define CMD_DDC_SEQ_BURSTREAD 0 #define CMD_LINK_CHKREAD 2 #define CMD_EDID_READ 3 #define CMD_FIFO_CLR 9 #define CMD_GEN_SCLCLK 0xA #define CMD_DDC_ABORT 0xF #define REG_TX_DDC_STATUS 0x16 #define B_TX_DDC_DONE (1<<7) #define B_TX_DDC_ACT (1<<6) #define B_TX_DDC_NOACK (1<<5) #define B_TX_DDC_WAITBUS (1<<4) #define B_TX_DDC_ARBILOSE (1<<3) #define B_TX_DDC_ERROR (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE) #define B_TX_DDC_FIFOFULL (1<<2) #define B_TX_DDC_FIFOEMPTY (1<<1) #define REG_TX_DDC_READFIFO 0x17 #define REG_TX_ROM_STARTADDR 0x18 #define REG_TX_HDCP_HEADER 0x19 #define REG_TX_ROM_HEADER 0x1A #define REG_TX_BUSHOLD_T 0x1B #define REG_TX_ROM_STAT 0x1C #define B_TX_ROM_DONE (1<<7) #define B_TX_ROM_ACTIVE (1<<6) #define B_TX_ROM_NOACK (1<<5) #define B_TX_ROM_WAITBUS (1<<4) #define B_TX_ROM_ARBILOSE (1<<3) #define B_TX_ROM_BUSHANG (1<<2) // HDCP #define REG_TX_AN_GENERATE 0x1F #define B_TX_START_CIPHER_GEN 1 #define B_TX_STOP_CIPHER_GEN 0 #define REG_TX_CLK_CTRL0 0x58 #define O_TX_OSCLK_SEL 5 #define M_TX_OSCLK_SEL 3 #define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4) #define O_TX_EXT_MCLK_SEL 2 #define M_TX_EXT_MCLK_SEL (3<