// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada AP807 Quad
 *
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 */

#include "armada-ap807.dtsi"

/ {
        model = "Marvell Armada AP807 Quad";
        compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";

        cpus {
                #address-cells = <1>;
                #size-cells = <0>;

                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x000>;
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 0>;
                        i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2_0>;
                };
                cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x001>;
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 0>;
                        i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2_0>;
                };
                cpu2: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x100>;
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 1>;
                        i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2_1>;
                };
                cpu3: cpu@101 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72";
                        reg = <0x101>;
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 1>;
                        i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2_1>;
                };

                l2_0: l2-cache0 {
                        compatible = "cache";
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <512>;
                };

                l2_1: l2-cache1 {
                        compatible = "cache";
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <512>;
                };
        };
};