// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040.dtsi"

/ {
        model = "Marvell 8040 MACCHIATOBin";
        compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
                        "marvell,armada-ap806-quad", "marvell,armada-ap806";

        chosen {
                stdout-path = "serial0:115200n8";
        };

        memory@0 {
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };

        aliases {
                ethernet0 = &cp0_eth0;
                ethernet1 = &cp1_eth0;
                ethernet2 = &cp1_eth1;
                ethernet3 = &cp1_eth2;
        };

        /* Regulator labels correspond with schematics */
        v_3_3: regulator-3-3v {
                compatible = "regulator-fixed";
                regulator-name = "v_3_3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
                status = "okay";
        };

        v_vddo_h: regulator-1-8v {
                compatible = "regulator-fixed";
                regulator-name = "v_vddo_h";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
                regulator-always-on;
                status = "okay";
        };

        v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
                compatible = "regulator-fixed";
                enable-active-high;
                gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&cp0_xhci_vbus_pins>;
                regulator-name = "v_5v0_usb3_hst_vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                status = "okay";
        };

        sfp_eth0: sfp-eth0 {
                /* CON15,16 - CPM lane 4 */
                compatible = "sff,sfp";
                i2c-bus = <&sfpp0_i2c>;
                los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
                mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
                tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
                tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&cp1_sfpp0_pins>;
                maximum-power-milliwatt = <2000>;
        };

        sfp_eth1: sfp-eth1 {
                /* CON17,18 - CPS lane 4 */
                compatible = "sff,sfp";
                i2c-bus = <&sfpp1_i2c>;
                los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
                mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
                tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
                tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
                maximum-power-milliwatt = <2000>;
        };

        sfp_eth3: sfp-eth3 {
                /* CON13,14 - CPS lane 5 */
                compatible = "sff,sfp";
                i2c-bus = <&sfp_1g_i2c>;
                los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
                mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
                tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
                tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
                maximum-power-milliwatt = <2000>;
        };
};

&uart0 {
        status = "okay";
        pinctrl-0 = <&uart0_pins>;
        pinctrl-names = "default";
};

&ap_sdhci0 {
        bus-width = <8>;
        /*
         * Not stable in HS modes - phy needs "more calibration", so add
         * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
         */
        marvell,xenon-phy-slow-mode;
        no-1-8-v;
        no-sd;
        no-sdio;
        non-removable;
        status = "okay";
        vqmmc-supply = <&v_vddo_h>;
};

&cp0_i2c0 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_i2c0_pins>;
        status = "okay";
};

&cp0_i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_i2c1_pins>;
        status = "okay";

        i2c-switch@70 {
                compatible = "nxp,pca9548";
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x70>;

                sfpp0_i2c: i2c@0 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0>;
                };
                sfpp1_i2c: i2c@1 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <1>;
                };
                sfp_1g_i2c: i2c@2 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <2>;
                };
        };
};

/* J25 UART header */
&cp0_uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_uart1_pins>;
        status = "okay";
};

&cp0_mdio {
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_ge_mdio_pins>;
        status = "okay";

        ge_phy: ethernet-phy@0 {
                reg = <0>;
        };
};

&cp0_pcie0 {
        compatible = "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam",
                     "pci-host-ecam-generic";
        reg = <0 0xe0000000 0 0xff00000>;
        bus-range = <0 0xfe>;
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_pcie_pins>;
        num-lanes = <4>;
        num-viewport = <8>;
        reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
        ranges = <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000>,
                 <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
                 <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;
        phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
               <&cp0_comphy2 0>, <&cp0_comphy3 0>;
        phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
                    "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
        status = "okay";
};

&cp0_pinctrl {
        cp0_ge_mdio_pins: ge-mdio-pins {
                marvell,pins = "mpp32", "mpp34";
                marvell,function = "ge";
        };
        cp0_i2c1_pins: i2c1-pins {
                marvell,pins = "mpp35", "mpp36";
                marvell,function = "i2c1";
        };
        cp0_i2c0_pins: i2c0-pins {
                marvell,pins = "mpp37", "mpp38";
                marvell,function = "i2c0";
        };
        cp0_uart1_pins: uart1-pins {
                marvell,pins = "mpp40", "mpp41";
                marvell,function = "uart1";
        };
        cp0_xhci_vbus_pins: xhci0-vbus-pins {
                marvell,pins = "mpp47";
                marvell,function = "gpio";
        };
        cp0_sfp_1g_pins: sfp-1g-pins {
                marvell,pins = "mpp51", "mpp53", "mpp54";
                marvell,function = "gpio";
        };
        cp0_pcie_pins: pcie-pins {
                marvell,pins = "mpp52";
                marvell,function = "gpio";
        };
        cp0_sdhci_pins: sdhci-pins {
                marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
                               "mpp60", "mpp61";
                marvell,function = "sdio";
        };
        cp0_sfpp1_pins: sfpp1-pins {
                marvell,pins = "mpp62";
                marvell,function = "gpio";
        };
};

&cp0_ethernet {
        status = "okay";
};

&cp0_eth0 {
        /* Generic PHY, providing serdes lanes */
        phys = <&cp0_comphy4 0>;
};

&cp0_sata0 {
        status = "okay";

        /* CPM Lane 5 - U29 */
        sata-port@1 {
                phys = <&cp0_comphy5 1>;
                phy-names = "cp0-sata0-1-phy";
        };
};

&cp0_sdhci0 {
        /* U6 */
        broken-cd;
        bus-width = <4>;
        pinctrl-names = "default";
        pinctrl-0 = <&cp0_sdhci_pins>;
        status = "okay";
        vqmmc-supply = <&v_3_3>;
};

&cp0_usb3_0 {
        /* J38? - USB2.0 only */
        status = "okay";
};

&cp0_usb3_1 {
        /* J38? - USB2.0 only */
        status = "okay";
};

&cp1_ethernet {
        status = "okay";
};

&cp1_eth0 {
        /* Generic PHY, providing serdes lanes */
        phys = <&cp1_comphy4 0>;
};

&cp1_eth1 {
        /* CPS Lane 0 - J5 (Gigabit RJ45) */
        status = "okay";
        /* Network PHY */
        phy = <&ge_phy>;
        phy-mode = "sgmii";
        /* Generic PHY, providing serdes lanes */
        phys = <&cp1_comphy0 1>;
};

&cp1_eth2 {
        /* CPS Lane 5 */
        status = "okay";
        /* Network PHY */
        phy-mode = "2500base-x";
        managed = "in-band-status";
        /* Generic PHY, providing serdes lanes */
        phys = <&cp1_comphy5 2>;
        sfp = <&sfp_eth3>;
};

&cp1_pinctrl {
        cp1_sfpp1_pins: sfpp1-pins {
                marvell,pins = "mpp8", "mpp10", "mpp11";
                marvell,function = "gpio";
        };
        cp1_spi1_pins: spi1-pins {
                marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
                marvell,function = "spi1";
        };
        cp1_uart0_pins: uart0-pins {
                marvell,pins = "mpp6", "mpp7";
                marvell,function = "uart0";
        };
        cp1_sfp_1g_pins: sfp-1g-pins {
                marvell,pins = "mpp24";
                marvell,function = "gpio";
        };
        cp1_sfpp0_pins: sfpp0-pins {
                marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
                marvell,function = "gpio";
        };
};

/* J27 UART header */
&cp1_uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&cp1_uart0_pins>;
        status = "okay";
};

&cp1_sata0 {
        status = "okay";

        /* CPS Lane 1 - U32 */
        sata-port@0 {
                phys = <&cp1_comphy1 0>;
                phy-names = "cp1-sata0-0-phy";
        };

        /* CPS Lane 3 - U31 */
        sata-port@1 {
                phys = <&cp1_comphy3 1>;
                phy-names = "cp1-sata0-1-phy";
        };
};

&cp1_spi1 {
        pinctrl-names = "default";
        pinctrl-0 = <&cp1_spi1_pins>;

        spi-flash@0 {
                compatible = "st,w25q32";
                spi-max-frequency = <50000000>;
                reg = <0>;
        };
};

&cp1_comphy2 {
        cp1_usbh0_con: connector {
                compatible = "usb-a-connector";
                phy-supply = <&v_5v0_usb3_hst_vbus>;
        };
};

&cp1_usb3_0 {
        /* CPS Lane 2 - CON7 */
        phys = <&cp1_comphy2 0>;
        phy-names = "cp1-usb3h0-comphy";
        status = "okay";
};