/** @file Header file for PchDmiLib. Copyright (c) 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef _PCH_DMI_LIB_H_ #define _PCH_DMI_LIB_H_ /** This function checks if DMI Secured Register Lock (SRL) is set @retval SRL state **/ BOOLEAN IsPchDmiLocked ( VOID ); /** Get PCH TCO base address. @retval Address Address of TCO base address. **/ UINT16 PchDmiGetTcoBase ( VOID ); /** Set PCH LPC/eSPI generic IO range decoding in DMI @param[in] Address Address for generic IO range base address. @param[in] Length Length of generic IO range. @param[in] RangeIndex Index of choosen range @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetLpcGenIoRange ( IN UINT32 Address, IN UINT32 Length, IN UINT32 RangeIndex ); /** Set PCH eSPI eSPI CS1# generic IO range decoding in DMI @param[in] Address Address for generic IO range base address. @param[in] Length Length of generic IO range. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetEspiCs1GenIoRange ( IN UINT32 Address, IN UINT32 Length ); /** Set PCH LPC/eSPI memory range decoding in DMI @param[in] Address Address for memory base address. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetLpcMemRange ( IN UINT32 Address ); /** Set PCH eSPI CS1# memory range decoding in DMI @param[in] Address Address for memory base address. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetEspiCs1MemRange ( IN UINT32 Address ); /** Check if Boot BIOS Strap is set for SPI. @retval TRUE Boot BIOS Strap set for SPI @retval FALSE Boot BIOS Strap set for LPC/eSPI **/ BOOLEAN PchDmiIsBootBiosStrapSetForSpi ( VOID ); /** Set PCH BIOS range decoding in DMI Please check EDS for detail of BiosDecodeEnable bit definition. bit 15: F8-FF Enable bit 14: F0-F8 Enable bit 13: E8-EF Enable bit 12: E0-E8 Enable bit 11: D8-DF Enable bit 10: D0-D7 Enable bit 9: C8-CF Enable bit 8: C0-C7 Enable bit 7: Legacy F Segment Enable bit 6: Legacy E Segment Enable bit 5: Reserved bit 4: Reserved bit 3: 70-7F Enable bit 2: 60-6F Enable bit 1: 50-5F Enable bit 0: 40-4F Enable @param[in] BiosDecodeEnable Bios decode enable setting. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetBiosDecodeEnable ( IN UINT16 BiosDecodeEnable ); /** Set PCH LPC/eSPI IO decode ranges in DMI Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. Bit 12: FDD range Bit 9:8: LPT range Bit 6:4: ComB range Bit 2:0: ComA range @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetLpcIoDecodeRanges ( IN UINT16 LpcIoDecodeRanges ); /** Set PCH LPC/eSPI IO enable decoding in DMI @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings. @retval EFI_SUCCESS Successfully completed. @retval EFI_UNSUPPORTED DMIC.SRL is set. **/ EFI_STATUS PchDmiSetLpcIoEnable ( IN UINT16 LpcIoEnableDecoding ); /** Configure PCH DMI Lock **/ VOID PchDmiSetLockWithS3BootScript ( VOID ); /** Set BIOS interface Lock-Down **/ VOID PchDmiSetBiosLockDownWithS3BootScript ( VOID ); #endif // _PCH_DMI_LIB_H_