/** @file Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.
Copyright (c) 2017, Linaro, Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef OGMA_REG_NETSEC_H #define OGMA_REG_NETSEC_H #define OGMA_REG_ADDR_SOFT_RST (0x41) #define OGMA_REG_ADDR_COM_INIT (0x48) #define OGMA_REG_ADDR_MC_BASE_ADDR (0x97) #define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84) #define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89) #define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A) #define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34) #define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C) #define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D) #define OGMA_REG_ADDR_DIS_CORE (0x86) #define OGMA_REG_ADDR_DMA_HM_CTRL (0x85) #define OGMA_REG_ADDR_DMA_MH_CTRL (0x88) #define OGMA_REG_ADDR_CLK_EN_0 (0x40) #define OGMA_REG_ADDR_CLK_EN_1 (0x64) #define OGMA_REG_ADDR_PKT_CTRL (0x50) #define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D) #define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102) #define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D) #define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112) #define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D) #define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122) #define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D) #define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132) #define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D) #define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142) #define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D) #define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152) #define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D) #define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192) #define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD) #define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2) #define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD) #define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2) #define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D) #define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202) #define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D) #define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212) #define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D) #define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222) #define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D) #define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232) #define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D) #define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242) #define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D) #define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252) #define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D) #define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262) #define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D) #define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272) #define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D) #define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282) #define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D) #define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292) #define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C) #define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C) #define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C) #define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C) #define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C) #define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C) #define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C) #define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC) #define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC) #define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C) #define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C) #define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C) #define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C) #define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C) #define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C) #define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C) #define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C) #define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C) #define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C) #define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83) #define OGMA_REG_ADDR_TOP_STATUS (0x80) #define OGMA_REG_ADDR_TOP_INTEN_A (0x81) #define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D) #define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E) #define OGMA_REG_ADDR_TOP_INTEN_B (0x8F) #define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90) #define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91) #define OGMA_REG_ADDR_PKT_STATUS (0x3) #define OGMA_REG_ADDR_PKT_INTEN (0x4) #define OGMA_REG_ADDR_PKT_INTEN_SET (0x7) #define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8) #define OGMA_REG_ADDR_TLS_STATUS (0x5) #define OGMA_REG_ADDR_TLS_INTEN (0x6) #define OGMA_REG_ADDR_TLS_INTEN_SET (0x9) #define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA) #define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB) #define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC) #define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD) #define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE) #define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF) #define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10) #define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11) #define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12) #define OGMA_REG_ADDR_MAC_STATUS (0x409) #define OGMA_REG_ADDR_MAC_INTEN (0x40A) #define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486) #define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487) #define OGMA_REG_ADDR_NRM_TX_STATUS (0x100) #define OGMA_REG_ADDR_NRM_TX_INTEN (0x101) #define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A) #define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B) #define OGMA_REG_ADDR_NRM_RX_STATUS (0x110) #define OGMA_REG_ADDR_NRM_RX_INTEN (0x111) #define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A) #define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B) #define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120) #define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121) #define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A) #define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B) #define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130) #define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131) #define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A) #define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B) #define OGMA_REG_ADDR_MISC_RX_STATUS (0x140) #define OGMA_REG_ADDR_MISC_RX_INTEN (0x141) #define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A) #define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B) #define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150) #define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151) #define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A) #define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B) #define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160) #define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161) #define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A) #define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B) #define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0) #define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1) #define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA) #define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB) #define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0) #define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1) #define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA) #define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB) #define OGMA_REG_ADDR_DEC_TX_STATUS (0x200) #define OGMA_REG_ADDR_DEC_TX_INTEN (0x201) #define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A) #define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B) #define OGMA_REG_ADDR_ENC_RX_STATUS (0x210) #define OGMA_REG_ADDR_ENC_RX_INTEN (0x211) #define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A) #define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B) #define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220) #define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221) #define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A) #define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B) #define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230) #define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231) #define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A) #define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B) #define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240) #define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241) #define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A) #define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B) #define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250) #define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251) #define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A) #define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B) #define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260) #define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261) #define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A) #define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B) #define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270) #define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271) #define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A) #define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B) #define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280) #define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281) #define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A) #define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B) #define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290) #define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291) #define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A) #define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B) #define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104) #define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134) #define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154) #define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4) #define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204) #define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224) #define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234) #define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264) #define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274) #define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105) #define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135) #define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155) #define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5) #define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205) #define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225) #define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235) #define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265) #define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275) #define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106) #define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136) #define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156) #define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6) #define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206) #define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226) #define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236) #define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266) #define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276) #define OGMA_REG_ADDR_NRM_TX_TMR (0x107) #define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137) #define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177) #define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7) #define OGMA_REG_ADDR_DEC_TX_TMR (0x207) #define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108) #define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138) #define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158) #define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178) #define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8) #define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8) #define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208) #define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115) #define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125) #define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145) #define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195) #define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5) #define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215) #define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245) #define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255) #define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285) #define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295) #define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116) #define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126) #define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146) #define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166) #define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186) #define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196) #define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6) #define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216) #define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246) #define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256) #define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286) #define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296) #define OGMA_REG_ADDR_NRM_RX_TMR (0x117) #define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127) #define OGMA_REG_ADDR_MISC_RX_TMR (0x147) #define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197) #define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7) #define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118) #define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128) #define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148) #define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168) #define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188) #define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198) #define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8) #define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8) #define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8) #define OGMA_REG_ADDR_PODB_CMD_ST (0x20) #define OGMA_REG_ADDR_PODB_DATA (0x21) #define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A) #define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B) #define OGMA_REG_ADDR_CLS_CMD_ST (0x2C) #define OGMA_REG_ADDR_CLS_DATA (0x2D) #define OGMA_REG_ADDR_SADB_CMD_ST (0x2E) #define OGMA_REG_ADDR_SADB_DATA (0x2F) #define OGMA_REG_ADDR_MAC_CMD (0x471) #define OGMA_REG_ADDR_MAC_DATA (0x470) #define OGMA_REG_ADDR_MAC_FLOW_TH (0x473) #define OGMA_REG_ADDR_MAC_INTF_SEL (0x475) #define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476) #define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477) #define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478) #define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479) #define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A) #define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B) #define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C) #define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F) #define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480) #define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481) #define OGMA_REG_ADDR_IV_INIT_VAL (0x45) #define OGMA_REG_ADDR_MAC_ADD_UP (0x43) #define OGMA_REG_ADDR_MAC_ADD_LW (0x44) #define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65) #define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66) #define OGMA_REG_ADDR_ST_INFO_SIZE (0x67) #define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68) #define OGMA_REG_ADDR_LOGIC_GR_ID (0x69) #define OGMA_REG_ADDR_ST_FOR_PBC (0x6A) #define OGMA_REG_ADDR_ALARM_INFO (0x6B) #define OGMA_REG_ADDR_MC_VER (0x8B) #define OGMA_REG_ADDR_HW_VER (0x8C) #define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140) #endif /* OGMA_REG_F_TAIKI_H */