// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

/dts-v1/;

#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-thunder-boot-spi-nor.dtsi"

/ {
	model = "Rockchip RV1106G EVB2 V10 Board";
	compatible = "rockchip,rv1106g-evb2-v10", "rockchip,rv1106";

	chosen {
		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
	};

	vcc_1v8: vcc-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v8";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vcc_3v3: vcc-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	vcc3v3_sd: vcc3v3-sd {
		compatible = "regulator-fixed";
		gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
		regulator-name = "vcc3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_pwren>;
	};

	wireless_wlan: wireless-wlan {
		compatible = "wlan-platdata";
		WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

&csi2_dphy_hw {
	status = "okay";
};

&csi2_dphy0 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			csi_dphy_input0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&sc3338_out>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			csi_dphy_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi_csi2_input>;
			};
		};
	};
};

&emmc {
	status = "disabled";
};

&fiq_debugger {
	rockchip,baudrate = <1500000>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m1_xfer>;
};

&i2c4 {
	rockchip,amp-shared;

	sc3338: sc3338@30 {
		compatible = "smartsens,sc3338";
		status = "okay";
		reg = <0x30>;
		clocks = <&cru MCLK_REF_MIPI0>;
		clock-names = "xvclk";
		reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
		pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&mipi_refclk_out0>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "FKO1";
		rockchip,camera-module-lens-name = "30IRC-F16";
		port {
			sc3338_out: endpoint {
				remote-endpoint = <&csi_dphy_input0>;
				data-lanes = <1 2>;
			};
		};
	};
};

&mipi0_csi2 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_csi2_input: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&csi_dphy_output>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_csi2_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&cif_mipi_in>;
			};
		};
	};
};

&mailbox {
	status = "okay";
};

&rkcif {
	status = "okay";
};

&rkcif_mipi_lvds {
	status = "okay";
	memory-region-thunderboot = <&rkisp_thunderboot>;

	pinctrl-names = "default";
	pinctrl-0 = <&mipi_pins>;
	port {
		/* MIPI CSI-2 endpoint */
		cif_mipi_in: endpoint {
			remote-endpoint = <&mipi_csi2_output>;
		};
	};
};

&rkcif_mipi_lvds_sditf {
	status = "okay";

	port {
		/* MIPI CSI-2 endpoint */
		mipi_lvds_sditf: endpoint {
			remote-endpoint = <&isp_in>;
		};
	};
};

&rkisp {
	status = "okay";
};

&rkisp_vir0 {
	status = "okay";

	port@0 {
		isp_in: endpoint {
			remote-endpoint = <&mipi_lvds_sditf>;
		};
	};
};

&thunder_boot_service {
	status = "okay";
};

&rkisp_thunderboot {
	/* reg's offset MUST match with RTOS */
	/*
	 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
	 * e.g. 2304x1296: 0xf30000
	 */
	reg = <0x00860000 0xf30000>;
};

&ramdisk_r {
	reg = <0x1790000 (20 * 0x00100000)>;
};

&ramdisk_c {
	reg = <0x2b90000 (10 * 0x00100000)>;
};

&pinctrl {
	sdmmc {
		/omit-if-no-ref/
		sdmmc_pwren: sdmmc-pwren {
			rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pwm10 {
	status = "okay";
};

&pwm11 {
	status = "okay";
};

&sdio {
	max-frequency = <50000000>;
	bus-width = <1>;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	non-removable;
	rockchip,default-sample-phase = <90>;
	no-sd;
	no-mmc;
	supports-sdio;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
	status = "okay";
};

&sdmmc {
	max-frequency = <200000000>;
	no-sdio;
	no-mmc;
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	pinctrl-names = "normal", "idle";
	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
	pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
	vmmc-supply = <&vcc3v3_sd>;
	status = "okay";
};

&sfc {
	assigned-clocks = <&cru SCLK_SFC>;
	assigned-clock-rates = <125000000>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <125000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
	};
};

&usbdrd_dwc3 {
	dr_mode = "peripheral";
};