/** @file
* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
*
* This file lists all the processors available on the platform that the OSPM
* can enumerate and boot. It also lists all the interrupt controllers available
* in the system.
*
* Copyright (c) 2021, Arm Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
* @par Specification Reference:
*   - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/

#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"

#define CORE_CNT   (FixedPcdGet32 (PcdClusterCount) * \
                      FixedPcdGet32 (PcdCoreCount))

// Multiple APIC Description Table
#pragma pack (1)

typedef struct {
  EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
  EFI_ACPI_6_2_GIC_STRUCTURE                            GicInterfaces[CORE_CNT];
  EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
  EFI_ACPI_6_2_GICR_STRUCTURE                           GicRedistributor;
  EFI_ACPI_6_2_GIC_ITS_STRUCTURE                        GicIts[3];
} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;

#pragma pack ()

STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
  {
    ARM_ACPI_HEADER (
      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
    ),
    // MADT specific fields
    0, // LocalApicAddress
    0  // Flags
  },
  {
    // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
    //                                          PmuIrq, GicBase, GicVBase,
    //                                          GicHBase, GsivId, GicRBase,
    //                                          Efficiency)
    // Note: The GIC Structure of the primary CPU must be the first entry
    // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
      0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
      0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
      0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
      0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
      0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
      0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
      0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
      0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
      0, 0, 0, 25, 0, 0),
  },
  // GIC Distributor Entry
  EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
                                    0, 3),
  // GIC Redistributor
  EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
                                      SIZE_16MB),
  // GIC ITS
  {
    EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
    EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
    EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
  },
};

//
// Reference the table being generated to prevent the optimizer from removing
// the data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Madt;