/** @file * Multiple APIC Description Table (MADT) * * Copyright (c) 2019-2020, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ #include "SgiPlatform.h" #include "SgiAcpiHeader.h" #include #include #include #include #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) #define CHIP_CNT (FixedPcdGet32 (PcdChipCount)) // Multiple APIC Description Table #pragma pack (1) typedef struct { EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT]; EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT]; } EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; #pragma pack () STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, // Efficiency) // Note: The GIC Structure of the primary CPU must be the first entry // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). // Chip - 0 CPUs EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), // Chip - 1 CPUs EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */) }, // GIC Distributor Entry EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3), { // GIC Redistributor for Chip 0 EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), SIZE_1MB), // GIC Redistributor for Chip 1 EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_1MB) } }; // // Reference the table being generated to prevent the optimizer from removing // the data structure from the executable // VOID* CONST ReferenceAcpiTable = &Madt;