// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

/dts-v1/;

#include "rv1103.dtsi"
#include "rv1106-thunder-boot-spi-nor.dtsi"

/ {
	model = "Rockchip RV1103G RMSL311 DLOC Board";
	compatible = "rockchip,rv1103g-rmsl311-dloc-v10", "rockchip,rv1103";

	chosen {
		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
	};

	vcc_1v8: vcc-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v8";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vcc_3v3: vcc-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	vdd_arm: vdd-arm {
		compatible = "pwm-regulator";
		pwms = <&pwm0 0 5000 1>;
		regulator-name = "vdd_arm";
		regulator-min-microvolt = <724000>;
		regulator-max-microvolt = <1078000>;
		regulator-init-microvolt = <950000>;
		regulator-always-on;
		regulator-boot-on;
		regulator-settling-time-up-us = <250>;
	};
};

&csi2_dphy_hw {
	status = "okay";
};

&csi2_dphy1 {
	status = "okay";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			dphy1_in: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&sc035gs_out>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			dphy1_out: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&mipi0_csi2_input>;
			};
		};
	};
};

&fiq_debugger {
	rockchip,irq-mode-enable = <1>;
	status = "okay";
	rockchip,baudrate = <1500000>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2m1_xfer>;
};

&i2c4 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4m2_xfer>;

	sc035gs: sc035gs@30 {
		compatible = "smartsens,sc035gs";
		status = "okay";
		reg = <0x30>;
		clocks = <&cru MCLK_REF_MIPI0>;
		clock-names = "xvclk";
		reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&mipi_refclk_out0>;

		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "default";
		rockchip,camera-module-lens-name = "default";

		port {
			sc035gs_out: endpoint {
				remote-endpoint = <&dphy1_in>;
				data-lanes = <1 2>;
			};
		};
	};

	vcsel_rk803: vcsel_rk803@63 {
		compatible = "rockchip,rk803";
		status = "okay";
		reg = <0x63>;

		gpio-encc1-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; //Flood
		gpio-encc2-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; //PRO
	};
};

&memory {
	reg = <0x00000000 0x04000000>;
};

&mipi0_csi2 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi0_csi2_input: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&dphy1_out>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi0_csi2_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&cif_mipi0_in>;
				data-lanes = <1 2>;
			};
		};
	};
};

&npu {
	status = "okay";
};

&pwm0 {
	status = "okay";
};

&rga2 {
	status = "okay";
};

&rkcif {
	status = "okay";
};

&rkcif_mipi_lvds {
	status = "okay";

	port {
		/* MIPI CSI-2 endpoint */
		cif_mipi0_in: endpoint {
			remote-endpoint = <&mipi0_csi2_output>;
			data-lanes = <1 2>;
		};
	};
};

&rkcif_mipi_lvds_sditf {
	status = "okay";

	port {
		/* MIPI CSI-2 endpoint */
		mipi_lvds0_sditf: endpoint {
			remote-endpoint = <&isp0_in>;
			data-lanes = <1 2>;
		};
	};
};

&rkisp {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&mipi_pins>;

	max-input = <640 480 30>;
};

&rkisp_vir0 {
	status = "okay";

	ports {
		port@0 {
			isp0_in: endpoint {
				remote-endpoint = <&mipi_lvds0_sditf>;
			};
		};
	};
};

&rkisp_vir1 {
	status = "okay";
};

&rng {
	status = "okay";
};

&saradc {
	status = "okay";
	vref-supply = <&vcc_1v8>;
};

&sfc {
	assigned-clocks = <&cru SCLK_SFC>;
	assigned-clock-rates = <125000000>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <125000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
	};
};

&tsadc {
	status = "okay";
};

&u2phy {
	status = "okay";
};

&u2phy_otg {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbdrd {
	status = "okay";
};

&usbdrd_dwc3 {
	extcon = <&u2phy>;
	status = "okay";
};