Rockchip specific extensions to the Synopsys Designware MIPI DSI
================================

Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: must be one of:
	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk1808-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi".
	"rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- power-domains: a phandle to mipi dsi power domain node.
- resets: list of phandle + reset specifier pairs, as described in [3].
- reset-names: string reset name, must be "apb".
- clocks, clock-names: Phandles to the controller's APB clock(pclk),
  As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
  For vopb,set the reg = <0> and set the reg = <1> for vopl.

Optional properties:
- clocks, clock-names:
  phandle to the SNPS-PHY config clock, name should be "phy_cfg".
  phandle to the SNPS-PHY PLL reference clock, name should be "ref".
  phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
- phys: phandle to Non-SNPS PHY node
- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
  attribute, provides phandle to MIPI PHY node
- rockchip,lane-rate: optional override of the desired bandwidth.
- rockchip,dual-channel: for dual-channel mode, phandle to the slave channel.
- rockchip,data-swap: for dual-channel mode, swap two channel data of MIPI.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
[3] Documentation/devicetree/bindings/reset/reset.txt

Example:
	dsi: dsi@ff960000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
		reg = <0xff960000 0x4000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
		clock-names = "ref", "pclk";
		resets = <&cru SRST_MIPIDSI0>;
		reset-names = "apb";
		rockchip,grf = <&grf>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			port {
				#address-cells = <1>;
				#size-cells = <0>;

				dsi_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_dsi>;
				};

				dsi_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_dsi>;
				};
			};
		};

		panel {
			compatible ="boe,tv080wum-nl0";
			reg = <0>;

			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&lcd_en>;
			backlight = <&backlight>;
		};
	};