// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/soc/rockchip-amp.h>

/ {
	rockchip_amp: rockchip-amp {
		compatible = "rockchip,amp";
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>,
			<&cru PCLK_TIMER>, <&cru SCLK_TIMER4>, <&cru SCLK_TIMER5>;

		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		status = "okay";
		amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
		amp-irqs = /bits/ 64 <GIC_AMP_IRQ_CFG_ROUTE(51, 0xd0, CPU_GET_AFFINITY(3, 0))
				      GIC_AMP_IRQ_CFG_ROUTE(132, 0xd0, CPU_GET_AFFINITY(3, 0))>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* remote amp core address */
		amp_reserved: amp@2e00000 {
			reg = <0x0 0x2e00000 0x0 0x1200000>;
			no-map;
		};

		rpmsg_reserved: rpmsg@7c00000 {
			reg = <0x0 0x07c00000 0x0 0x400000>;
			no-map;
		};

		rpmsg_dma_reserved: rpmsg-dma@8000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x08000000 0x0 0x100000>;
			no-map;
		};
	};

	rpmsg: rpmsg@7c00000 {
		compatible = "rockchip,rpmsg-softirq";
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,vdev-nums = <1>;
		rockchip,link-id = <0x03>;
		reg = <0x0 0x7c00000 0x0 0x20000>;
		memory-region = <&rpmsg_dma_reserved>;

		status = "okay";
	};
};

&cpu3 {
	status = "disabled";
};