From d4a1bd480003f3e1a0590bc46fbcb24f05652ca7 Mon Sep 17 00:00:00 2001
From: tzh <tanzhtanzh@gmail.com>
Date: Thu, 15 Aug 2024 06:56:47 +0000
Subject: [PATCH] feat(wfit/bt): update aic8800 wifi/bt drive and hal
---
longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h | 124 ++++++++++++++++++++++++++++++++++-------
1 files changed, 103 insertions(+), 21 deletions(-)
diff --git a/longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h b/longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h
old mode 100644
new mode 100755
index 1fc80a9..c644bd4
--- a/longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h
+++ b/longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h
@@ -190,6 +190,13 @@
DBG_MEM_MASK_WRITE_REQ,
/// Memory mask write confirm
DBG_MEM_MASK_WRITE_CFM,
+
+ DBG_RFTEST_CMD_REQ,
+ DBG_RFTEST_CMD_CFM,
+ DBG_BINDING_REQ,
+ DBG_BINDING_CFM,
+ DBG_BINDING_IND,
+
/// Max number of Debug messages
DBG_MAX,
};
@@ -257,6 +264,14 @@
u32 bootstatus;
};
+struct dbg_binding_ind {
+ u8 enc_data[16];
+};
+
+struct dbg_binding_req {
+ u8 driver_data[16];
+};
+
int rwnx_send_dbg_mem_read_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
struct dbg_mem_read_cfm *cfm);
int rwnx_send_dbg_mem_block_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
@@ -264,23 +279,21 @@
int rwnx_send_dbg_mem_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr, u32 mem_data);
int rwnx_send_dbg_mem_mask_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
u32 mem_mask, u32 mem_data);
-int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type);
+int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type, struct dbg_start_app_cfm *start_app_cfm);
+int rwnx_send_dbg_binding_req(struct aic_sdio_dev *sdiodev, u8 *dout, u8 *binding_status);
void rwnx_rx_handle_msg(struct aic_sdio_dev *sdiodev, struct ipc_e2a_msg *msg);
int aicbsp_platform_init(struct aic_sdio_dev *sdiodev);
void aicbsp_platform_deinit(struct aic_sdio_dev *sdiodev);
-void aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
+int aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
+int aicbsp_resv_mem_init(void);
+int aicbsp_resv_mem_deinit(void);
-#define AICBSP_FW_PATH "/vendor/etc/firmware"
-#define AICBSP_FW_PATH_MAX 200
-
-#define RAM_FW_ADDR 0x00100000
-#define RAM_FMAC_FW_ADDR 0x00110000
+#define RAM_FMAC_FW_ADDR 0x00120000
#define FW_RAM_ADID_BASE_ADDR 0x00161928
-#define FW_RAM_PATCH_BASE_ADDR 0x0016ad64
-#define FW_PATCH_TEST_BASE_ADDR 0x00100000
-#define FW_WIFI_RAM_ADDR 0x00110000
+#define FW_RAM_ADID_BASE_ADDR_U03 0x00161928
+#define FW_RAM_PATCH_BASE_ADDR 0x00100000
#define AICBT_PT_TAG "AICBT_PT_TAG"
@@ -290,19 +303,70 @@
AICBT_PT_BTMODE,
AICBT_PT_PWRON,
AICBT_PT_AF,
+ AICBT_PT_VER,
};
-enum aicbsp_mode_num {
- AICBSP_MODE_BT_ONLY_SW = 0x0, // bt only mode with switch
- AICBSP_MODE_BT_WIFI_COMBO, // wifi/bt combo mode
- AICBSP_MODE_BT_ONLY, // bt only mode without switch
- AICBSP_MODE_BT_ONLY_TEST, // bt only test mode
- AICBSP_MODE_COMBO_TEST, // wifi/bt combo test mode
+enum aicbt_btport_type {
+ AICBT_BTPORT_NULL,
+ AICBT_BTPORT_MB,
+ AICBT_BTPORT_UART,
};
-#define AICBSP_MODE_DEFAULT AICBSP_MODE_BT_WIFI_COMBO
+/* btmode
+ * used for force bt mode,if not AICBSP_MODE_NULL
+ * efuse valid and vendor_info will be invalid, even has beed set valid
+*/
+enum aicbt_btmode_type {
+ AICBT_BTMODE_BT_ONLY_SW = 0x0, // bt only mode with switch
+ AICBT_BTMODE_BT_WIFI_COMBO, // wifi/bt combo mode
+ AICBT_BTMODE_BT_ONLY, // bt only mode without switch
+ AICBT_BTMODE_BT_ONLY_TEST, // bt only test mode
+ AICBT_BTMODE_BT_WIFI_COMBO_TEST, // wifi/bt combo test mode
+ AICBT_MODE_NULL = 0xFF, // invalid value
+};
-#define FEATURE_5G_SUPPORT 0x01
+/* uart_baud
+ * used for config uart baud when btport set to uart,
+ * otherwise meaningless
+*/
+enum aicbt_uart_baud_type {
+ AICBT_UART_BAUD_115200 = 115200,
+ AICBT_UART_BAUD_921600 = 921600,
+ AICBT_UART_BAUD_1_5M = 1500000,
+ AICBT_UART_BAUD_3_25M = 3250000,
+};
+
+enum aicbt_uart_flowctrl_type {
+ AICBT_UART_FLOWCTRL_DISABLE = 0x0, // uart without flow ctrl
+ AICBT_UART_FLOWCTRL_ENABLE, // uart with flow ctrl
+};
+
+enum aicbsp_cpmode_type {
+ AICBSP_CPMODE_WORK,
+ AICBSP_CPMODE_TEST,
+ AICBSP_CPMODE_MAX,
+};
+
+enum chip_rev {
+ CHIP_REV_U02 = 3,
+ CHIP_REV_U03 = 7,
+ CHIP_REV_U04 = 7,
+};
+
+///aic bt tx pwr lvl :lsb->msb: first byte, min pwr lvl; second byte, max pwr lvl;
+///pwr lvl:20(min), 30 , 40 , 50 , 60(max)
+#define AICBT_TXPWR_LVL 0x00006020
+
+#define AICBSP_HWINFO_DEFAULT (-1)
+#define AICBSP_CPMODE_DEFAULT AICBSP_CPMODE_WORK
+
+#define AICBT_BTMODE_DEFAULT AICBT_MODE_NULL
+#define AICBT_BTPORT_DEFAULT AICBT_BTPORT_UART
+#define AICBT_UART_BAUD_DEFAULT AICBT_UART_BAUD_1_5M
+#define AICBT_UART_FC_DEFAULT AICBT_UART_FLOWCTRL_ENABLE
+#define AICBT_LPM_ENABLE_DEFAULT 1
+#define AICBT_TXPWR_LVL_DEFAULT AICBT_TXPWR_LVL
+
#define FEATURE_SDIO_CLOCK 70000000 // 0: default, other: target clock rate
#define FEATURE_SDIO_PHASE 2 // 0: default, 2: 180°
@@ -314,17 +378,35 @@
struct aicbt_patch_table *next;
};
+struct aicbt_info_t {
+ uint32_t btmode;
+ uint32_t btport;
+ uint32_t uart_baud;
+ uint32_t uart_flowctrl;
+ uint32_t lpm_enable;
+ uint32_t txpwr_lvl;
+};
+
struct aicbsp_firmware {
const char *desc;
const char *bt_adid;
const char *bt_patch;
const char *bt_table;
- const char *bt_patch_test;
const char *wl_fw;
};
-extern uint32_t aicbsp_mode_index;
+struct aicbsp_info_t {
+ int hwinfo;
+ int hwinfo_r;
+ uint32_t cpmode;
+ uint32_t chip_rev;
+ bool fwlog_en;
+};
+
+extern struct aicbsp_info_t aicbsp_info;
extern struct mutex aicbsp_power_lock;
-extern const struct aicbsp_firmware aicbsp_firmware_list[];
+extern const struct aicbsp_firmware *aicbsp_firmware_list;
+extern const struct aicbsp_firmware fw_u02[];
+extern const struct aicbsp_firmware fw_u03[];
#endif
--
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