From 830ce1f69238136c0197858242f16cf44e0d6cb9 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 01 Nov 2024 03:09:37 +0000
Subject: [PATCH] gpio config
---
kernel/arch/arm/mm/cache-l2x0.c | 47 +++++++++++++++++++++++++++++++++++++++--------
1 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/kernel/arch/arm/mm/cache-l2x0.c b/kernel/arch/arm/mm/cache-l2x0.c
index 43d91bf..b2af3e0 100644
--- a/kernel/arch/arm/mm/cache-l2x0.c
+++ b/kernel/arch/arm/mm/cache-l2x0.c
@@ -38,7 +38,7 @@
static void __iomem *l2x0_base;
static const struct l2c_init_data *l2x0_data;
-static DEFINE_RAW_SPINLOCK(l2x0_lock);
+static DEFINE_HARD_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
@@ -47,6 +47,19 @@
static bool l2x0_bresp_disable;
static bool l2x0_flz_disable;
+
+#ifdef CONFIG_IRQ_PIPELINE
+#define CACHE_RANGE_ATOMIC_MAX 512UL
+static int l2x0_wa = -1;
+static int __init l2x0_setup_wa(char *str)
+{
+ l2x0_wa = !!simple_strtol(str, NULL, 0);
+ return 0;
+}
+early_param("l2x0_write_allocate", l2x0_setup_wa);
+#else
+#define CACHE_RANGE_ATOMIC_MAX 4096UL
+#endif
/*
* Common code for all cache controllers.
@@ -120,11 +133,11 @@
l2x0_data->unlock(base, num_lock);
- local_irq_save(flags);
+ flags = hard_local_irq_save();
__l2c_op_way(base + L2X0_INV_WAY);
writel_relaxed(0, base + sync_reg_offset);
l2c_wait_mask(base + sync_reg_offset, 1);
- local_irq_restore(flags);
+ hard_local_irq_restore(flags);
l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
}
@@ -225,7 +238,7 @@
{
void __iomem *base = l2x0_base;
- BUG_ON(!irqs_disabled());
+ BUG_ON(!hard_irqs_disabled());
__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
__l2c210_cache_sync(base);
@@ -284,10 +297,10 @@
static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
unsigned long end, unsigned long flags)
{
- raw_spinlock_t *lock = &l2x0_lock;
+ typeof(l2x0_lock) *lock = &l2x0_lock;
while (start < end) {
- unsigned long blk_end = start + min(end - start, 4096UL);
+ unsigned long blk_end = start + min(end - start, CACHE_RANGE_ATOMIC_MAX);
while (start < blk_end) {
l2c_wait_mask(reg, 1);
@@ -498,13 +511,13 @@
static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
{
- raw_spinlock_t *lock = &l2x0_lock;
+ typeof(l2x0_lock) *lock = &l2x0_lock;
unsigned long flags;
void __iomem *base = l2x0_base;
raw_spin_lock_irqsave(lock, flags);
while (start < end) {
- unsigned long blk_end = start + min(end - start, 4096UL);
+ unsigned long blk_end = start + min(end - start, CACHE_RANGE_ATOMIC_MAX);
l2c_set_debug(base, 0x03);
while (start < blk_end) {
@@ -800,6 +813,24 @@
if (aux_val & aux_mask)
pr_alert("L2C: platform provided aux values permit register corruption.\n");
+#ifdef CONFIG_IRQ_PIPELINE
+ if (!l2x0_wa) {
+ /*
+ * Disable WA by setting bit 23 in the auxiliary
+ * control register.
+ */
+ aux_mask &= ~L220_AUX_CTRL_FWA_MASK;
+ aux_val &= ~L220_AUX_CTRL_FWA_MASK;
+ aux_val |= 1 << L220_AUX_CTRL_FWA_SHIFT;
+ pr_warn("%s: irq_pipeline: write-allocate disabled via command line\n",
+ data->type);
+ } else if ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L220 ||
+ ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310 &&
+ (cache_id & L2X0_CACHE_ID_RTL_MASK) < L310_CACHE_ID_RTL_R3P2))
+ pr_alert("%s: irq_pipeline: write-allocate enabled, may induce high latency\n",
+ data->type);
+#endif
+
old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
aux |= aux_val;
--
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