From 2f529f9b558ca1c1bd74be7437a84e4711743404 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 01 Nov 2024 02:11:33 +0000
Subject: [PATCH] add xenomai

---
 kernel/arch/arm64/boot/dts/rockchip/NK-6A13_V0A.dtsi |   99 +++++++++++++++++++++++--------------------------
 1 files changed, 46 insertions(+), 53 deletions(-)

diff --git a/kernel/arch/arm64/boot/dts/rockchip/NK-6A13_V0A.dtsi b/kernel/arch/arm64/boot/dts/rockchip/NK-6A13_V0A.dtsi
index ec9d948..fc812b5 100755
--- a/kernel/arch/arm64/boot/dts/rockchip/NK-6A13_V0A.dtsi
+++ b/kernel/arch/arm64/boot/dts/rockchip/NK-6A13_V0A.dtsi
@@ -27,7 +27,7 @@
 	};
 
 	es8316_sound: es8316-sound {
-		status = "okay";
+		status = "disabled";
 		compatible = "rockchip,multicodecs-card";
 		rockchip,card-name = "rockchip-es8316";
 		rockchip,format = "i2s";
@@ -235,7 +235,7 @@
 		BT,reset_gpio    = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; //BT_DISABLE_GPIO0_B2_u_1V8
 		//BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;//HOST_WAKE_BT_H
 		//BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;//BT_WAKE_HOST_H
-		status = "okay";
+		status = "disabled";
 	};
 
 	wireless_wlan: wireless-wlan {
@@ -245,7 +245,7 @@
 	//	pinctrl-0 = <&wifi_host_wake_irq>;
 	//	WIFI,host_wake_irq = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; //GPIO2_B5_u_1V8_WF-BT_WAKEUP_IN
 	//	WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
-		status = "okay";
+		status = "disabled";
 	};
 	
 	ndj_io_init {
@@ -253,40 +253,15 @@
 			pinctrl-names = "default";
           	pinctrl-0 = <&ndj_io_gpio>;
 									
-			vcc_12v {
-				gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
-				gpio_function = <0>;
-			};//VCC12_IO_EN_GPIO0_D3_u_3V3
-			
-			vcc_3v {
-				gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
-				gpio_function = <0>;
-			};//VCC3_IO_EN_GPIO4_A1_d_3V3
+
 			
            	hub_5V_reset {
 				gpio_num = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 
 				gpio_function = <3>;
 			};//HUB_RESET_GPIO4_B6_d_3V3
 			
-			4g_power {
-				gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-				gpio_function = <0>;
-			};//4G_PWREN_GPIO3_C7_u_3V3
 			
-         	wake_wifi_bt {
-				gpio_num = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
-				gpio_function = <0>;
-			};//GPIO2_B5_u_1V8_WF-BT_WAKEUP_IN
 			
-			air_mode_4g {
-				gpio_num = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>;
-				gpio_function = <0>;
-			};	//GPIO2_B4_u_1V8_4G_AIR_MODE_IN		
-			
-			reset_4g {
-				gpio_num = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
-				gpio_function = <3>;
-			};	//GPIO2_C3_d_1V8_4G_RESET_N_IN
 		};
 		
 		
@@ -432,7 +407,7 @@
 };
 
 &dsi0_in_vp3 {
-	status = "okay";
+	status = "disabled";
 };
 
 /*
@@ -465,6 +440,31 @@
 	//pinctrl-0 = <&lcd_rst_gpio>;
 };
 
+&gmac0 {
+	/* Use rgmii-rxid mode to disable rx delay inside Soc */
+	phy-mode = "rgmii-rxid";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+                     &gmac0_tx_bus2
+                     &gmac0_rx_bus2
+                     &gmac0_rgmii_clk
+                     &gmac0_rgmii_bus
+                     &eth0_pins
+		     &gmac0_clkinout>;
+	tx_delay = <0x44>;
+	/* rx_delay = <0x4f>; */
+
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
 &gmac1 {
 	/* Use rgmii-rxid mode to disable rx delay inside Soc */
 	phy-mode = "rgmii-rxid";
@@ -485,7 +485,7 @@
 	tx_delay = <0x43>;
 	/* rx_delay = <0x3f>; */
 
-	phy-handle = <&rgmii_phy>;
+	phy-handle = <&rgmii_phy1>;
 	status = "okay";
 };
 
@@ -517,7 +517,7 @@
 
 /* Should work with at least 128MB cma reserved above. */
 &hdmirx_ctrler {
-	status = "okay";
+	status = "disabled";
 
 	#sound-dai-cells = <1>;
 	/* Effective level used to trigger HPD: 0-low, 1-high */
@@ -817,12 +817,18 @@
 };
 
 &mdio1 {
-	rgmii_phy: phy@1 {
+	rgmii_phy1: phy@1 {
 		compatible = "ethernet-phy-ieee802.3-c22";
 		reg = <0x1>;
 	};
 };
 
+&mdio0 {
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
 
 
 &mipi_dcphy1 {
@@ -831,7 +837,7 @@
 
 &pcie2x1l2 {
 	phys = <&combphy0_ps PHY_TYPE_PCIE>;
-	reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;//PCIE20x1_2_RSTn_GPIO3_D0_3V3
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;//PCIE20x1_2_RSTn_GPIO3_D0_3V3
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };//MINIPCIE
@@ -969,20 +975,7 @@
 	ndj_io_init{
 		ndj_io_gpio: ndj_io_gpio_col{
 				rockchip,pins =
-					<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
-					<4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,
-					<4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,
-					<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,
-					<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
-					<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
-					<4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,  //vcc_5v				
-					<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI0_MISO_M2_1V8 41
-					<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI4_MISO_M2_1V8 32
-					<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI0_MOSI_M2_3V3 42
-					<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI4_MOSI_M2_1V8 33
-					<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI0_CLK_M2_1V8  43 
-					<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI4_CLK_M2_1V8  34
-					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,  //SPI0_CS0_M2_1V8  44
+				
 					<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;  //SPI4_CS0_M2_1V8  35		 		
 		};
 	};
@@ -1042,7 +1035,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdiom0_pins>;
 	sd-uhs-sdr104;
-	status = "okay";
+	status = "disabled";
 };
 
 &sdmmc {
@@ -1102,7 +1095,7 @@
 #endif
 
 &uart1 {
-	status = "okay";
+	status = "disabled";
 //	dma-names = "tx", "rx"; //ʹ��dma����ģʽ
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1m0_xfer>;
@@ -1116,7 +1109,7 @@
 
 
 &uart4 {
-	status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart4m0_xfer>;
 };
@@ -1134,7 +1127,7 @@
 };
 
 &uart7 {
-	status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart7m1_xfer>;
 };
@@ -1147,7 +1140,7 @@
 
 
 &uart9 {
-	status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;	
 };

--
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