From f45e756958099c35d6afb746df1d40a1c6302cfc Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 07 Nov 2023 06:20:23 +0000
Subject: [PATCH] enable wifi gpio
---
u-boot/drivers/pci/pcie_dw_rockchip.c | 63 ++++++++++++++++++++++++++-----
1 files changed, 52 insertions(+), 11 deletions(-)
diff --git a/u-boot/drivers/pci/pcie_dw_rockchip.c b/u-boot/drivers/pci/pcie_dw_rockchip.c
index 27312d1..dd81acf 100644
--- a/u-boot/drivers/pci/pcie_dw_rockchip.c
+++ b/u-boot/drivers/pci/pcie_dw_rockchip.c
@@ -18,8 +18,41 @@
#include <asm-generic/gpio.h>
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
+#include <linux/ioport.h>
DECLARE_GLOBAL_DATA_PTR;
+
+#define RK_PCIE_DBG 0
+
+#define __pcie_dev_print_emit(fmt, ...) \
+({ \
+ printf(fmt, ##__VA_ARGS__); \
+})
+
+#ifdef dev_err
+#undef dev_err
+#define dev_err(dev, fmt, ...) \
+({ \
+ if (dev) \
+ __pcie_dev_print_emit("%s: " fmt, dev->name, \
+ ##__VA_ARGS__); \
+})
+#endif
+
+#ifdef dev_info
+#undef dev_info
+#define dev_info dev_err
+#endif
+
+#ifdef DEBUG
+#define dev_dbg dev_err
+#else
+#define dev_dbg(dev, fmt, ...) \
+({ \
+ if (0) \
+ __dev_printk(7, dev, fmt, ##__VA_ARGS__); \
+})
+#endif
struct rk_pcie {
struct udevice *dev;
@@ -62,7 +95,6 @@
#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
#define PCIE_CLIENT_DBF_EN 0xffff0003
-#define RK_PCIE_DBG 0
/* PCI DBICS registers */
#define PCIE_LINK_STATUS_REG 0x80
@@ -119,6 +151,8 @@
#define LINK_WAIT_MAX_IATU_RETRIES 5
#define LINK_WAIT_IATU 10000
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000
+
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
@@ -165,7 +199,7 @@
ret = rk_pcie_read(base + reg, size, &val);
if (ret)
- dev_err(rk_pcie->pci->dev, "Read APB address failed\n");
+ dev_err(rk_pcie->dev, "Read APB address failed\n");
return val;
}
@@ -177,7 +211,7 @@
ret = rk_pcie_write(base + reg, size, val);
if (ret)
- dev_err(rk_pcie->pci->dev, "Write APB address failed\n");
+ dev_err(rk_pcie->dev, "Write APB address failed\n");
}
static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
@@ -272,6 +306,10 @@
val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
val |= PORT_LOGIC_SPEED_CHANGE;
writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+
+ /* Disable BAR0 BAR1 */
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);
rk_pcie_dbi_write_enable(rk_pcie, false);
}
@@ -469,10 +507,10 @@
#if RK_PCIE_DBG
u32 loop;
- dev_info(rk_pcie->dev, "ltssm = 0x%x\n",
+ dev_err(rk_pcie->dev, "ltssm = 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
for (loop = 0; loop < 64; loop++)
- dev_info(rk_pcie->dev, "fifo_status = 0x%x\n",
+ dev_err(rk_pcie->dev, "fifo_status = 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
#endif
}
@@ -641,17 +679,18 @@
struct rk_pcie *priv = dev_get_priv(dev);
u32 max_link_speed;
int ret;
+ struct resource res;
- priv->dbi_base = (void *)dev_read_addr_index(dev, 0);
- if (!priv->dbi_base)
+ ret = dev_read_resource_byname(dev, "pcie-dbi", &res);
+ if (ret)
return -ENODEV;
-
+ priv->dbi_base = (void *)(res.start);
dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);
- priv->apb_base = (void *)dev_read_addr_index(dev, 1);
- if (!priv->apb_base)
+ ret = dev_read_resource_byname(dev, "pcie-apb", &res);
+ if (ret)
return -ENODEV;
-
+ priv->apb_base = (void *)(res.start);
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
ret = gpio_request_by_name(dev, "reset-gpios", 0,
@@ -771,6 +810,8 @@
};
static const struct udevice_id rockchip_pcie_ids[] = {
+ { .compatible = "rockchip,rk3528-pcie" },
+ { .compatible = "rockchip,rk3562-pcie" },
{ .compatible = "rockchip,rk3568-pcie" },
{ .compatible = "rockchip,rk3588-pcie" },
{ }
--
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