From e3e12f52b214121840b44c91de5b3e5af5d3eb84 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 03:04:41 +0000
Subject: [PATCH] rk3568 rt init
---
kernel/drivers/soc/rockchip/pm_domains.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/kernel/drivers/soc/rockchip/pm_domains.c b/kernel/drivers/soc/rockchip/pm_domains.c
index 6c5aa46..d5cc4f0 100644
--- a/kernel/drivers/soc/rockchip/pm_domains.c
+++ b/kernel/drivers/soc/rockchip/pm_domains.c
@@ -37,6 +37,7 @@
#include <dt-bindings/power/rk3366-power.h>
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/power/rk3399-power.h>
+#include <dt-bindings/power/rk3528-power.h>
#include <dt-bindings/power/rk3568-power.h>
struct rockchip_domain_info {
@@ -146,6 +147,20 @@
.keepon_startup = keepon, \
}
+#define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon) \
+{ \
+ .pwr_w_mask = (pwr) << 16, \
+ .pwr_mask = (pwr), \
+ .status_mask = (status), \
+ .req_w_mask = (req) << 16, \
+ .req_mask = (req), \
+ .idle_mask = (idle), \
+ .ack_mask = (ack), \
+ .always_on = always, \
+ .active_wakeup = wakeup, \
+ .keepon_startup = keepon, \
+}
+
#define DOMAIN_M_O(pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \
{ \
.pwr_w_mask = (pwr) << 16, \
@@ -205,6 +220,9 @@
#define DOMAIN_RK3399_PROTECT(pwr, status, req, wakeup) \
DOMAIN(pwr, status, req, req, req, wakeup, true)
+
+#define DOMAIN_RK3528(pwr, req, always, wakeup) \
+ DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
#define DOMAIN_RK3568(pwr, req, wakeup) \
DOMAIN_M(pwr, pwr, req, req, req, wakeup, false)
@@ -1357,6 +1375,18 @@
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
};
+static const struct rockchip_domain_info rk3528_pm_domains[] = {
+ [RK3528_PD_PMU] = DOMAIN_RK3528(0, BIT(0), true, false),
+ [RK3528_PD_BUS] = DOMAIN_RK3528(0, BIT(1), true, false),
+ [RK3528_PD_DDR] = DOMAIN_RK3528(0, BIT(2), true, false),
+ [RK3528_PD_MSCH] = DOMAIN_RK3528(0, BIT(3), true, false),
+ [RK3528_PD_GPU] = DOMAIN_RK3528(BIT(0), BIT(4), true, false),
+ [RK3528_PD_RKVDEC] = DOMAIN_RK3528(0, BIT(5), true, false),
+ [RK3528_PD_RKVENC] = DOMAIN_RK3528(0, BIT(6), true, false),
+ [RK3528_PD_VO] = DOMAIN_RK3528(0, BIT(7), true, false),
+ [RK3528_PD_VPU] = DOMAIN_RK3528(0, BIT(8), true, false),
+};
+
static const struct rockchip_domain_info rk3568_pm_domains[] = {
[RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
[RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
@@ -1508,6 +1538,17 @@
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3528_pmu = {
+ .pwr_offset = 0x1210,
+ .status_offset = 0x1230,
+ .req_offset = 0x1110,
+ .idle_offset = 0x1128,
+ .ack_offset = 0x1120,
+
+ .num_domains = ARRAY_SIZE(rk3528_pm_domains),
+ .domain_info = rk3528_pm_domains,
+};
+
static const struct rockchip_pmu_info rk3568_pmu = {
.pwr_offset = 0xa0,
.status_offset = 0x98,
@@ -1586,6 +1627,12 @@
.data = (void *)&rk3399_pmu,
},
#endif
+#ifdef CONFIG_CPU_RK3528
+ {
+ .compatible = "rockchip,rk3528-power-controller",
+ .data = (void *)&rk3528_pmu,
+ },
+#endif
#ifdef CONFIG_CPU_RK3568
{
.compatible = "rockchip,rk3568-power-controller",
--
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