From e3e12f52b214121840b44c91de5b3e5af5d3eb84 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Mon, 06 Nov 2023 03:04:41 +0000 Subject: [PATCH] rk3568 rt init --- kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 168 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 167 insertions(+), 1 deletions(-) diff --git a/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 7fb5abb..0681e3e 100644 --- a/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1091,6 +1091,7 @@ #define RK3568_VP0_DSP_CTRL 0xC00 #define RK3568_VP0_MIPI_CTRL 0xC04 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 +#define RK3568_VP0_DCLK_SEL 0xC0C #define RK3568_VP0_3D_LUT_CTRL 0xC10 #define RK3568_VP0_3D_LUT_MST 0xC20 #define RK3568_VP0_DSP_BG 0xC2C @@ -1110,6 +1111,16 @@ #define RK3568_VP0_BCSH_BCS 0xC64 #define RK3568_VP0_BCSH_H 0xC68 #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C +#define RK3528_VP0_ACM_CTRL 0xCD0 +#define RK3528_VP0_CSC_COE01_02 0xCD4 +#define RK3528_VP0_CSC_COE10_11 0xCD8 +#define RK3528_VP0_CSC_COE12_20 0xCDC +#define RK3528_VP0_CSC_COE21_22 0xCE0 +#define RK3528_VP0_CSC_OFFSET0 0xCE4 +#define RK3528_VP0_CSC_OFFSET1 0xCE8 +#define RK3528_VP0_CSC_OFFSET2 0xCEC +#define RK3528_VP0_MCU_CTRL 0xCF8 +#define RK3528_VP0_MCU_RW_BYPASS_PORT 0xCFC #define RK3568_VP1_DSP_CTRL 0xD00 #define RK3568_VP1_MIPI_CTRL 0xD04 @@ -1133,6 +1144,8 @@ #define RK3568_VP1_BCSH_BCS 0xD64 #define RK3568_VP1_BCSH_H 0xD68 #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C +#define RK3528_VP1_MCU_CTRL 0xDF8 +#define RK3528_VP1_MCU_RW_BYPASS_PORT 0xDFC #define RK3568_VP2_DSP_CTRL 0xE00 #define RK3568_VP2_MIPI_CTRL 0xE04 @@ -1157,7 +1170,76 @@ #define RK3568_VP2_BCSH_H 0xE68 #define RK3568_VP2_BCSH_COLOR_BAR 0xE6C -/* Overlay registers definition */ +#define RK3588_VP3_DSP_CTRL 0xF00 +#define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04 +#define RK3588_VP3_COLOR_BAR_CTRL 0xF08 +#define RK3568_VP3_CLK_CTRL 0xF0C +#define RK3588_VP3_DSP_BG 0xF2C +#define RK3588_VP3_PRE_SCAN_HTIMING 0xF30 +#define RK3588_VP3_POST_DSP_HACT_INFO 0xF34 +#define RK3588_VP3_POST_DSP_VACT_INFO 0xF38 +#define RK3588_VP3_POST_SCL_FACTOR_YRGB 0xF3C +#define RK3588_VP3_POST_SCL_CTRL 0xF40 +#define RK3588_VP3_DSP_HACT_INFO 0xF34 +#define RK3588_VP3_DSP_VACT_INFO 0xF38 +#define RK3588_VP3_POST_DSP_VACT_INFO_F1 0xF44 +#define RK3588_VP3_DSP_HTOTAL_HS_END 0xF48 +#define RK3588_VP3_DSP_HACT_ST_END 0xF4C +#define RK3588_VP3_DSP_VTOTAL_VS_END 0xF50 +#define RK3588_VP3_DSP_VACT_ST_END 0xF54 +#define RK3588_VP3_DSP_VS_ST_END_F1 0xF58 +#define RK3588_VP3_DSP_VACT_ST_END_F1 0xF5C +#define RK3588_VP3_BCSH_CTRL 0xF60 +#define RK3588_VP3_BCSH_BCS 0xF64 +#define RK3588_VP3_BCSH_H 0xF68 +#define RK3588_VP3_BCSH_COLOR_BAR 0xF6C +#define RK3528_OVL_SYS 0x500 +#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504 +#define RK3528_OVL_SYS_GATING_EN_IMD 0x508 +#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510 +#define RK3528_OVL_SYS_ESMART0_CTRL 0x520 +#define RK3528_OVL_SYS_ESMART1_CTRL 0x524 +#define RK3528_OVL_SYS_ESMART2_CTRL 0x528 +#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C +#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530 +#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534 +#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538 +#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c +#define RK3528_OVL_PORT0_CTRL 0x600 +#define RK3528_OVL_PORT0_LAYER_SEL 0x604 +#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620 +#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624 +#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628 +#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C +#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630 +#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634 +#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638 +#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C +#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640 +#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644 +#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648 +#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C +#define RK3528_HDR_SRC_COLOR_CTRL 0x660 +#define RK3528_HDR_DST_COLOR_CTRL 0x664 +#define RK3528_HDR_SRC_ALPHA_CTRL 0x668 +#define RK3528_HDR_DST_ALPHA_CTRL 0x66C +#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670 +#define RK3528_OVL_PORT1_CTRL 0x700 +#define RK3528_OVL_PORT1_LAYER_SEL 0x704 +#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720 +#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724 +#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728 +#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C +#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730 +#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734 +#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738 +#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C +#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740 +#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744 +#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748 +#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C +#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770 + #define RK3568_OVL_CTRL 0x600 #define RK3568_OVL_LAYER_SEL 0x604 #define RK3568_OVL_PORT_SEL 0x608 @@ -1186,6 +1268,8 @@ /* Cluster0 register definition */ #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 +#define RK3528_CLUSTER0_WIN0_CTRL1 0x1004 +#define RK3528_CLUSTER0_WIN0_CTRL2 0x1008 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 @@ -1205,6 +1289,8 @@ #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3528_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3528_CLUSTER0_WIN1_CTRL2 0x1088 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 @@ -1265,6 +1351,7 @@ /* Esmart register definition */ #define RK3568_ESMART0_CTRL0 0x1800 #define RK3568_ESMART0_CTRL1 0x1804 +#define RK3568_ESMART0_AXI_CTRL 0x1808 #define RK3568_ESMART0_REGION0_CTRL 0x1810 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 @@ -1466,4 +1553,83 @@ #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 #define RK3568_HDR_OETF_DX_POW1 0x2200 #define RK3568_HDR_OETF_XN1 0x2300 + +/* RK3528 HDR register definition */ +#define RK3528_HDR_LUT_CTRL 0x2000 +#define RK3528_HDR_LUT_MST 0x2004 +#define RK3528_HDR_LUT_STATUS 0x2008 +#define RK3528_SDR2HDR_CTRL 0x2010 +#define RK3528_SDR_CFG_COE0 0x2014 +#define RK3528_SDR_CFG_COE1 0x2018 +#define RK3528_SDR_CSC_COE00_01 0x201C +#define RK3528_SDR_CSC_COE02_10 0x2020 +#define RK3528_SDR_CSC_COE11_12 0x2024 +#define RK3528_SDR_CSC_COE20_21 0x2028 +#define RK3528_SDR_CSC_COE22 0x202C +#define RK3528_HDRVIVID_CTRL 0x2040 +#define RK3528_HDR_PQ_GAMMA 0x2044 +#define RK3528_HLG_RFIX_SCALEFAC 0x2048 +#define RK3528_HLG_MAXLUMA 0x204C +#define RK3528_HLG_R_TM_LIN2NON 0x2050 +#define RK3528_HDR_CSC_COE00_01 0x2054 +#define RK3528_HDR_CSC_COE02_10 0x2058 +#define RK3528_HDR_CSC_COE11_12 0x205C +#define RK3528_HDR_CSC_COE20_21 0x2060 +#define RK3528_HDR_CSC_COE22 0x2064 +#define RK3528_INK_CFG 0x2080 +#define RK3528_INK_POINT0_CFG 0x2084 +#define RK3528_INK_POINT1_CFG 0x2088 +#define RK3528_INK_POINT0_R0 0x208C +#define RK3528_INK_POINT0_G0 0x2090 +#define RK3528_INK_POINT0_B0 0x2094 +#define RK3528_INK_POINT0_R1 0x2098 +#define RK3528_INK_POINT0_G1 0x209C +#define RK3528_INK_POINT0_B1 0x20A0 +#define RK3528_INK_POINT1_R0 0x20A4 +#define RK3528_INK_POINT1_G0 0x20A8 +#define RK3528_INK_POINT1_B0 0x20AC +#define RK3528_INK_POINT1_R1 0x20B0 +#define RK3528_INK_POINT1_G1 0x20B4 +#define RK3528_INK_POINT1_B1 0x20B8 +#define RK3528_HDR_TONE_SCA 0x213C +#define RK3528_HDRGAMMA_CURVE 0x2540 +#define RK3528_HDRGAMMA_MDFVALUE 0x2690 +#define RK3528_SDRINVGAMMA_CURVE 0x2700 +#define RK3528_SDRINVGAMMA_STARTIDX 0x2820 +#define RK3528_SDRINVGAMMA_CHANGEIDX 0x2840 +#define RK3528_SDR_SMGAIN 0x2900 + +/* RK3588 ACM register definition */ +#define RK3528_ACM_CTRL 0x0000 +#define RK3528_ACM_ENABLE BIT(0) +#define RK3528_ACM_BYPASS BIT(1) +#define RK3528_ACM_DELTA_RANGE 0x0004 +#define RK3528_ACM_FETCH_START 0x0008 +#define RK3528_ACM_DEBUG_POINT0 0x0010 +#define RK3528_ACM_DEBUG_POINT1 0x0014 +#define RK3528_ACM_DEBUG_POINT2 0x0018 +#define RK3528_ACM_DEBUG_POINT3 0x001c +#define RK3528_ACM_FETCH_DONE 0x0020 +#define RK3528_ACM_DEBUG0_DATA0 0x0030 +#define RK3528_ACM_DEBUG0_DATA1 0x0034 +#define RK3528_ACM_DEBUG0_DATA2 0x0038 +#define RK3528_ACM_DEBUG0_DATA3 0x003c +#define RK3528_ACM_DEBUG1_DATA0 0x0040 +#define RK3528_ACM_DEBUG1_DATA1 0x0044 +#define RK3528_ACM_DEBUG1_DATA2 0x0048 +#define RK3528_ACM_DEBUG1_DATA3 0x004c +#define RK3528_ACM_DEBUG2_DATA0 0x0050 +#define RK3528_ACM_DEBUG2_DATA1 0x0054 +#define RK3528_ACM_DEBUG2_DATA2 0x0058 +#define RK3528_ACM_DEBUG2_DATA3 0x005c +#define RK3528_ACM_DEBUG3_DATA0 0x0060 +#define RK3528_ACM_DEBUG3_DATA1 0x0064 +#define RK3528_ACM_DEBUG3_DATA2 0x0068 +#define RK3528_ACM_DEBUG3_DATA3 0x006c +#define RK3528_ACM_YHS_DEL_HY_SEG0 0x0100 +#define RK3528_ACM_YHS_DEL_HY_SEG152 0x0360 +#define RK3528_ACM_YHS_DEL_HS_SEG0 0x0364 +#define RK3528_ACM_YHS_DEL_HS_SEG220 0x06d4 +#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x06d8 +#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x07d8 #endif /* _ROCKCHIP_VOP_REG_H */ -- Gitblit v1.6.2