From e3e12f52b214121840b44c91de5b3e5af5d3eb84 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 03:04:41 +0000
Subject: [PATCH] rk3568 rt init
---
kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 140 insertions(+), 5 deletions(-)
diff --git a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index ae92b87..a0677dd 100644
--- a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,6 +24,7 @@
#define VOP_MAJOR(version) ((version) >> 8)
#define VOP_MINOR(version) ((version) & 0xff)
+#define VOP_VERSION_RK3528 VOP_VERSION(0x50, 0x17)
#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
@@ -42,6 +43,9 @@
/* a feature to splice two windows and two vps to support resolution > 4096 */
#define VOP_FEATURE_SPLICE BIT(5)
#define VOP_FEATURE_OVERSCAN BIT(6)
+#define VOP_FEATURE_VIVID_HDR BIT(7)
+#define VOP_FEATURE_POST_ACM BIT(8)
+#define VOP_FEATURE_POST_CSC BIT(9)
#define WIN_FEATURE_HDR2SDR BIT(0)
#define WIN_FEATURE_SDR2HDR BIT(1)
@@ -92,10 +96,10 @@
};
enum vop3_esmart_lb_mode {
- VOP3_ESMART_ONE_8K_MODE,
- VOP3_ESMART_TWO_4K_MODE,
- VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
- VOP3_ESMART_FOUR_2K_MODE,
+ VOP3_ESMART_8K_MODE,
+ VOP3_ESMART_4K_4K_MODE,
+ VOP3_ESMART_4K_2K_2K_MODE,
+ VOP3_ESMART_2K_2K_2K_2K_MODE,
};
#define DSP_BG_SWAP 0x1
@@ -439,6 +443,104 @@
const uint32_t *sdr2hdr_st2084oetf_xn;
};
+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
+#define RK_SDR2HDR_SMGAIN_LENGTH 64
+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
+
+struct hdrvivid_regs {
+ uint32_t sdr2hdr_ctrl;
+ uint32_t sdr2hdr_coe0;
+ uint32_t sdr2hdr_coe1;
+ uint32_t sdr2hdr_csc_coe00_01;
+ uint32_t sdr2hdr_csc_coe02_10;
+ uint32_t sdr2hdr_csc_coe11_12;
+ uint32_t sdr2hdr_csc_coe20_21;
+ uint32_t sdr2hdr_csc_coe22;
+ uint32_t hdrvivid_ctrl;
+ uint32_t hdr_pq_gamma;
+ uint32_t hlg_rfix_scalefac;
+ uint32_t hlg_maxluma;
+ uint32_t hlg_r_tm_lin2non;
+ uint32_t hdr_csc_coe00_01;
+ uint32_t hdr_csc_coe02_10;
+ uint32_t hdr_csc_coe11_12;
+ uint32_t hdr_csc_coe20_21;
+ uint32_t hdr_csc_coe22;
+ uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
+ uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
+ uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
+ uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
+ uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
+ uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
+ uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
+ uint32_t hdr_mode;
+ uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
+};
+
+struct hdr_extend {
+ uint32_t hdr_type;
+ uint32_t length;
+ union {
+ struct hdrvivid_regs hdrvivid_data;
+ };
+};
+
+enum _vop_hdrvivid_mode {
+ PQHDR2HDR_WITH_DYNAMIC = 0,
+ PQHDR2SDR_WITH_DYNAMIC,
+ HLG2PQHDR_WITH_DYNAMIC,
+ HLG2SDR_WITH_DYNAMIC,
+ HLG2PQHDR_WITHOUT_DYNAMIC,
+ HLG2SDR_WITHOUT_DYNAMIC,
+ HDR_BYPASS,
+ HDR102SDR,
+ SDR2HDR10,
+ SDR2HLG,
+ SDR2HDR10_USERSPACE = 100,
+ SDR2HLG_USERSPACE = 101,
+};
+
+enum vop_hdr_format {
+ HDR_NONE = 0,
+ HDR_HDR10 = 1,
+ HDR_HLGSTATIC = 2,
+ RESERVED3 = 3, /* reserved for more future static hdr format */
+ RESERVED4 = 4, /* reserved for more future static hdr format */
+ HDR_HDRVIVID = 5,
+ RESERVED6 = 6, /* reserved for hdr vivid */
+ RESERVED7 = 7, /* reserved for hdr vivid */
+ HDR_HDR10PLUS = 8,
+ RESERVED9 = 9, /* reserved for hdr hdr10+ */
+ RESERVED10 = 10, /* reserved for hdr hdr10+ */
+ HDR_NEXT = 11,
+ RESERVED12 = 12, /* reserved for other dynamic hdr format */
+ RESERVED13 = 13, /* reserved for other dynamic hdr format */
+ HDR_FORMAT_MAX,
+};
+
+struct post_csc_coef {
+ s32 csc_coef00;
+ s32 csc_coef01;
+ s32 csc_coef02;
+ s32 csc_coef10;
+ s32 csc_coef11;
+ s32 csc_coef12;
+ s32 csc_coef20;
+ s32 csc_coef21;
+ s32 csc_coef22;
+
+ s32 csc_dc0;
+ s32 csc_dc1;
+ s32 csc_dc2;
+
+ u32 range_type;
+};
+
enum {
VOP_CSC_Y2R_BT601,
VOP_CSC_Y2R_BT709,
@@ -509,6 +611,8 @@
struct vop_reg enable;
struct vop_reg afbc_enable;
struct vop_reg lb_mode;
+ struct vop_reg scl_lb_mode;
+ struct vop_reg frm_reset_en;
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
@@ -626,6 +730,13 @@
struct vop_reg hdr_lut_update_en;
struct vop_reg hdr_lut_mode;
struct vop_reg hdr_lut_mst;
+ struct vop_reg hdr_lut_fetch_done;
+ struct vop_reg hdr_vivid_en;
+ struct vop_reg hdr_vivid_bypass_en;
+ struct vop_reg hdr_vivid_path_mode;
+ struct vop_reg hdr_vivid_dstgamut;
+ struct vop_reg sdr2hdr_en;
+ struct vop_reg sdr2hdr_dstmode;
struct vop_reg sdr2hdr_eotf_en;
struct vop_reg sdr2hdr_r2r_en;
struct vop_reg sdr2hdr_r2r_mode;
@@ -677,6 +788,25 @@
struct vop_reg edpi_wms_fs;
struct vop_reg gamma_update_en;
struct vop_reg lut_dma_rid;
+
+ /* CSC */
+ struct vop_reg acm_bypass_en;
+ struct vop_reg csc_en;
+ struct vop_reg acm_r2y_en;
+ struct vop_reg csc_mode;
+ struct vop_reg acm_r2y_mode;
+ struct vop_reg csc_coe00;
+ struct vop_reg csc_coe01;
+ struct vop_reg csc_coe02;
+ struct vop_reg csc_coe10;
+ struct vop_reg csc_coe11;
+ struct vop_reg csc_coe12;
+ struct vop_reg csc_coe20;
+ struct vop_reg csc_coe21;
+ struct vop_reg csc_coe22;
+ struct vop_reg csc_offset0;
+ struct vop_reg csc_offset1;
+ struct vop_reg csc_offset2;
};
struct vop2_wb_regs {
@@ -711,7 +841,6 @@
uint8_t axi_id;
uint8_t axi_yrgb_id;
uint8_t axi_uv_id;
- uint8_t scale_engine_num;
uint8_t possible_crtcs;
uint32_t base;
@@ -775,6 +904,11 @@
uint16_t cubic_lut_len;
struct vop_rect max_output;
const u8 pre_scan_max_dly[4];
+ const u8 hdrvivid_dly[10];
+ const u8 sdr2hdr_dly;
+ const u8 layer_mix_dly;
+ const u8 hdr_mix_dly;
+ const u8 win_dly;
const struct vop_intr *intr;
const struct vop_hdr_table *hdr_table;
const struct vop2_video_port_regs *regs;
@@ -849,6 +983,7 @@
struct vop_reg version;
struct vop_reg standby;
struct vop_reg dma_stop;
+ struct vop_reg dsp_vs_t_sel;
struct vop_reg lut_dma_en;
struct vop_reg axi_outstanding_max_num;
struct vop_reg axi_max_outstanding_en;
--
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