From e3e12f52b214121840b44c91de5b3e5af5d3eb84 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Mon, 06 Nov 2023 03:04:41 +0000 Subject: [PATCH] rk3568 rt init --- kernel/drivers/clk/rockchip/clk-rk3568.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/drivers/clk/rockchip/clk-rk3568.c b/kernel/drivers/clk/rockchip/clk-rk3568.c index 73dda8e..bf83b6d 100644 --- a/kernel/drivers/clk/rockchip/clk-rk3568.c +++ b/kernel/drivers/clk/rockchip/clk-rk3568.c @@ -1421,21 +1421,21 @@ RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, + RK3568_CLKSEL_CON(72), 8, 2, MFLAGS, RK3568_CLKGATE_CON(31), 11, GFLAGS), GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 12, GFLAGS), GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 13, GFLAGS), COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, + RK3568_CLKSEL_CON(72), 10, 2, MFLAGS, RK3568_CLKGATE_CON(31), 14, GFLAGS), GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, RK3568_CLKGATE_CON(31), 15, GFLAGS), GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, RK3568_CLKGATE_CON(32), 0, GFLAGS), COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, + RK3568_CLKSEL_CON(72), 12, 2, MFLAGS, RK3568_CLKGATE_CON(32), 1, GFLAGS), GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, RK3568_CLKGATE_CON(32), 2, GFLAGS), -- Gitblit v1.6.2