From 9df731a176aab8e03b984b681b1bea01ccff6644 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 07:23:06 +0000
Subject: [PATCH] rk3568 rt uboot init
---
u-boot/drivers/thermal/rockchip_thermal.c | 283 +++++++++++++++++++++++++++++++++++++++++++++++++++++---
1 files changed, 266 insertions(+), 17 deletions(-)
diff --git a/u-boot/drivers/thermal/rockchip_thermal.c b/u-boot/drivers/thermal/rockchip_thermal.c
index 1bd6e31..e5551d4 100644
--- a/u-boot/drivers/thermal/rockchip_thermal.c
+++ b/u-boot/drivers/thermal/rockchip_thermal.c
@@ -78,6 +78,7 @@
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV3_AUTO_PERIOD 0x154
#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV3_Q_MAX 0x210
#define TSADCV2_AUTO_EN BIT(0)
#define TSADCV2_AUTO_EN_MASK BIT(16)
@@ -88,6 +89,7 @@
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
@@ -101,6 +103,7 @@
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
#define TSADCV4_DATA_MASK 0x1ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
@@ -112,6 +115,14 @@
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
+#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
+#define TSADCV9_Q_MAX 0x210
+#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -123,7 +134,10 @@
#define PX30_GRF_SOC_CON0 0x0400
#define PX30_GRF_SOC_CON2 0x0408
+#define RK3562_GRF_TSADC_CON 0x0580
+
#define RK3568_GRF_TSADC_CON 0x0600
+#define RK3528_GRF_TSADC_CON 0x40030
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
@@ -137,9 +151,10 @@
#define GRF_CON_TSADC_CH_INV (0x10001 << 1)
#define PX30S_TSADC_TDC_MODE (0x10001 << 4)
-#define MIN_TEMP (-40000)
+/* -40 to 125 is reliable, outside the range existed unreliability */
+#define MIN_TEMP (-60000)
#define LOWEST_TEMP (-273000)
-#define MAX_TEMP (125000)
+#define MAX_TEMP (180000)
#define MAX_ENV_TEMP (85000)
#define BASE (1024)
@@ -208,7 +223,8 @@
};
static const struct tsadc_table rk1808_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {3423, MIN_TEMP},
{3455, -40000},
{3463, -35000},
{3471, -30000},
@@ -243,11 +259,13 @@
{3709, 115000},
{3718, 120000},
{3726, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3820, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3228_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {568, MIN_TEMP},
{588, -40000},
{593, -35000},
{598, -30000},
@@ -282,11 +300,13 @@
{749, 115000},
{754, 120000},
{760, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {821, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3288_code_table[] = {
- {TSADCV2_DATA_MASK, -40000},
+ {TSADCV2_DATA_MASK, MIN_TEMP},
+ {3833, MIN_TEMP},
{3800, -40000},
{3792, -35000},
{3783, -30000},
@@ -321,10 +341,15 @@
{3452, 115000},
{3437, 120000},
{3421, 125000},
+ {3350, 145000},
+ {3270, 165000},
+ {3195, MAX_TEMP},
+ {0, MAX_TEMP},
};
static const struct tsadc_table rk3328_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {261, MIN_TEMP},
{296, -40000},
{304, -35000},
{313, -30000},
@@ -358,11 +383,15 @@
{644, 115000},
{659, 120000},
{675, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {745, 145000},
+ {825, 165000},
+ {900, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3368_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {98, MIN_TEMP},
{106, -40000},
{108, -35000},
{110, -30000},
@@ -397,11 +426,13 @@
{167, 115000},
{169, 120000},
{171, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {193, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3399_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {368, MIN_TEMP},
{402, -40000},
{410, -35000},
{419, -30000},
@@ -436,11 +467,95 @@
{668, 115000},
{677, 120000},
{685, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {782, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
+};
+
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, MIN_TEMP},
+ {1386, MIN_TEMP},
+ {1419, -40000},
+ {1427, -35000},
+ {1435, -30000},
+ {1443, -25000},
+ {1452, -20000},
+ {1460, -15000},
+ {1468, -10000},
+ {1477, -5000},
+ {1486, 0},
+ {1494, 5000},
+ {1502, 10000},
+ {1510, 15000},
+ {1519, 20000},
+ {1527, 25000},
+ {1535, 30000},
+ {1544, 35000},
+ {1552, 40000},
+ {1561, 45000},
+ {1569, 50000},
+ {1578, 55000},
+ {1586, 60000},
+ {1594, 65000},
+ {1603, 70000},
+ {1612, 75000},
+ {1620, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1662, 105000},
+ {1671, 110000},
+ {1679, 115000},
+ {1688, 120000},
+ {1696, 125000},
+ {1790, MAX_TEMP},
+ {TSADCV5_DATA_MASK, MAX_TEMP},
+};
+
+static const struct tsadc_table rk3562_code_table[] = {
+ {0, MIN_TEMP},
+ {1385, MIN_TEMP},
+ {1419, -40000},
+ {1428, -35000},
+ {1436, -30000},
+ {1445, -25000},
+ {1453, -20000},
+ {1462, -15000},
+ {1470, -10000},
+ {1479, -5000},
+ {1487, 0},
+ {1496, 5000},
+ {1504, 10000},
+ {1512, 15000},
+ {1521, 20000},
+ {1529, 25000},
+ {1538, 30000},
+ {1546, 35000},
+ {1555, 40000},
+ {1563, 45000},
+ {1572, 50000},
+ {1580, 55000},
+ {1589, 60000},
+ {1598, 65000},
+ {1606, 70000},
+ {1615, 75000},
+ {1623, 80000},
+ {1632, 85000},
+ {1640, 90000},
+ {1648, 95000},
+ {1657, 100000},
+ {1666, 105000},
+ {1674, 110000},
+ {1682, 115000},
+ {1691, 120000},
+ {1699, 125000},
+ {1793, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3568_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {1448, MIN_TEMP},
{1584, -40000},
{1620, -35000},
{1652, -30000},
@@ -475,16 +590,19 @@
{2636, 115000},
{2672, 120000},
{2704, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3076, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3588_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {194, MIN_TEMP},
{215, -40000},
{285, 25000},
{350, 85000},
{395, 125000},
- {TSADCV4_DATA_MASK, 125000},
+ {455, MAX_TEMP},
+ {TSADCV4_DATA_MASK, MAX_TEMP},
};
/*
@@ -806,6 +924,81 @@
tsadc_init_v2(dev);
if (!IS_ERR(priv->grf))
writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
+}
+
+static void tsadc_init_v11(struct udevice *dev)
+{
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
+
+ writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
+ writel(TSADCV7_AUTO_PERIOD_HT_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ else
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(priv->grf)) {
+ writel(RK3568_GRF_TSADC_TSEN,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ udelay(15);
+ writel(RK3568_GRF_TSADC_ANA_REG0,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG1,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG2,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ udelay(200);
+ }
+}
+
+static void tsadc_init_v12(struct udevice *dev)
+{
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
+
+ writel(TSADCV12_AUTO_PERIOD_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD);
+ writel(TSADCV12_AUTO_PERIOD_HT_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel(TSADCV12_Q_MAX_VAL,
+ priv->base + TSADCV9_Q_MAX);
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ else
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(priv->grf)) {
+ writel(RK3568_GRF_TSADC_TSEN,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ udelay(15);
+ writel(RK3568_GRF_TSADC_ANA_REG0,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG1,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG2,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ udelay(200);
+ }
}
static int tsadc_get_temp_v2(struct udevice *dev,
@@ -1381,6 +1574,54 @@
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .tsadc_init = tsadc_init_v11,
+ .tsadc_control = tsadc_control_v4,
+ .tsadc_get_temp = tsadc_get_temp_v4,
+ .irq_ack = tsadc_irq_ack_v4,
+ .set_alarm_temp = tsadc_alarm_temp_v3,
+ .set_tshut_temp = tsadc_tshut_temp_v3,
+ .set_tshut_mode = tsadc_tshut_mode_v4,
+
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .tsadc_init = tsadc_init_v12,
+ .tsadc_control = tsadc_control_v4,
+ .tsadc_get_temp = tsadc_get_temp_v4,
+ .irq_ack = tsadc_irq_ack_v4,
+ .set_alarm_temp = tsadc_alarm_temp_v3,
+ .set_tshut_temp = tsadc_tshut_temp_v3,
+ .set_tshut_mode = tsadc_tshut_mode_v4,
+
+ .table = {
+ .id = rk3562_code_table,
+ .length = ARRAY_SIZE(rk3562_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1477,6 +1718,14 @@
.data = (ulong)&rk3399_tsadc_data,
},
{
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (ulong)&rk3528_tsadc_data,
+ },
+ {
+ .compatible = "rockchip,rk3562-tsadc",
+ .data = (ulong)&rk3562_tsadc_data,
+ },
+ {
.compatible = "rockchip,rk3568-tsadc",
.data = (ulong)&rk3568_tsadc_data,
},
--
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