From 2f7c68cb55ecb7331f2381deb497c27155f32faf Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 03 Jan 2024 09:43:39 +0000
Subject: [PATCH] update kernel to 5.10.198
---
kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 566 +++++++++++++++++++++++++++++++++++++++++++++++++++++---
1 files changed, 534 insertions(+), 32 deletions(-)
diff --git a/kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index d18a886..c844328 100644
--- a/kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -59,10 +59,12 @@
struct combphy_reg con2_for_sata;
struct combphy_reg con3_for_sata;
struct combphy_reg pipe_con0_for_sata;
+ struct combphy_reg pipe_con1_for_sata;
struct combphy_reg pipe_sgmii_mac_sel;
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg u3otg0_port_en;
struct combphy_reg u3otg1_port_en;
+ struct combphy_reg pipe_phy_grf_reset;
};
struct rockchip_combphy_cfg {
@@ -251,6 +253,9 @@
if (ret)
goto err_clk;
+ if (cfg->pipe_phy_grf_reset.enable)
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
+
if (priv->mode == PHY_TYPE_USB3) {
ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
priv, val,
@@ -271,6 +276,10 @@
static int rockchip_combphy_exit(struct phy *phy)
{
struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+
+ if (cfg->pipe_phy_grf_reset.enable)
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
reset_control_assert(priv->phy_rst);
@@ -278,9 +287,42 @@
return 0;
}
+static const char *rockchip_combphy_mode2str(enum phy_mode mode)
+{
+ switch (mode) {
+ case PHY_TYPE_SATA:
+ return "SATA";
+ case PHY_TYPE_PCIE:
+ return "PCIe";
+ case PHY_TYPE_USB3:
+ return "USB3";
+ case PHY_TYPE_SGMII:
+ case PHY_TYPE_QSGMII:
+ return "GMII";
+ default:
+ return "Unknown";
+ }
+}
+
+static int rockchip_combphy_validate(struct phy *phy, enum phy_mode mode, int submode,
+ union phy_configure_opts *opts)
+{
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+
+ if (mode != priv->mode) {
+ dev_err(priv->dev, "expected mode is %s, but current mode is %s\n",
+ rockchip_combphy_mode2str(mode),
+ rockchip_combphy_mode2str(priv->mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct phy_ops rochchip_combphy_ops = {
.init = rockchip_combphy_init,
.exit = rockchip_combphy_exit,
+ .validate = rockchip_combphy_validate,
.owner = THIS_MODULE,
};
@@ -308,6 +350,7 @@
{
const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
int ret, mac_id;
+ u32 vals[4];
ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
if (ret == -EPROBE_DEFER)
@@ -340,6 +383,11 @@
(mac_id > 0))
param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
true);
+
+ if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
+ vals, ARRAY_SIZE(vals)))
+ regmap_write(priv->pipe_grf, vals[0],
+ (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
if (IS_ERR(priv->apb_rst)) {
@@ -468,6 +516,18 @@
val |= 0x01 << 17;
writel(val, priv->mmio + 0x200);
+ /* Set slow slew rate control for PI */
+ val = readl(priv->mmio + 0x204);
+ val &= ~GENMASK(2, 0);
+ val |= 0x07;
+ writel(val, priv->mmio + 0x204);
+
+ /* Set CDR phase path with 2x gain */
+ val = readl(priv->mmio + 0x204);
+ val &= ~GENMASK(5, 5);
+ val |= 0x01 << 5;
+ writel(val, priv->mmio + 0x204);
+
/* Set Rx squelch input filler bandwidth */
val = readl(priv->mmio + 0x20c);
val &= ~GENMASK(2, 0);
@@ -495,39 +555,15 @@
val |= 0x17d;
writel(val, priv->mmio + 0x100);
} else if (priv->mode == PHY_TYPE_PCIE) {
- /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
- val = readl(priv->mmio + 0x100);
- val &= ~GENMASK(10, 0);
- val |= 0x17d;
- writel(val, priv->mmio + 0x100);
-
/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
val = readl(priv->mmio + 0x218);
val |= (1 << 14);
writel(val, priv->mmio + 0x218);
-
- /* PLL KVCO tuning fine */
- val = readl(priv->mmio + 0x18);
- val &= ~(0x7 << 10);
- val |= 0x2 << 10;
- writel(val, priv->mmio + 0x18);
-
- /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
- val = readl(priv->mmio + 0x108);
- val &= ~(0x7f7);
- val |= 0x4f0;
- writel(val, priv->mmio + 0x108);
}
break;
case 100000000:
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
- /* Set ssc_cnt[10:0]=11000110011 & 31.5KHz */
- val = readl(priv->mmio + 0x100);
- val &= ~GENMASK(10, 0);
- val |= 0x633;
- writel(val, priv->mmio + 0x100);
-
/* PLL KVCO tuning fine */
val = readl(priv->mmio + 0x18);
val &= ~(0x7 << 10);
@@ -542,14 +578,6 @@
default:
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
return -EINVAL;
- }
-
- if (priv->mode == PHY_TYPE_PCIE) {
- if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
- val = readl(priv->mmio + 0x100);
- val |= BIT(20);
- writel(val, priv->mmio + 0x100);
- }
}
return 0;
@@ -588,6 +616,201 @@
.clks = rk3528_clks,
.grfcfg = &rk3528_combphy_grfcfgs,
.combphy_cfg = rk3528_combphy_cfg,
+};
+
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ struct clk *refclk = NULL;
+ unsigned long rate;
+ int i;
+ u32 val;
+
+ /* Configure PHY reference clock frequency */
+ for (i = 0; i < priv->num_clks; i++) {
+ if (!strncmp(priv->clks[i].id, "refclk", 6)) {
+ refclk = priv->clks[i].clk;
+ break;
+ }
+ }
+
+ if (!refclk) {
+ dev_err(priv->dev, "No refclk found\n");
+ return -EINVAL;
+ }
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ /* Set PLL KVCO fine tuning signals */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ /* Set PLL input clock divider 1/2 */
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ /* Set PLL loop divider */
+ writel(0x32, priv->mmio + (0x11 << 2));
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ /* Set Rx squelch input filler bandwidth */
+ writel(0x0e, priv->mmio + (0x14 << 2));
+
+ param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ rate = clk_get_rate(refclk);
+
+ switch (rate) {
+ case 24000000:
+ if (priv->mode == PHY_TYPE_USB3) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(7, 6);
+ val |= 0x01 << 6;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ val = readl(priv->mmio + (0x0f << 2));
+ val &= ~GENMASK(7, 0);
+ val |= 0x5f;
+ writel(val, priv->mmio + (0x0f << 2));
+ }
+ break;
+ case 25000000:
+ param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+ break;
+ case 100000000:
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Enable controlling random jitter, aka RMJ */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ writel(0x32, priv->mmio + (0x11 << 2));
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ /* CKDRV output swing adjust to 650mv */
+ val = readl(priv->mmio + (0xd << 2));
+ val &= ~(0xf << 1);
+ val |= (0xb << 1);
+ writel(val, priv->mmio + (0xd << 2));
+ }
+ break;
+ default:
+ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
+ return -EINVAL;
+ }
+
+ if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
+ param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
+ val = readl(priv->mmio + (0xc << 2));
+ val |= 0x3 << 4 | 0x1 << 7;
+ writel(val, priv->mmio + (0xc << 2));
+
+ val = readl(priv->mmio + (0xd << 2));
+ val |= 0x1;
+ writel(val, priv->mmio + (0xd << 2));
+ }
+ }
+
+ if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
+ val = readl(priv->mmio + (0x7 << 2));
+ val |= BIT(4);
+ writel(val, priv->mmio + (0x7 << 2));
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 },
+ /* peri-grf */
+ .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct clk_bulk_data rk3562_clks[] = {
+ { .id = "refclk" },
+ { .id = "apbclk" },
+ { .id = "pipe_clk" },
+};
+
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
+ .num_clks = ARRAY_SIZE(rk3562_clks),
+ .clks = rk3562_clks,
+ .grfcfg = &rk3562_combphy_grfcfgs,
+ .combphy_cfg = rk3562_combphy_cfg,
+ .force_det_out = true,
};
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
@@ -817,15 +1040,294 @@
.force_det_out = true,
};
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ struct clk *refclk = NULL;
+ unsigned long rate;
+ int i;
+ u32 val;
+
+ /* Configure PHY reference clock frequency */
+ for (i = 0; i < priv->num_clks; i++) {
+ if (!strncmp(priv->clks[i].id, "refclk", 6)) {
+ refclk = priv->clks[i].clk;
+ break;
+ }
+ }
+
+ if (!refclk) {
+ dev_err(priv->dev, "No refclk found\n");
+ return -EINVAL;
+ }
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ /* Set PLL KVCO fine tuning signals */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ /* Set PLL input clock divider 1/2 */
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ /* Set PLL loop divider */
+ writel(0x32, priv->mmio + (0x11 << 2));
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ /* Set Rx squelch input filler bandwidth */
+ writel(0x0d, priv->mmio + (0x14 << 2));
+
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
+ writel(0x8F, priv->mmio + (0x06 << 2));
+
+ param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+ param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+ param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+ param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
+ break;
+ case PHY_TYPE_SGMII:
+ case PHY_TYPE_QSGMII:
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ rate = clk_get_rate(refclk);
+
+ switch (rate) {
+ case 24000000:
+ param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+ if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(7, 6);
+ val |= 0x01 << 6;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ val = readl(priv->mmio + (0x0f << 2));
+ val &= ~GENMASK(7, 0);
+ val |= 0x5f;
+ writel(val, priv->mmio + (0x0f << 2));
+ } else if (priv->mode == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~GENMASK(4, 2);
+ val |= 0x4 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set up rx_trim */
+ val = 0x0;
+ writel(val, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T0_1 */
+ val = 0x90;
+ writel(val, priv->mmio + (0xa << 2));
+ val = 0x02;
+ writel(val, priv->mmio + (0xb << 2));
+ val = 0x57;
+ writel(val, priv->mmio + (0xd << 2));
+
+ val = 0x5f;
+ writel(val, priv->mmio + (0xf << 2));
+ }
+ break;
+ case 25000000:
+ param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+ break;
+ case 100000000:
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* gate_tx_pck_sel length select work for L1SS */
+ val = 0xc0;
+ writel(val, priv->mmio + 0x74);
+
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~GENMASK(4, 2);
+ val |= 0x4 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+ val = 0x4c;
+ writel(val, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T3_P1 650mv */
+ val = 0x90;
+ writel(val, priv->mmio + (0xa << 2));
+ val = 0x43;
+ writel(val, priv->mmio + (0xb << 2));
+ val = 0x88;
+ writel(val, priv->mmio + (0xc << 2));
+ val = 0x56;
+ writel(val, priv->mmio + (0xd << 2));
+ } else if (priv->mode == PHY_TYPE_SATA) {
+ /* downward spread spectrum +500ppm */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(7, 4);
+ val |= 0x50;
+ writel(val, priv->mmio + (0x1f << 2));
+
+ /* ssc ppm adjust to 3500ppm */
+ val = readl(priv->mmio + (0x9 << 2));
+ val &= ~GENMASK(3, 0);
+ val |= 0x7;
+ writel(val, priv->mmio + (0x9 << 2));
+ }
+ break;
+ default:
+ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
+ return -EINVAL;
+ }
+
+ if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
+ param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
+ val = 0x10;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ val = 0x0c;
+ writel(val, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T3_P1 650mv */
+ val = 0x90;
+ writel(val, priv->mmio + (0xa << 2));
+ val = 0x43;
+ writel(val, priv->mmio + (0xb << 2));
+ val = 0x88;
+ writel(val, priv->mmio + (0xc << 2));
+ val = 0x56;
+ writel(val, priv->mmio + (0xd << 2));
+ }
+ }
+
+ if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
+ val = readl(priv->mmio + (0x7 << 2));
+ val |= BIT(4);
+ writel(val, priv->mmio + (0x7 << 2));
+
+ if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
+ /* Xin24M T0_1 650mV */
+ writel(0x00, priv->mmio + (0x10 << 2));
+ writel(0x32, priv->mmio + (0x11 << 2));
+ writel(0x00, priv->mmio + (0x1b << 2));
+ writel(0x90, priv->mmio + (0x0a << 2));
+ writel(0x02, priv->mmio + (0x0b << 2));
+ writel(0x08, priv->mmio + (0x0c << 2));
+ writel(0x57, priv->mmio + (0x0d << 2));
+ writel(0x40, priv->mmio + (0x0e << 2));
+ writel(0x5f, priv->mmio + (0x0f << 2));
+ writel(0x10, priv->mmio + (0x20 << 2));
+ }
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
+ /* pipe-grf */
+ .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
+ .pipe_con1_for_sata = { 0x0004, 2, 0, 0x00, 0x2 },
+};
+
+static const struct clk_bulk_data rk3588_clks[] = {
+ { .id = "refclk" },
+ { .id = "apbclk" },
+ { .id = "phpclk" },
+};
+
+static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
+ .num_clks = ARRAY_SIZE(rk3588_clks),
+ .clks = rk3588_clks,
+ .grfcfg = &rk3588_combphy_grfcfgs,
+ .combphy_cfg = rk3588_combphy_cfg,
+ .force_det_out = true,
+};
+
static const struct of_device_id rockchip_combphy_of_match[] = {
{
.compatible = "rockchip,rk3528-naneng-combphy",
.data = &rk3528_combphy_cfgs,
},
{
+ .compatible = "rockchip,rk3562-naneng-combphy",
+ .data = &rk3562_combphy_cfgs,
+ },
+ {
.compatible = "rockchip,rk3568-naneng-combphy",
.data = &rk3568_combphy_cfgs,
},
+ {
+ .compatible = "rockchip,rk3588-naneng-combphy",
+ .data = &rk3588_combphy_cfgs,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
--
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