From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
u-boot/drivers/phy/phy-rockchip-inno-usb2.c | 364 ++++++++++++++++++++++++++++++++++++++++++++++++----
1 files changed, 336 insertions(+), 28 deletions(-)
diff --git a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
index 6ff06f7..92a9181 100644
--- a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
@@ -149,6 +149,7 @@
* primary stage.
* @grf: General Register Files register base.
* @usbgrf_base : USB General Register Files register base.
+ * @phy_base: the base address of USB PHY.
* @phy_rst: phy reset control.
* @phy_cfg: phy register configuration, assigned by driver data.
*/
@@ -157,6 +158,7 @@
u8 primary_retries;
struct regmap *grf_base;
struct regmap *usbgrf_base;
+ void __iomem *phy_base;
struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
struct reset_ctl phy_rst;
const struct rockchip_usb2phy_cfg *phy_cfg;
@@ -282,6 +284,11 @@
return POWER_SUPPLY_TYPE_UNKNOWN;
}
+#ifdef CONFIG_ROCKCHIP_RK3036
+ chg_type = POWER_SUPPLY_TYPE_USB;
+ goto out;
+#endif
+
/* Suspend USB-PHY and put the controller in non-driving mode */
property_enable(base, &port_cfg->phy_sus, true);
property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
@@ -388,36 +395,14 @@
port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
/* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
- property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
+ if(rphy->phy_cfg->clkout_ctl.disable)
+ property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
/* Reset USB-PHY */
property_enable(base, &port_cfg->phy_sus, true);
udelay(20);
property_enable(base, &port_cfg->phy_sus, false);
mdelay(2);
-}
-
-static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
-{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_usb2phy *rphy = dev_get_priv(parent);
- const struct rockchip_usb2phy_port_cfg *port_cfg;
- struct regmap *base = get_reg_base(rphy);
- struct udevice *vbus = NULL;
- bool iddig = true;
-
- if (phy->id == USB2PHY_PORT_HOST) {
- vbus = rphy->vbus_supply[USB2PHY_PORT_HOST];
- } else if (phy->id == USB2PHY_PORT_OTG) {
- port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
- if (port_cfg->utmi_iddig.offset) {
- iddig = property_enabled(base, &port_cfg->utmi_iddig);
- if (!iddig)
- vbus = rphy->vbus_supply[USB2PHY_PORT_OTG];
- }
- }
-
- return vbus;
}
static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
@@ -492,10 +477,11 @@
static int rockchip_usb2phy_power_on(struct phy *phy)
{
- struct udevice *vbus = NULL;
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
int ret;
- vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, true);
if (ret) {
@@ -509,10 +495,11 @@
static int rockchip_usb2phy_power_off(struct phy *phy)
{
- struct udevice *vbus = NULL;
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
int ret;
- vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, false);
if (ret) {
@@ -587,6 +574,11 @@
struct resource res;
u32 reg, index;
int ret;
+
+ rphy->phy_base = (void __iomem *)dev_read_addr(dev);
+ if (IS_ERR(rphy->phy_base)) {
+ dev_err(dev, "get the base address of usb phy failed\n");
+ }
if (!strncmp(parent->name, "root_driver", 11) &&
dev_read_bool(dev, "rockchip,grf")) {
@@ -818,6 +810,102 @@
return 0;
}
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+
+ /* Set HS disconnect detect mode to single ended detect mode */
+ reg = readl(rphy->phy_base + 0x70);
+ writel(reg | BIT(2), rphy->phy_base + 0x70);
+
+ return 0;
+}
+
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+ int ret = 0;
+
+ if (IS_ERR(rphy->phy_base)) {
+ return PTR_ERR(rphy->phy_base);
+ }
+
+ /* Turn off otg port differential receiver in suspend mode */
+ reg = readl(rphy->phy_base + 0x30);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
+
+ /* Turn off host port differential receiver in suspend mode */
+ reg = readl(rphy->phy_base + 0x0430);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
+
+ /* Set otg port HS eye height to 400mv(default is 450mv) */
+ reg = readl(rphy->phy_base + 0x30);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x00 << 4);
+ writel(reg, rphy->phy_base + 0x30);
+
+ /* Set host port HS eye height to 400mv(default is 450mv) */
+ reg = readl(rphy->phy_base + 0x430);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x00 << 4);
+ writel(reg, rphy->phy_base + 0x430);
+
+ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
+ reg = readl(rphy->phy_base + 0x94);
+ reg &= ~GENMASK(6, 3);
+ reg |= (0x03 << 3);
+ writel(reg, rphy->phy_base + 0x94);
+
+ /* Turn on output clk of phy*/
+ reg = readl(rphy->phy_base + 0x41c);
+ reg &= ~GENMASK(7, 2);
+ reg |= (0x27 << 2);
+ writel(reg, rphy->phy_base + 0x41c);
+
+ return ret;
+}
+
+static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+ int ret = 0;
+
+ if (IS_ERR(rphy->phy_base)) {
+ return PTR_ERR(rphy->phy_base);
+ }
+
+ /* Turn off differential receiver by default to save power */
+ reg = readl(rphy->phy_base + 0x30);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
+
+ reg = readl(rphy->phy_base + 0x0430);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
+
+ /* Enable pre-emphasis during non-chirp phase */
+ reg = readl(rphy->phy_base);
+ reg &= ~GENMASK(2, 0);
+ reg |= 0x04;
+ writel(reg, rphy->phy_base);
+
+ reg = readl(rphy->phy_base + 0x0400);
+ reg &= ~GENMASK(2, 0);
+ reg |= 0x04;
+ writel(reg, rphy->phy_base + 0x0400);
+
+ /* Set HS eye height to 425mv(default is 400mv) */
+ reg = readl(rphy->phy_base + 0x0030);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x05 << 4);
+ writel(reg, rphy->phy_base + 0x0030);
+
+ reg = readl(rphy->phy_base + 0x0430);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x05 << 4);
+ writel(reg, rphy->phy_base + 0x0430);
+
+ return ret;
+}
+
static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
struct regmap *base = get_reg_base(rphy);
@@ -902,6 +990,43 @@
.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
+ {
+ .reg = 0x17c,
+ .num_ports = 2,
+ .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
+ .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
+ .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
+ .iddig_output = { 0x017c, 10, 10, 0, 1 },
+ .iddig_en = { 0x017c, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
+ .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
+ .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
+ .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
+ .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
+ .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
+ .ls_det_en = { 0x017c, 12, 12, 0, 1 },
+ .ls_det_st = { 0x017c, 13, 13, 0, 1 },
+ .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
+ .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
+ .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
+ .utmi_ls = { 0x014c, 7, 6, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x0194, 14, 14, 0, 1 },
+ .ls_det_st = { 0x0194, 15, 15, 0, 1 },
+ .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
+ }
},
},
{ /* sentinel */ }
@@ -1272,6 +1397,51 @@
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
+ {
+ .reg = 0xff3e0000,
+ .num_ports = 1,
+ .phy_tuning = rv1106_usb2phy_tuning,
+ .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
+ .iddig_output = { 0x0050, 10, 10, 0, 1 },
+ .iddig_en = { 0x0050, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
+ .ls_det_en = { 0x0100, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0104, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
+ .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0060, 5, 4, 0, 1 },
+ },
+ },
+ .chg_det = {
+ .opmode = { 0x0050, 3, 0, 5, 1 },
+ .cp_det = { 0x0060, 13, 13, 0, 1 },
+ .dcp_det = { 0x0060, 12, 12, 0, 1 },
+ .dp_det = { 0x0060, 14, 14, 0, 1 },
+ .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
+ .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
+ .idp_src_en = { 0x0058, 9, 9, 0, 1 },
+ .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
+ .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
+ .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
{
.reg = 0x100,
@@ -1309,6 +1479,110 @@
.rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .num_ports = 2,
+ .phy_tuning = rk3528_usb2phy_tuning,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
+ .iddig_output = { 0x6004c, 10, 10, 0, 1 },
+ .iddig_en = { 0x6004c, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
+ .ls_det_en = { 0x60074, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60078, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
+ .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x60090, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60094, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x6004c, 3, 0, 5, 1 },
+ .cp_det = { 0x6006c, 19, 19, 0, 1 },
+ .dcp_det = { 0x6006c, 18, 18, 0, 1 },
+ .dp_det = { 0x6006c, 20, 20, 0, 1 },
+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
+ .idp_src_en = { 0x60058, 2, 2, 0, 1 },
+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
+ },
+ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
+ {
+ .reg = 0xff740000,
+ .num_ports = 2,
+ .phy_tuning = rk3562_usb2phy_tuning,
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
+ .iddig_output = { 0x0100, 10, 10, 0, 1 },
+ .iddig_en = { 0x0100, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
+ .ls_det_en = { 0x0110, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0114, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
+ .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0120, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x0110, 1, 1, 0, 1 },
+ .ls_det_st = { 0x0114, 1, 1, 0, 1 },
+ .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
+ .utmi_ls = { 0x0120, 17, 16, 0, 1 },
+ .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x0100, 3, 0, 5, 1 },
+ .cp_det = { 0x0120, 24, 24, 0, 1 },
+ .dcp_det = { 0x0120, 23, 23, 0, 1 },
+ .dp_det = { 0x0120, 25, 25, 0, 1 },
+ .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
+ .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
+ .idp_src_en = { 0x0108, 9, 9, 0, 1 },
+ .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
+ .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
+ .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
},
},
{ /* sentinel */ }
@@ -1401,6 +1675,8 @@
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
.utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
@@ -1468,16 +1744,48 @@
};
static const struct udevice_id rockchip_usb2phy_ids[] = {
+#ifdef CONFIG_ROCKCHIP_RK1808
{ .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3036
+ { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
+#endif
+#if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
{ .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK322X
{ .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3308
{ .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
+#endif
+#if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30
{ .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3368
{ .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3399
{ .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3528
+ { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3562
+ { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3568
{ .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3588
{ .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RV1106
+ { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RV1108
{ .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
+#endif
{ }
};
--
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