From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/video/rockchip/rga3/rga_common.c | 129 +++++++++++++++++++++++++++++++++++++++----
1 files changed, 117 insertions(+), 12 deletions(-)
diff --git a/kernel/drivers/video/rockchip/rga3/rga_common.c b/kernel/drivers/video/rockchip/rga3/rga_common.c
index 0e21326..80d4821 100644
--- a/kernel/drivers/video/rockchip/rga3/rga_common.c
+++ b/kernel/drivers/video/rockchip/rga3/rga_common.c
@@ -107,6 +107,30 @@
}
}
+bool rga_is_yuv420_planar_format(uint32_t format)
+{
+ switch (format) {
+ case RGA_FORMAT_YCbCr_420_P:
+ case RGA_FORMAT_YCrCb_420_P:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool rga_is_yuv420_semi_planar_format(uint32_t format)
+{
+ switch (format) {
+ case RGA_FORMAT_YCbCr_420_SP:
+ case RGA_FORMAT_YCrCb_420_SP:
+ case RGA_FORMAT_YCbCr_420_SP_10B:
+ case RGA_FORMAT_YCrCb_420_SP_10B:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool rga_is_yuv422_packed_format(uint32_t format)
{
switch (format) {
@@ -114,6 +138,30 @@
case RGA_FORMAT_VYUY_422:
case RGA_FORMAT_YUYV_422:
case RGA_FORMAT_UYVY_422:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool rga_is_yuv422_planar_format(uint32_t format)
+{
+ switch (format) {
+ case RGA_FORMAT_YCbCr_422_P:
+ case RGA_FORMAT_YCrCb_422_P:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool rga_is_yuv422_semi_planar_format(uint32_t format)
+{
+ switch (format) {
+ case RGA_FORMAT_YCbCr_422_SP:
+ case RGA_FORMAT_YCrCb_422_SP:
+ case RGA_FORMAT_YCbCr_422_SP_10B:
+ case RGA_FORMAT_YCrCb_422_SP_10B:
return true;
default:
return false;
@@ -481,20 +529,49 @@
}
}
-const char *rga_get_blend_mode_str(uint16_t alpha_rop_flag,
- uint16_t alpha_mode_0,
- uint16_t alpha_mode_1)
+const char *rga_get_blend_mode_str(enum rga_alpha_blend_mode mode)
{
- if (alpha_rop_flag == 0) {
+ switch (mode) {
+ case RGA_ALPHA_NONE:
return "no blend";
- } else if (alpha_rop_flag == 0x9) {
- if (alpha_mode_0 == 0x381A && alpha_mode_1 == 0x381A)
- return "105 src + (1-src.a)*dst";
- else if (alpha_mode_0 == 0x483A && alpha_mode_1 == 0x483A)
- return "405 src.a * src + (1-src.a) * dst";
- else
- return "check reg for more imformation";
- } else {
+
+ case RGA_ALPHA_BLEND_SRC:
+ return "src";
+
+ case RGA_ALPHA_BLEND_DST:
+ return "dst";
+
+ case RGA_ALPHA_BLEND_SRC_OVER:
+ return "src-over";
+
+ case RGA_ALPHA_BLEND_DST_OVER:
+ return "dst-over";
+
+ case RGA_ALPHA_BLEND_SRC_IN:
+ return "src-in";
+
+ case RGA_ALPHA_BLEND_DST_IN:
+ return "dst-in";
+
+ case RGA_ALPHA_BLEND_SRC_OUT:
+ return "src-out";
+
+ case RGA_ALPHA_BLEND_DST_OUT:
+ return "dst-out";
+
+ case RGA_ALPHA_BLEND_SRC_ATOP:
+ return "src-atop";
+
+ case RGA_ALPHA_BLEND_DST_ATOP:
+ return "dst-atop";
+
+ case RGA_ALPHA_BLEND_XOR:
+ return "xor";
+
+ case RGA_ALPHA_BLEND_CLEAR:
+ return "clear";
+
+ default:
return "check reg for more imformation";
}
}
@@ -524,6 +601,20 @@
return "RK_IOMMU";
default:
return "NONE_MMU";
+ }
+}
+
+const char *rga_get_core_name(enum RGA_SCHEDULER_CORE core)
+{
+ switch (core) {
+ case RGA_SCHEDULER_RGA3_CORE0:
+ return "RGA3_core0";
+ case RGA_SCHEDULER_RGA3_CORE1:
+ return "RGA3_core1";
+ case RGA_SCHEDULER_RGA2_CORE0:
+ return "RGA2_core0";
+ default:
+ return "unknown_core";
}
}
@@ -665,3 +756,17 @@
return (yrgb + uv + v);
}
+
+void rga_dump_memory_parm(struct rga_memory_parm *parm)
+{
+ pr_info("memory param: w = %d, h = %d, f = %s(0x%x), size = %d\n",
+ parm->width, parm->height, rga_get_format_name(parm->format),
+ parm->format, parm->size);
+}
+
+void rga_dump_external_buffer(struct rga_external_buffer *buffer)
+{
+ pr_info("external: memory = 0x%lx, type = %s\n",
+ (unsigned long)buffer->memory, rga_get_memory_type_str(buffer->type));
+ rga_dump_memory_parm(&buffer->memory_parm);
+}
--
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