From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/video/rockchip/rga3/rga3_reg_info.c | 506 +++++++++++++++++++++++++++++++++----------------------
1 files changed, 304 insertions(+), 202 deletions(-)
diff --git a/kernel/drivers/video/rockchip/rga3/rga3_reg_info.c b/kernel/drivers/video/rockchip/rga3/rga3_reg_info.c
index f6e4345..2b61833 100644
--- a/kernel/drivers/video/rockchip/rga3/rga3_reg_info.c
+++ b/kernel/drivers/video/rockchip/rga3/rga3_reg_info.c
@@ -390,9 +390,9 @@
*/
/* do not use win0 src size except fbcd */
- *bRGA3_WIN0_SRC_SIZE = (msg->win0.src_act_w +
- msg->win0.x_offset) | ((msg->win0.y_offset +
- msg->win0.src_act_h) << 16);
+ /* in FBCD, src_width needs to be aligned at 16 */
+ *bRGA3_WIN0_SRC_SIZE = ALIGN(msg->win0.src_act_w + msg->win0.x_offset, 16) |
+ (ALIGN(msg->win0.y_offset + msg->win0.src_act_h, 16) << 16);
*bRGA3_WIN0_ACT_SIZE =
msg->win0.src_act_w | (msg->win0.src_act_h << 16);
*bRGA3_WIN0_DST_SIZE =
@@ -1028,6 +1028,9 @@
u32 *bRGA3_OVLP_OFF;
u32 reg;
+ union rga3_color_ctrl top_color_ctrl, bottom_color_ctrl;
+ union rga3_alpha_ctrl top_alpha_ctrl, bottom_alpha_ctrl;
+ struct rga_alpha_config *config;
bRGA_OVERLAP_TOP_CTRL = (u32 *) (base + RGA3_OVLP_TOP_CTRL_OFFSET);
bRGA_OVERLAP_BOT_CTRL = (u32 *) (base + RGA3_OVLP_BOT_CTRL_OFFSET);
@@ -1039,98 +1042,249 @@
/* Alpha blend */
/*bot -> win0(dst), top -> win1(src). */
- reg = 0;
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0
- (msg->alpha_mode_0 >> 7)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0
- (msg->alpha_mode_0 >> 0)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0
- (msg->alpha_mode_0 >> 1)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0
- (msg->alpha_mode_0 >> 3)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0
- (msg->alpha_mode_0 >> 4)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA)) |
- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA
- (msg->win1_a_global_val)));
- *bRGA_OVERLAP_TOP_CTRL = reg;
+ top_color_ctrl.value = 0;
+ bottom_color_ctrl.value = 0;
+ top_alpha_ctrl.value = 0;
+ bottom_alpha_ctrl.value = 0;
+ config = &msg->alpha_config;
- reg = 0;
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0
- (msg->alpha_mode_0 >> 15)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0
- (msg->alpha_mode_0 >> 8)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0
- (msg->alpha_mode_0 >> 9)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0
- (msg->alpha_mode_0 >> 11)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0
- (msg->alpha_mode_0 >> 12)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA)) |
- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA
- (msg->win0_a_global_val)));
- *bRGA_OVERLAP_BOT_CTRL = reg;
+ if (config->fg_pixel_alpha_en)
+ top_color_ctrl.bits.blend_mode =
+ config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
+ RGA_ALPHA_PER_PIXEL;
+ else
+ top_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
- reg = 0;
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1)) |
- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1
- (msg->alpha_mode_1 >> 0)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1)) |
- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1
- (msg->alpha_mode_1 >> 1)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1)) |
- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1
- (msg->alpha_mode_1 >> 3)));
- reg =
- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1)) |
- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1
- (msg->alpha_mode_1 >> 4)));
- *bRGA_OVERLAP_TOP_ALPHA = reg;
+ if (config->bg_pixel_alpha_en)
+ bottom_color_ctrl.bits.blend_mode =
+ config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
+ RGA_ALPHA_PER_PIXEL;
+ else
+ bottom_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
- reg = 0;
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1)) |
- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1
- (msg->alpha_mode_1 >> 8)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1)) |
- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1
- (msg->alpha_mode_1 >> 9)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1)) |
- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1
- (msg->alpha_mode_1 >> 11)));
- reg =
- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1)) |
- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1
- (msg->alpha_mode_1 >> 12)));
+ /*
+ * Since the hardware uses 256 as 1, the original alpha value needs to
+ * be + (alpha >> 7).
+ */
+ top_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
+ bottom_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
- *bRGA_OVERLAP_BOT_ALPHA = reg;
+ top_color_ctrl.bits.global_alpha = config->fg_global_alpha_value;
+ bottom_color_ctrl.bits.global_alpha = config->bg_global_alpha_value;
+
+ /* porter duff alpha enable */
+ switch (config->mode) {
+ case RGA_ALPHA_BLEND_SRC:
+ /*
+ * SRC mode:
+ * Sf = 1, Df = 0；
+ * [Rc,Ra] = [Sc,Sa]；
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ break;
+
+ case RGA_ALPHA_BLEND_DST:
+ /*
+ * SRC mode:
+ * Sf = 0, Df = 1；
+ * [Rc,Ra] = [Dc,Da]；
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_SRC_OVER:
+ /*
+ * SRC-OVER mode:
+ * Sf = 1, Df = (1 - Sa)
+ * [Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_DST_OVER:
+ /*
+ * DST-OVER mode:
+ * Sf = (1 - Da) , Df = 1
+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_SRC_IN:
+ /*
+ * SRC-IN mode:
+ * Sf = Da , Df = 0
+ * [Rc,Ra] = [ Sc * Da, Sa * Da ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ break;
+
+ case RGA_ALPHA_BLEND_DST_IN:
+ /*
+ * DST-IN mode:
+ * Sf = 0 , Df = Sa
+ * [Rc,Ra] = [ Dc * Sa, Da * Sa ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_SRC_OUT:
+ /*
+ * SRC-OUT mode:
+ * Sf = (1 - Da) , Df = 0
+ * [Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ break;
+
+ case RGA_ALPHA_BLEND_DST_OUT:
+ /*
+ * DST-OUT mode:
+ * Sf = 0 , Df = (1 - Sa)
+ * [Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_SRC_ATOP:
+ /*
+ * SRC-ATOP mode:
+ * Sf = Da , Df = (1 - Sa)
+ * [Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_DST_ATOP:
+ /*
+ * DST-ATOP mode:
+ * Sf = (1 - Da) , Df = Sa
+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_XOR:
+ /*
+ * DST-XOR mode:
+ * Sf = (1 - Da) , Df = (1 - Sa)
+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
+
+ break;
+
+ case RGA_ALPHA_BLEND_CLEAR:
+ /*
+ * DST-CLEAR mode:
+ * Sf = 0 , Df = 0
+ * [Rc,Ra] = [ 0, 0 ]
+ */
+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
+
+ break;
+
+ default:
+ break;
+ }
+
+ if (!config->enable && msg->abb_alpha_pass) {
+ /*
+ * enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0)
+ * In ABB mode, the number will be fetched according to 16*16, so it needs to
+ * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
+ */
+ top_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
+
+ top_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
+ top_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
+
+ bottom_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
+
+ bottom_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
+ bottom_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
+ } else {
+ top_color_ctrl.bits.color_mode =
+ config->fg_pre_multiplied ?
+ RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
+
+ top_alpha_ctrl.bits.blend_mode = top_color_ctrl.bits.blend_mode;
+ top_alpha_ctrl.bits.alpha_cal_mode = top_color_ctrl.bits.alpha_cal_mode;
+ top_alpha_ctrl.bits.alpha_mode = top_color_ctrl.bits.alpha_mode;
+ top_alpha_ctrl.bits.factor_mode = top_color_ctrl.bits.factor_mode;
+
+ bottom_color_ctrl.bits.color_mode =
+ config->bg_pre_multiplied ?
+ RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
+
+ bottom_alpha_ctrl.bits.blend_mode = bottom_color_ctrl.bits.blend_mode;
+ bottom_alpha_ctrl.bits.alpha_cal_mode = bottom_color_ctrl.bits.alpha_cal_mode;
+ bottom_alpha_ctrl.bits.alpha_mode = bottom_color_ctrl.bits.alpha_mode;
+ bottom_alpha_ctrl.bits.factor_mode = bottom_color_ctrl.bits.factor_mode;
+ }
+
+ *bRGA_OVERLAP_TOP_CTRL = top_color_ctrl.value;
+ *bRGA_OVERLAP_BOT_CTRL = bottom_color_ctrl.value;
+ *bRGA_OVERLAP_TOP_ALPHA = top_alpha_ctrl.value;
+ *bRGA_OVERLAP_BOT_ALPHA = bottom_alpha_ctrl.value;
/* set RGA_OVERLAP_CTRL */
reg = 0;
@@ -1166,9 +1320,8 @@
* warning: if m1 & m0 need config split，need to redesign
* this judge, which consider RGBA8888 format
*/
- if (msg->alpha_mode_1 > 0 && msg->alpha_mode_0 > 0)
- reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) |
- (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(1)));
+ reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) |
+ (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(config->enable)));
*bRGA_OVERLAP_CTRL = reg;
@@ -1261,7 +1414,6 @@
/* TODO: common part */
static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
{
- u16 alpha_mode_0, alpha_mode_1;
struct rga_img_info_t tmp;
req->render_mode = BITBLT_MODE;
@@ -1324,8 +1476,8 @@
if (!(req_rga->alpha_rop_flag & 1)) {
if (!rga_is_alpha_format(req_rga->src.format) &&
rga_is_alpha_format(req_rga->dst.format)) {
- req->win0_a_global_val = 0xff;
- req->win1_a_global_val = 0xff;
+ req->alpha_config.fg_global_alpha_value = 0xff;
+ req->alpha_config.bg_global_alpha_value = 0xff;
}
}
@@ -1345,7 +1497,7 @@
* be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
*/
if (rga_is_alpha_format(req_rga->src.format))
- req->alpha_mode_1 = 0x0a0a;
+ req->abb_alpha_pass = true;
set_win_info(&req->win0, &req_rga->src);
@@ -1375,7 +1527,7 @@
* be enabled bot_blend_m1 && bot_alpha_cal_m1 for src1/dst channel(win0).
*/
if (rga_is_alpha_format(req_rga->src.format))
- req->alpha_mode_1 = 0x0a0a;
+ req->abb_alpha_pass = true;
if (req_rga->pat.yrgb_addr != 0) {
if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) {
@@ -1478,103 +1630,43 @@
/* Alpha blend mode */
if (((req_rga->alpha_rop_flag) & 1)) {
if ((req_rga->alpha_rop_flag >> 3) & 1) {
- /* porter duff alpha enable */
- switch (req_rga->PD_mode) {
- /* dst = 0 */
- case 0:
- break;
- /* dst = src */
- case 1:
- req->alpha_mode_0 = 0x0212;
- req->alpha_mode_1 = 0x0212;
- break;
- /* dst = dst */
- case 2:
- req->alpha_mode_0 = 0x1202;
- req->alpha_mode_1 = 0x1202;
- break;
- /* dst = (256*sc + (256 - sa)*dc) >> 8 */
- case 3:
- if ((req_rga->alpha_rop_mode & 3) == 0) {
- /* both use globalAlpha. */
- alpha_mode_0 = 0x3010;
- alpha_mode_1 = 0x3010;
- } else if ((req_rga->alpha_rop_mode & 3) == 1) {
- /* Do not use globalAlpha. */
- alpha_mode_0 = 0x3212;
- alpha_mode_1 = 0x3212;
- } else if ((req_rga->alpha_rop_mode & 3) == 2) {
- /*
- * dst use globalAlpha,
- * and dst has pixelAlpha.
- */
- alpha_mode_0 = 0x3014;
- alpha_mode_1 = 0x3014;
- } else {
- /*
- * dst use globalAlpha,
- * and dst does not have pixelAlpha.
- */
- alpha_mode_0 = 0x3012;
- alpha_mode_1 = 0x3012;
- }
- req->alpha_mode_0 = alpha_mode_0;
- req->alpha_mode_1 = alpha_mode_1;
- break;
- /* dst = (sc*(256-da) + 256*dc) >> 8 */
- case 4:
- /* Do not use globalAlpha. */
- req->alpha_mode_0 = 0x1232;
- req->alpha_mode_1 = 0x1232;
- break;
- /* dst = (da*sc) >> 8 */
- case 5:
- break;
- /* dst = (sa*dc) >> 8 */
- case 6:
- break;
- /* dst = ((256-da)*sc) >> 8 */
- case 7:
- break;
- /* dst = ((256-sa)*dc) >> 8 */
- case 8:
- break;
- /* dst = (da*sc + (256-sa)*dc) >> 8 */
- case 9:
- req->alpha_mode_0 = 0x3040;
- req->alpha_mode_1 = 0x3040;
- break;
- /* dst = ((256-da)*sc + (sa*dc)) >> 8 */
- case 10:
- break;
- /* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */
- case 11:
- break;
- case 12:
- req->alpha_mode_0 = 0x0010;
- req->alpha_mode_1 = 0x0820;
- break;
- default:
- break;
- }
- /* Real color mode */
+ req->alpha_config.enable = true;
+
if ((req_rga->alpha_rop_flag >> 9) & 1) {
- if (req->alpha_mode_0 & (0x01 << 1))
- req->alpha_mode_0 |= (1 << 7);
- if (req->alpha_mode_0 & (0x01 << 9))
- req->alpha_mode_0 |= (1 << 15);
+ req->alpha_config.fg_pre_multiplied = false;
+ req->alpha_config.bg_pre_multiplied = false;
+ } else {
+ req->alpha_config.fg_pre_multiplied = true;
+ req->alpha_config.bg_pre_multiplied = true;
}
- } else {
- if ((req_rga->alpha_rop_mode & 3) == 0) {
- req->alpha_mode_0 = 0x3040;
- req->alpha_mode_1 = 0x3040;
- } else if ((req_rga->alpha_rop_mode & 3) == 1) {
- req->alpha_mode_0 = 0x3042;
- req->alpha_mode_1 = 0x3242;
- } else if ((req_rga->alpha_rop_mode & 3) == 2) {
- req->alpha_mode_0 = 0x3044;
- req->alpha_mode_1 = 0x3044;
+
+ req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->win1.format);
+ req->alpha_config.bg_pixel_alpha_en = rga_is_alpha_format(req->win0.format);
+
+ if (req_rga->feature.global_alpha_en) {
+ if (req_rga->fg_global_alpha < 0xff) {
+ req->alpha_config.fg_global_alpha_en = true;
+ req->alpha_config.fg_global_alpha_value =
+ req_rga->fg_global_alpha;
+ } else if (!req->alpha_config.fg_pixel_alpha_en) {
+ req->alpha_config.fg_global_alpha_en = true;
+ req->alpha_config.fg_global_alpha_value = 0xff;
+ }
+
+ if (req_rga->bg_global_alpha < 0xff) {
+ req->alpha_config.bg_global_alpha_en = true;
+ req->alpha_config.bg_global_alpha_value =
+ req_rga->bg_global_alpha;
+ } else if (!req->alpha_config.bg_pixel_alpha_en) {
+ req->alpha_config.bg_global_alpha_en = true;
+ req->alpha_config.bg_global_alpha_value = 0xff;
+ }
+ } else {
+ req->alpha_config.bg_global_alpha_value = 0xff;
+ req->alpha_config.bg_global_alpha_value = 0xff;
}
+
+ req->alpha_config.mode = req_rga->PD_mode;
}
}
@@ -1651,10 +1743,11 @@
}
if (i == RGA_RESET_TIMEOUT)
- pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
- rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler));
+ pr_err("RGA3 core[%d] soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
+ scheduler->core, rga_read(RGA3_SYS_CTRL, scheduler),
+ rga_read(RGA3_RO_SRST, scheduler));
else
- pr_info("RGA3 soft reset complete.\n");
+ pr_info("RGA3 core[%d] soft reset complete.\n", scheduler->core);
}
static int rga3_scale_check(const struct rga3_req *req)
@@ -1821,11 +1914,14 @@
pr_info("mmu: win0 = %.2x win1 = %.2x wr = %.2x\n",
req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
req->mmu_info.dst_mmu_flag);
- pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
- req->alpha_mode_0, req->alpha_mode_1);
- pr_info("blend mode is %s\n",
- rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
- req->alpha_mode_1));
+ pr_info("alpha: flag %x mode=%s\n",
+ req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
+ pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
+ req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
+ req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
+ req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
+ pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
+ req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
}
@@ -1859,6 +1955,7 @@
struct rga3_req req;
int ret = 0;
struct rga_scheduler_t *scheduler = NULL;
+ ktime_t timestamp = ktime_get();
scheduler = job->scheduler;
if (unlikely(scheduler == NULL)) {
@@ -1887,6 +1984,10 @@
pr_err("RKA: gen reg info error\n");
return -EINVAL;
}
+
+ if (DEBUGGER_EN(TIME))
+ pr_info("request[%d], generate register cost time %lld us\n",
+ job->request_id, ktime_us_delta(ktime_get(), timestamp));
return ret;
}
@@ -1974,7 +2075,8 @@
}
if (DEBUGGER_EN(TIME))
- pr_info("set cmd use time = %lld\n", ktime_us_delta(now, job->timestamp));
+ pr_info("request[%d], set register cost time %lld us\n",
+ job->request_id, ktime_us_delta(now, job->timestamp));
job->hw_running_time = now;
job->hw_recoder_time = now;
--
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