From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/pinctrl/pinctrl-sx150x.c | 83 ++++++++++++++++++++---------------------
1 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/kernel/drivers/pinctrl/pinctrl-sx150x.c b/kernel/drivers/pinctrl/pinctrl-sx150x.c
index 4d87d75..484a3b9 100644
--- a/kernel/drivers/pinctrl/pinctrl-sx150x.c
+++ b/kernel/drivers/pinctrl/pinctrl-sx150x.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, BayLibre, SAS. All rights reserved.
* Author: Neil Armstrong <narmstrong@baylibre.com>
@@ -8,15 +9,6 @@
* The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
*
* Author: Gregory Bean <gbean@codeaurora.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/regmap.h>
@@ -399,13 +391,16 @@
int ret;
if (sx150x_pin_is_oscio(pctl, offset))
- return false;
+ return GPIO_LINE_DIRECTION_OUT;
ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
if (ret < 0)
return ret;
- return !!(value & BIT(offset));
+ if (value & BIT(offset))
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
}
static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
@@ -448,7 +443,6 @@
sx150x_gpio_oscio_set(pctl, value);
else
__sx150x_gpio_set(pctl, offset, value);
-
}
static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
@@ -695,7 +689,7 @@
if (ret < 0)
return ret;
- if (ret)
+ if (ret == GPIO_LINE_DIRECTION_IN)
return -EINVAL;
ret = sx150x_gpio_get(&pctl->gpio, pin);
@@ -993,7 +987,7 @@
/*
* In order to mask the differences between 16 and 8 bit expander
* devices we set up a sligthly ficticious regmap that pretends to be
- * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
+ * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
* pair/quartet) registers and transparently reconstructs those
* registers via multiple I2C/SMBus reads
*
@@ -1159,12 +1153,6 @@
return ret;
}
- ret = pinctrl_enable(pctl->pctldev);
- if (ret) {
- dev_err(dev, "Failed to enable pinctrl device\n");
- return ret;
- }
-
/* Register GPIO controller */
pctl->gpio.base = -1;
pctl->gpio.ngpio = pctl->data->npins;
@@ -1192,17 +1180,10 @@
if (pctl->data->model != SX150X_789)
pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
- ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
- if (ret)
- return ret;
-
- ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
- 0, 0, pctl->data->npins);
- if (ret)
- return ret;
-
/* Add Interrupt support if an irq is specified */
if (client->irq > 0) {
+ struct gpio_irq_chip *girq;
+
pctl->irq_chip.irq_mask = sx150x_irq_mask;
pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
@@ -1218,8 +1199,8 @@
/*
* Because sx150x_irq_threaded_fn invokes all of the
- * nested interrrupt handlers via handle_nested_irq,
- * any "handler" passed to gpiochip_irqchip_add()
+ * nested interrupt handlers via handle_nested_irq,
+ * any "handler" assigned to struct gpio_irq_chip
* below is going to be ignored, so the choice of the
* function does not matter that much.
*
@@ -1227,13 +1208,15 @@
* plus it will be instantly noticeable if it is ever
* called (should not happen)
*/
- ret = gpiochip_irqchip_add_nested(&pctl->gpio,
- &pctl->irq_chip, 0,
- handle_bad_irq, IRQ_TYPE_NONE);
- if (ret) {
- dev_err(dev, "could not connect irqchip to gpiochip\n");
- return ret;
- }
+ girq = &pctl->gpio.irq;
+ girq->chip = &pctl->irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ girq->threaded = true;
ret = devm_request_threaded_irq(dev, client->irq, NULL,
sx150x_irq_thread_fn,
@@ -1242,12 +1225,28 @@
pctl->irq_chip.name, pctl);
if (ret < 0)
return ret;
-
- gpiochip_set_nested_irqchip(&pctl->gpio,
- &pctl->irq_chip,
- client->irq);
}
+ ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
+ if (ret)
+ return ret;
+
+ /*
+ * Pin control functions need to be enabled AFTER registering the
+ * GPIO chip because sx150x_pinconf_set() calls
+ * sx150x_gpio_direction_output().
+ */
+ ret = pinctrl_enable(pctl->pctldev);
+ if (ret) {
+ dev_err(dev, "Failed to enable pinctrl device\n");
+ return ret;
+ }
+
+ ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
+ 0, 0, pctl->data->npins);
+ if (ret)
+ return ret;
+
return 0;
}
--
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