From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver

---
 kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h |   37 +++++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h b/kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h
index 1e13bc0..31331f4 100644
--- a/kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h
+++ b/kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h
@@ -18,6 +18,9 @@
 
 /* Test Code: 0x44 (HS RX Control of Lane 0) */
 #define HSFREQRANGE(x)			UPDATE(x, 6, 1)
+#define HSTX(x)				UPDATE(x, 6, 0)
+#define HSZERO(x)			UPDATE(x, 5, 0)
+#define HSPOST(x)			UPDATE(x, 4, 0)
 
 static inline void testif_testclk_assert(struct rk628 *rk628)
 {
@@ -189,6 +192,40 @@
 	testif_write(rk628, 0x44, HSFREQRANGE(hsfreqrange));
 }
 
+static void __maybe_unused mipi_dphy_init_hsmanual(struct rk628 *rk628, bool manual)
+{
+	if (manual) {
+		//config mipi timing when mipi freq is 1250Mbps
+		testif_write(rk628, 0x71, HSTX(0x4a) | BIT(7));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x72, HSZERO(0xf) | BIT(6));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x73, HSTX(0x5d) | BIT(7));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x61, HSTX(0x3a) | BIT(7));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x62, HSZERO(0x3a) | BIT(6));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x63, HSTX(0x5a) | BIT(7));
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x65, HSPOST(0x1f) | BIT(5));
+	} else {
+		testif_write(rk628, 0x71, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x72, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x73, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x61, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x62, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x63, 0);
+		usleep_range(1500, 2000);
+		testif_write(rk628, 0x65, 0);
+	}
+}
+
 static inline int mipi_dphy_reset(struct rk628 *rk628)
 {
 	u32 val, mask;

--
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