From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/media/i2c/gc2093.c | 769 ++++++++++++++++++++++++++++++----------------------------
1 files changed, 399 insertions(+), 370 deletions(-)
diff --git a/kernel/drivers/media/i2c/gc2093.c b/kernel/drivers/media/i2c/gc2093.c
index 399eace..f612814 100644
--- a/kernel/drivers/media/i2c/gc2093.c
+++ b/kernel/drivers/media/i2c/gc2093.c
@@ -11,8 +11,6 @@
* 2. add hdr mode exposure limit issue.
* 3. fix hdr mode highlighting pink issue.
* 4. add some debug info.
- * V0.0X01.0X03 fix hdr mode not support vts change
- * V0.0X01.0X04 add 24M MCLK register setting.
*/
//#define DEBUG
#include <linux/clk.h>
@@ -34,22 +32,17 @@
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
+#include "../platform/rockchip/isp/rkisp_tb_helper.h"
+#include "cam-tb-setup.h"
-#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
+#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
#define GC2093_NAME "gc2093"
#define GC2093_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
#define MIPI_FREQ_297M 297000000
#define MIPI_FREQ_396M 396000000
-/* 27M or 24M */
-#define MCLK_27M
-
-#ifdef MCLK_27M
#define GC2093_XVCLK_FREQ 27000000
-#else
-#define GC2093_XVCLK_FREQ 24000000
-#endif
#define GC2093_REG_CHIP_ID_H 0x03F0
#define GC2093_REG_CHIP_ID_L 0x03F1
@@ -90,6 +83,8 @@
#define GC2093_LANES 2
+#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
+
static const char * const gc2093_supply_names[] = {
"dovdd", /* Digital I/O power */
"avdd", /* Analog power */
@@ -99,14 +94,6 @@
#define GC2093_NUM_SUPPLIES ARRAY_SIZE(gc2093_supply_names)
#define to_gc2093(sd) container_of(sd, struct gc2093, subdev)
-
-enum {
- PAD0,
- PAD1,
- PAD2,
- PAD3,
- PAD_MAX,
-};
enum {
LINK_FREQ_297M_INDEX,
@@ -158,16 +145,19 @@
struct mutex lock;
bool streaming;
bool power_on;
- unsigned int cfg_num;
const struct gc2093_mode *cur_mode;
u32 module_index;
const char *module_facing;
const char *module_name;
const char *len_name;
- u32 cur_vts;
- bool has_init_exp;
+ struct v4l2_fract cur_fps;
+ u32 cur_vts;
+
+ bool has_init_exp;
+ bool is_thunderboot;
+ bool is_first_streamoff;
struct preisp_hdrae_exp_s init_hdrae_exp;
};
@@ -189,7 +179,6 @@
* row_time=29.62us frame_rate=30fps
*/
static const struct reg_sequence gc2093_1080p_liner_settings[] = {
-#ifdef MCLK_27M
/* System */
{0x03fe, 0x80},
{0x03fe, 0x80},
@@ -300,157 +289,6 @@
{0x0212, 0x80},
{0x0213, 0x07},
{0x003e, 0x91},
-#else
- /****system****/
- {0x03fe, 0xf0},
- {0x03fe, 0xf0},
- {0x03fe, 0xf0},
- {0x03fe, 0x00},
- {0x03f2, 0x00},
- {0x03f3, 0x00},
- {0x03f4, 0x36},
- {0x03f5, 0xc0},
- {0x03f6, 0x0B},
- {0x03f7, 0x11},
- {0x03f8, 0x30},
- {0x03f9, 0x42},
- {0x03fc, 0x8e},
- /****CISCTL & ANALOG****/
- {0x0087, 0x18},
- {0x00ee, 0x30},
- {0x00d0, 0xbf},
- {0x01a0, 0x00},
- {0x01a4, 0x40},
- {0x01a5, 0x40},
- {0x01a6, 0x40},
- {0x01af, 0x09},
- {0x0003, 0x04},
- {0x0004, 0x65},
- {0x0005, 0x05},
- {0x0006, 0x8e},
- {0x0007, 0x00},
- {0x0008, 0x11},
- {0x0009, 0x00},
- {0x000a, 0x02},
- {0x000b, 0x00},
- {0x000c, 0x04},
- {0x000d, 0x04},
- {0x000e, 0x40},
- {0x000f, 0x07},
- {0x0010, 0x8c},
- {0x0013, 0x15},
- {0x0019, 0x0c},
- {0x0041, 0x04},
- {0x0042, 0x65},
- {0x0053, 0x60},
- {0x008d, 0x92},
- {0x0090, 0x00},
- {0x00c7, 0xe1},
- {0x001b, 0x73},
- {0x0028, 0x0d},
- {0x0029, 0x40},
- {0x002b, 0x04},
- {0x002e, 0x23},
- {0x0037, 0x03},
- {0x0043, 0x04},
- {0x0044, 0x30},
- {0x004a, 0x01},
- {0x004b, 0x28},
- {0x0055, 0x30},
- {0x0066, 0x3f},
- {0x0068, 0x3f},
- {0x006b, 0x44},
- {0x0077, 0x00},
- {0x0078, 0x20},
- {0x007c, 0xa1},
- {0x00ce, 0x7c},
- {0x00d3, 0xd4},
- {0x00e6, 0x50},
- /*gain*/
- {0x00b6, 0xc0},
- {0x00b0, 0x68},
- {0x00b3, 0x00},
- {0x00b8, 0x01},
- {0x00b9, 0x00},
- {0x00b1, 0x01},
- {0x00b2, 0x00},
- /*isp*/
- {0x0101, 0x0c},
- {0x0102, 0x89},
- {0x0104, 0x01},
- {0x0107, 0xa6},
- {0x0108, 0xa9},
- {0x0109, 0xa8},
- {0x010a, 0xa7},
- {0x010b, 0xff},
- {0x010c, 0xff},
- {0x010f, 0x00},
- {0x0158, 0x00},
- {0x0428, 0x86},
- {0x0429, 0x86},
- {0x042a, 0x86},
- {0x042b, 0x68},
- {0x042c, 0x68},
- {0x042d, 0x68},
- {0x042e, 0x68},
- {0x042f, 0x68},
- {0x0430, 0x4f},
- {0x0431, 0x68},
- {0x0432, 0x67},
- {0x0433, 0x66},
- {0x0434, 0x66},
- {0x0435, 0x66},
- {0x0436, 0x66},
- {0x0437, 0x66},
- {0x0438, 0x62},
- {0x0439, 0x62},
- {0x043a, 0x62},
- {0x043b, 0x62},
- {0x043c, 0x62},
- {0x043d, 0x62},
- {0x043e, 0x62},
- {0x043f, 0x62},
- /*dark sun*/
- {0x0123, 0x08},
- {0x0123, 0x00},
- {0x0120, 0x01},
- {0x0121, 0x04},
- {0x0122, 0x65},
- {0x0124, 0x03},
- {0x0125, 0xff},
- {0x001a, 0x8c},
- {0x00c6, 0xe0},
- /*blk*/
- {0x0026, 0x30},
- {0x0142, 0x00},
- {0x0149, 0x1e},
- {0x014a, 0x0f},
- {0x014b, 0x00},
- {0x0155, 0x07},
- {0x0414, 0x78},
- {0x0415, 0x78},
- {0x0416, 0x78},
- {0x0417, 0x78},
- {0x04e0, 0x18},
- /*window*/
- {0x0192, 0x02},
- {0x0194, 0x03},
- {0x0195, 0x04},
- {0x0196, 0x38},
- {0x0197, 0x07},
- {0x0198, 0x80},
- /****DVP & MIPI****/
- {0x019a, 0x06},
- {0x007b, 0x2a},
- {0x0023, 0x2d},
- {0x0201, 0x27},
- {0x0202, 0x56},
- {0x0203, 0xb6},
- {0x0212, 0x80},
- {0x0213, 0x07},
- {0x0215, 0x10},
- {0x003e, 0x91},
-#endif
};
/*
@@ -460,7 +298,6 @@
* row_time=13.33us frame_rate=60fps
*/
static const struct reg_sequence gc2093_1080p_hdr_settings[] = {
-#ifdef MCLK_27M
/* System */
{0x03fe, 0x80},
{0x03fe, 0x80},
@@ -502,7 +339,139 @@
{0x0010, 0x8c},
{0x0013, 0x15},
{0x0019, 0x0c},
- {0x0041, 0x05}, //30fps: 0x4e2; 25FPS: 0x5dc: 20FPS: 0x753
+ {0x0041, 0x04},
+ {0x0042, 0xe2},
+ {0x0053, 0x60},
+ {0x008d, 0x92},
+ {0x0090, 0x00},
+ {0x00c7, 0xe1},
+ {0x001b, 0x73},
+ {0x0028, 0x0d},
+ {0x0029, 0x24},
+ {0x002b, 0x04},
+ {0x002e, 0x23},
+ {0x0037, 0x03},
+ {0x0043, 0x04},
+ {0x0044, 0x20},
+ {0x004a, 0x01},
+ {0x004b, 0x20},
+ {0x0055, 0x30},
+ {0x006b, 0x44},
+ {0x0077, 0x00},
+ {0x0078, 0x20},
+ {0x007c, 0xa1},
+ {0x00d3, 0xd4},
+ {0x00e6, 0x50},
+ /* Gain */
+ {0x00b6, 0xc0},
+ {0x00b0, 0x60},
+ /* Isp */
+ {0x0102, 0x89},
+ {0x0104, 0x01},
+ {0x010e, 0x01},
+ {0x0158, 0x00},
+ {0x0183, 0x01},
+ {0x0187, 0x50},
+ /* Dark sun*/
+ {0x0123, 0x08},
+ {0x0123, 0x00},
+ {0x0120, 0x01},
+ {0x0121, 0x00},
+ {0x0122, 0x10},
+ {0x0124, 0x03},
+ {0x0125, 0xff},
+ {0x0126, 0x3c},
+ {0x001a, 0x8c},
+ {0x00c6, 0xe0},
+ /* Blk */
+ {0x0026, 0x30},
+ {0x0142, 0x00},
+ {0x0149, 0x1e},
+ {0x014a, 0x0f},
+ {0x014b, 0x00},
+ {0x0155, 0x00},
+ {0x0414, 0x78},
+ {0x0415, 0x78},
+ {0x0416, 0x78},
+ {0x0417, 0x78},
+ {0x0454, 0x78},
+ {0x0455, 0x78},
+ {0x0456, 0x78},
+ {0x0457, 0x78},
+ {0x04e0, 0x18},
+ /* Window */
+ {0x0192, 0x02},
+ {0x0194, 0x03},
+ {0x0195, 0x04},
+ {0x0196, 0x38},
+ {0x0197, 0x07},
+ {0x0198, 0x80},
+ /* MIPI */
+ {0x019a, 0x06},
+ {0x007b, 0x2a},
+ {0x0023, 0x2d},
+ {0x0201, 0x27},
+ {0x0202, 0x56},
+ {0x0203, 0xb6},
+ {0x0212, 0x80},
+ {0x0213, 0x07},
+ {0x0215, 0x12},
+ {0x003e, 0x91},
+ /* HDR En */
+ {0x0027, 0x71},
+ {0x0215, 0x92},
+ {0x024d, 0x01},
+};
+
+/*
+ * window size=1920*1080 mipi@2lane
+ * mclk=27M mipi_clk=792Mbps
+ * pixel_line_total=2640 line_frame_total=1500
+ * row_time=20us frame_rate=50fps
+ */
+static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = {
+ /* System */
+ {0x03fe, 0x80},
+ {0x03fe, 0x80},
+ {0x03fe, 0x80},
+ {0x03fe, 0x00},
+ {0x03f2, 0x00},
+ {0x03f3, 0x00},
+ {0x03f4, 0x36},
+ {0x03f5, 0xc0},
+ {0x03f6, 0x0B},
+ {0x03f7, 0x01},
+ {0x03f8, 0x58},
+ {0x03f9, 0x40},
+ {0x03fc, 0x8e},
+ /* Cisctl & Analog */
+ {0x0087, 0x18},
+ {0x00ee, 0x30},
+ {0x00d0, 0xbf},
+ {0x01a0, 0x00},
+ {0x01a4, 0x40},
+ {0x01a5, 0x40},
+ {0x01a6, 0x40},
+ {0x01af, 0x09},
+ {0x0001, 0x00},
+ {0x0002, 0x02},
+ {0x0003, 0x04},
+ {0x0004, 0x02},
+ {0x0005, 0x02},
+ {0x0006, 0x94},
+ {0x0007, 0x00},
+ {0x0008, 0x11},
+ {0x0009, 0x00},
+ {0x000a, 0x02},
+ {0x000b, 0x00},
+ {0x000c, 0x04},
+ {0x000d, 0x04},
+ {0x000e, 0x40},
+ {0x000f, 0x07},
+ {0x0010, 0x8c},
+ {0x0013, 0x15},
+ {0x0019, 0x0c},
+ {0x0041, 0x05},
{0x0042, 0xdc},
{0x0053, 0x60},
{0x008d, 0x92},
@@ -584,135 +553,6 @@
{0x0027, 0x71},
{0x0215, 0x92},
{0x024d, 0x01},
-#else
- /****system****/
- {0x03fe, 0xf0},
- {0x03fe, 0xf0},
- {0x03fe, 0xf0},
- {0x03fe, 0x00},
- {0x03f2, 0x00},
- {0x03f3, 0x00},
- {0x03f4, 0x36},
- {0x03f5, 0xc0},
- {0x03f6, 0x0B},
- {0x03f7, 0x01},
- {0x03f8, 0x63},
- {0x03f9, 0x40},
- {0x03fc, 0x8e},
- /****CISCTL & ANALOG****/
- {0x0087, 0x18},
- {0x00ee, 0x30},
- {0x00d0, 0xbf},
- {0x01a0, 0x00},
- {0x01a4, 0x40},
- {0x01a5, 0x40},
- {0x01a6, 0x40},
- {0x01af, 0x09},
- {0x0001, 0x00},
- {0x0002, 0x02},
- {0x0003, 0x04},
- {0x0004, 0x02},
- {0x0005, 0x02},
- {0x0006, 0x94},
- {0x0007, 0x00},
- {0x0008, 0x11},
- {0x0009, 0x00},
- {0x000a, 0x02},
- {0x000b, 0x00},
- {0x000c, 0x04},
- {0x000d, 0x04},
- {0x000e, 0x40},
- {0x000f, 0x07},
- {0x0010, 0x8c},
- {0x0013, 0x15},
- {0x0019, 0x0c},
- {0x0041, 0x05}, //30fps: 0x4e2; 25FPS: 0x5dc: 20FPS: 0x753
- {0x0042, 0xdc},
- {0x0053, 0x60},
- {0x008d, 0x92},
- {0x0090, 0x00},
- {0x00c7, 0xe1},
- {0x001b, 0x73},
- {0x0028, 0x0d},
- {0x0029, 0x24},
- {0x002b, 0x04},
- {0x002e, 0x23},
- {0x0037, 0x03},
- {0x0043, 0x04},
- {0x0044, 0x28},
- {0x004a, 0x01},
- {0x004b, 0x20},
- {0x0055, 0x28},
- {0x0066, 0x3f},
- {0x0068, 0x3f},
- {0x006b, 0x44},
- {0x0077, 0x00},
- {0x0078, 0x20},
- {0x007c, 0xa1},
- {0x00ce, 0x7c},
- {0x00d3, 0xd4},
- {0x00e6, 0x50},
- /*gain*/
- {0x00b6, 0xc0},
- {0x00b0, 0x68},
- /*isp*/
- {0x0101, 0x0c},
- {0x0102, 0x89},
- {0x0104, 0x01},
- {0x010e, 0x01},
- {0x010f, 0x00},
- {0x0158, 0x00},
- {0x0183, 0x01},
- {0x0187, 0x50},
- /*dark sun*/
- {0x0123, 0x08},
- {0x0123, 0x00},
- {0x0120, 0x01},
- {0x0121, 0x04},
- {0x0122, 0xd8},
- {0x0124, 0x03},
- {0x0125, 0xff},
- {0x001a, 0x8c},
- {0x00c6, 0xe0},
- /*blk*/
- {0x0026, 0x30},
- {0x0142, 0x00},
- {0x0149, 0x1e},
- {0x014a, 0x0f},
- {0x014b, 0x00},
- {0x0155, 0x07},
- {0x0414, 0x78},
- {0x0415, 0x78},
- {0x0416, 0x78},
- {0x0417, 0x78},
- {0x0454, 0x78},
- {0x0455, 0x78},
- {0x0456, 0x78},
- {0x0457, 0x78},
- {0x04e0, 0x18},
- /*window*/
- {0x0192, 0x02},
- {0x0194, 0x03},
- {0x0195, 0x04},
- {0x0196, 0x38},
- {0x0197, 0x07},
- {0x0198, 0x80},
- /****DVP & MIPI****/
- {0x019a, 0x06},
- {0x007b, 0x2a},
- {0x0023, 0x2d},
- {0x0201, 0x27},
- {0x0202, 0x56},
- {0x0203, 0xb6}, //try 0xce or 0x8e
- {0x0212, 0x80},
- {0x0213, 0x07},
- {0x0215, 0x10},
- {0x003e, 0x91},
- /****HDR EN****/
- {0x0027, 0x71},
- {0x0215, 0x92},
- {0x024d, 0x01},
-#endif
};
static const struct gc2093_mode supported_modes[] = {
@@ -737,14 +577,33 @@
.height = 1080,
.max_fps = {
.numerator = 10000,
+ .denominator = 300000,
+ },
+ .exp_def = 0x460,
+ .hts_def = 0xa50,
+ .vts_def = 0x4e2,
+ .link_freq_index = LINK_FREQ_396M_INDEX,
+ .reg_list = gc2093_1080p_hdr_settings,
+ .reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
+ .hdr_mode = HDR_X2,
+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
+ .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
+ .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
+ .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
+ },
+ {
+ .width = 1920,
+ .height = 1080,
+ .max_fps = {
+ .numerator = 10000,
.denominator = 250000,
},
.exp_def = 0x460,
.hts_def = 0xa50,
- .vts_def = 0x5dc,//30fps: 0x4e2; 25FPS: 0x5dc: 20FPS: 0x753
+ .vts_def = 0x5dc,
.link_freq_index = LINK_FREQ_396M_INDEX,
- .reg_list = gc2093_1080p_hdr_settings,
- .reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
+ .reg_list = gc2093_1080p_25fps_hdr_settings,
+ .reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings),
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
@@ -847,6 +706,14 @@
return ret;
}
+static void gc2093_modify_fps_info(struct gc2093 *gc2093)
+{
+ const struct gc2093_mode *mode = gc2093->cur_mode;
+
+ gc2093->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
+ gc2093->cur_vts;
+}
+
static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct gc2093 *gc2093 = container_of(ctrl->handler,
@@ -871,6 +738,7 @@
switch (ctrl->id) {
case V4L2_CID_EXPOSURE:
+ dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
if (gc2093->cur_mode->hdr_mode != NO_HDR)
goto ctrl_end;
dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
@@ -880,29 +748,36 @@
ctrl->val & 0xff);
break;
case V4L2_CID_ANALOGUE_GAIN:
+ dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n",
+ ctrl->val, gc2093->cur_mode->hdr_mode);
if (gc2093->cur_mode->hdr_mode != NO_HDR)
goto ctrl_end;
dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
gc2093_set_gain(gc2093, ctrl->val);
break;
case V4L2_CID_VBLANK:
- if (gc2093->cur_mode->hdr_mode != NO_HDR)
- goto ctrl_end;
+ dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val);
vts = gc2093->cur_mode->height + ctrl->val;
gc2093->cur_vts = vts;
ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
(vts >> 8) & 0x3f);
ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
vts & 0xff);
+ if (!ret)
+ gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height;
+ if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
+ gc2093_modify_fps_info(gc2093);
dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
break;
case V4L2_CID_HFLIP:
- regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
- MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
+ dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val);
+ regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
+ MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
break;
case V4L2_CID_VFLIP:
- regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
- FLIP_MASK, ctrl->val ? FLIP_MASK : 0);
+ dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val);
+ regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
+ FLIP_MASK, ctrl->val ? FLIP_MASK : 0);
break;
default:
dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
@@ -959,7 +834,7 @@
h_blank, h_blank, 1, h_blank);
if (gc2093->hblank)
gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
-
+ gc2093->cur_fps = mode->max_fps;
vblank_def = mode->vts_def - mode->height;
gc2093->cur_vts = mode->vts_def;
gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
@@ -992,6 +867,8 @@
gc2093->subdev.ctrl_handler = handler;
gc2093->has_init_exp = false;
+ gc2093->cur_vts = mode->vts_def;
+ gc2093->cur_fps = mode->max_fps;
return 0;
@@ -1018,6 +895,9 @@
return ret;
}
+ if (gc2093->is_thunderboot)
+ return 0;
+
ret = regulator_bulk_enable(GC2093_NUM_SUPPLIES, gc2093->supplies);
if (ret < 0) {
dev_err(dev, "Failed to enable regulators\n");
@@ -1025,14 +905,14 @@
}
if (!IS_ERR(gc2093->reset_gpio))
- gpiod_set_value_cansleep(gc2093->reset_gpio, 1);
+ gpiod_direction_output(gc2093->reset_gpio, 1);
usleep_range(1000, 2000);
if (!IS_ERR(gc2093->pwdn_gpio))
- gpiod_set_value_cansleep(gc2093->pwdn_gpio, 1);
+ gpiod_direction_output(gc2093->pwdn_gpio, 1);
if (!IS_ERR(gc2093->reset_gpio))
- gpiod_set_value_cansleep(gc2093->reset_gpio, 0);
+ gpiod_direction_output(gc2093->reset_gpio, 0);
usleep_range(10000, 20000);
@@ -1045,20 +925,35 @@
static void __gc2093_power_off(struct gc2093 *gc2093)
{
+ clk_disable_unprepare(gc2093->xvclk);
+ if (gc2093->is_thunderboot) {
+ if (gc2093->is_first_streamoff) {
+ gc2093->is_thunderboot = false;
+ gc2093->is_first_streamoff = false;
+ } else {
+ return;
+ }
+ }
+
if (!IS_ERR(gc2093->reset_gpio))
- gpiod_set_value_cansleep(gc2093->reset_gpio, 1);
+ gpiod_direction_output(gc2093->reset_gpio, 1);
if (!IS_ERR(gc2093->pwdn_gpio))
- gpiod_set_value_cansleep(gc2093->pwdn_gpio, 0);
+ gpiod_direction_output(gc2093->pwdn_gpio, 0);
regulator_bulk_disable(GC2093_NUM_SUPPLIES, gc2093->supplies);
- clk_disable_unprepare(gc2093->xvclk);
}
static int gc2093_check_sensor_id(struct gc2093 *gc2093)
{
+ struct device *dev = gc2093->dev;
u8 id_h = 0, id_l = 0;
u16 id = 0;
int ret = 0;
+
+ if (gc2093->is_thunderboot) {
+ dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
+ return 0;
+ }
ret = gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_H, &id_h);
ret |= gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_L, &id_l);
@@ -1086,11 +981,24 @@
strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
}
+static int gc2093_get_channel_info(struct gc2093 *gc2093,
+ struct rkmodule_channel_info *ch_info)
+{
+ if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
+ return -EINVAL;
+ ch_info->vc = gc2093->cur_mode->vc[ch_info->index];
+ ch_info->width = gc2093->cur_mode->width;
+ ch_info->height = gc2093->cur_mode->height;
+ ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT;
+ return 0;
+}
+
static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct gc2093 *gc2093 = to_gc2093(sd);
struct preisp_hdrae_exp_s *hdrae_exp = arg;
struct rkmodule_hdr_cfg *hdr_cfg;
+ struct rkmodule_channel_info *ch_info;
long ret = 0;
u32 i, h, w;
u32 stream = 0;
@@ -1107,8 +1015,7 @@
dev_info(gc2093->dev, "don't streaming, record hdrae\n");
break;
}
- /* group hold start*/
- gc2093_write_reg(gc2093, 0x031d, 0x2c);
+
ret = gc2093_set_gain(gc2093, hdrae_exp->short_gain_reg);
if (ret) {
dev_err(gc2093->dev, "Failed to set gain!)\n");
@@ -1171,8 +1078,6 @@
(short_exp >> 8) & 0x3f);
ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_SHORT_L,
short_exp & 0xff);
- /* group hold end*/
- gc2093_write_reg(gc2093, 0x031d, 0x28);
break;
case RKMODULE_GET_HDR_CFG:
hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
@@ -1183,15 +1088,18 @@
hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
w = gc2093->cur_mode->width;
h = gc2093->cur_mode->height;
- for (i = 0; i < gc2093->cfg_num; i++) {
+ for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
if (w == supported_modes[i].width &&
h == supported_modes[i].height &&
supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
gc2093->cur_mode = &supported_modes[i];
break;
}
+ dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n",
+ i, supported_modes[i].width, supported_modes[i].height,
+ supported_modes[i].hdr_mode);
}
- if (i == gc2093->cfg_num) {
+ if (i == ARRAY_SIZE(supported_modes)) {
dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
hdr_cfg->hdr_mode, w, h);
ret = -EINVAL;
@@ -1203,6 +1111,7 @@
GC2093_VTS_MAX - gc2093->cur_mode->height,
1, h);
gc2093->cur_vts = gc2093->cur_mode->vts_def;
+ gc2093->cur_fps = gc2093->cur_mode->max_fps;
dev_info(gc2093->dev, "sensor mode: %d\n",
gc2093->cur_mode->hdr_mode);
}
@@ -1226,6 +1135,10 @@
usleep_range(delay_us, delay_us + 2000);
}
break;
+ case RKMODULE_GET_CHANNEL_INFO:
+ ch_info = (struct rkmodule_channel_info *)arg;
+ ret = gc2093_get_channel_info(gc2093, ch_info);
+ break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -1237,33 +1150,46 @@
{
int ret;
- ret = regmap_multi_reg_write(gc2093->regmap,
- gc2093->cur_mode->reg_list,
- gc2093->cur_mode->reg_num);
- if (ret)
- return ret;
-
- /* Apply customized control from user */
- mutex_unlock(&gc2093->lock);
- v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
- mutex_lock(&gc2093->lock);
-
- if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
- ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
- &gc2093->init_hdrae_exp);
- if (ret) {
- dev_err(gc2093->dev, "init exp fail in hdr mode\n");
+ if (!gc2093->is_thunderboot) {
+ ret = regmap_multi_reg_write(gc2093->regmap,
+ gc2093->cur_mode->reg_list,
+ gc2093->cur_mode->reg_num);
+ if (ret)
return ret;
+
+ /* Apply customized control from user */
+ mutex_unlock(&gc2093->lock);
+ v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
+ mutex_lock(&gc2093->lock);
+
+ if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
+ ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
+ &gc2093->init_hdrae_exp);
+ if (ret) {
+ dev_err(gc2093->dev, "init exp fail in hdr mode\n");
+ return ret;
+ }
}
}
-
+ dev_info(gc2093->dev,
+ "%dx%d@%d, mode %d, vts 0x%x\n",
+ gc2093->cur_mode->width,
+ gc2093->cur_mode->height,
+ gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
+ gc2093->cur_mode->hdr_mode,
+ gc2093->cur_vts);
+ dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot);
return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
- GC2093_MODE_STREAMING);
+ GC2093_MODE_STREAMING);
}
static int __gc2093_stop_stream(struct gc2093 *gc2093)
{
gc2093->has_init_exp = false;
+ if (gc2093->is_thunderboot) {
+ gc2093->is_first_streamoff = true;
+ pm_runtime_put(gc2093->dev);
+ }
return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
GC2093_MODE_SW_STANDBY);
}
@@ -1276,6 +1202,7 @@
struct rkmodule_inf *inf;
struct rkmodule_hdr_cfg *hdr;
struct preisp_hdrae_exp_s *hdrae;
+ struct rkmodule_channel_info *ch_info;
long ret = 0;
u32 stream = 0;
@@ -1345,6 +1272,21 @@
else
ret = -EFAULT;
break;
+ case RKMODULE_GET_CHANNEL_INFO:
+ ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
+ if (!ch_info) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ ret = gc2093_ioctl(sd, cmd, ch_info);
+ if (!ret) {
+ ret = copy_to_user(up, ch_info, sizeof(*ch_info));
+ if (ret)
+ ret = -EFAULT;
+ }
+ kfree(ch_info);
+ break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -1363,17 +1305,27 @@
fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
gc2093->cur_mode->max_fps.numerator);
- dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
- gc2093->cur_mode->width,
- gc2093->cur_mode->height,
- fps);
+ dev_info(gc2093->dev,
+ "%dx%d@%d, mode %d, vts 0x%x\n",
+ gc2093->cur_mode->width,
+ gc2093->cur_mode->height,
+ gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
+ gc2093->cur_mode->hdr_mode,
+ gc2093->cur_vts);
+ dev_info(gc2093->dev,
+ "stream:%d\n, on:%d",
+ gc2093->streaming, on);
mutex_lock(&gc2093->lock);
on = !!on;
if (on == gc2093->streaming)
goto unlock_and_return;
if (on) {
+ if (gc2093->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
+ gc2093->is_thunderboot = false;
+ __gc2093_power_on(gc2093);
+ }
ret = pm_runtime_get_sync(gc2093->dev);
if (ret < 0) {
pm_runtime_put_noidle(gc2093->dev);
@@ -1410,21 +1362,22 @@
struct gc2093 *gc2093 = to_gc2093(sd);
const struct gc2093_mode *mode = gc2093->cur_mode;
- mutex_lock(&gc2093->lock);
- fi->interval = mode->max_fps;
- mutex_unlock(&gc2093->lock);
+ if (gc2093->streaming)
+ fi->interval = gc2093->cur_fps;
+ else
+ fi->interval = mode->max_fps;
return 0;
}
-static int gc2093_g_mbus_config(struct v4l2_subdev *sd,
+static int gc2093_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc2093 *gc2093 = to_gc2093(sd);
u32 val = 1 << (GC2093_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
- config->type = V4L2_MBUS_CSI2;
+ config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = (gc2093->cur_mode->hdr_mode == NO_HDR) ?
val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
@@ -1445,9 +1398,7 @@
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
- struct gc2093 *gc2093 = to_gc2093(sd);
-
- if (fse->index >= gc2093->cfg_num)
+ if (fse->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
if (fse->code != GC2093_MEDIA_BUS_FMT)
@@ -1464,9 +1415,7 @@
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum *fie)
{
- struct gc2093 *gc2093 = to_gc2093(sd);
-
- if (fie->index >= gc2093->cfg_num)
+ if (fie->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
fie->code = GC2093_MEDIA_BUS_FMT;
@@ -1515,6 +1464,8 @@
__v4l2_ctrl_modify_range(gc2093->vblank, vblank_def,
GC2093_VTS_MAX - mode->height,
1, vblank_def);
+ gc2093->cur_vts = mode->vts_def;
+ gc2093->cur_fps = mode->max_fps;
}
mutex_unlock(&gc2093->lock);
@@ -1618,7 +1569,6 @@
static const struct v4l2_subdev_video_ops gc2093_video_ops = {
.s_stream = gc2093_s_stream,
.g_frame_interval = gc2093_g_frame_interval,
- .g_mbus_config = gc2093_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
@@ -1627,6 +1577,7 @@
.enum_frame_interval = gc2093_enum_frame_interval,
.get_fmt = gc2093_get_fmt,
.set_fmt = gc2093_set_fmt,
+ .get_mbus_config = gc2093_g_mbus_config,
};
static const struct v4l2_subdev_ops gc2093_subdev_ops = {
@@ -1635,7 +1586,7 @@
.pad = &gc2093_pad_ops,
};
-static int gc2093_runtime_resume(struct device *dev)
+static int __maybe_unused gc2093_runtime_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *sd = i2c_get_clientdata(client);
@@ -1645,7 +1596,7 @@
return 0;
}
-static int gc2093_runtime_suspend(struct device *dev)
+static int __maybe_unused gc2093_runtime_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *sd = i2c_get_clientdata(client);
@@ -1659,6 +1610,78 @@
SET_RUNTIME_PM_OPS(gc2093_runtime_suspend,
gc2093_runtime_resume, NULL)
};
+
+
+#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
+static void find_terminal_resolution(struct gc2093 *gc2093)
+{
+ int i = 0;
+ const struct gc2093_mode *mode = NULL;
+ const struct gc2093_mode *fit_mode = NULL;
+ u32 cur_fps = 0;
+ u32 dst_fps = 0;
+ u32 tmp_fps = 0;
+ u32 rk_cam_hdr = get_rk_cam_hdr();
+ u32 rk_cam_w = get_rk_cam_w();
+ u32 rk_cam_h = get_rk_cam_h();
+ u32 rk_cam_fps = get_rk_cam_fps();
+
+ if (rk_cam_w == 0 || rk_cam_h == 0 ||
+ rk_cam_fps == 0)
+ goto err_find_res;
+
+ dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n",
+ rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps);
+ dst_fps = rk_cam_fps;
+ for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
+ mode = &supported_modes[i];
+ cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
+ if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
+ mode->hdr_mode == rk_cam_hdr) {
+ if (cur_fps == dst_fps) {
+ gc2093->cur_mode = mode;
+ return;
+ }
+ if (cur_fps >= dst_fps) {
+ if (fit_mode) {
+ tmp_fps = fit_mode->max_fps.denominator /
+ fit_mode->max_fps.numerator;
+ if (tmp_fps - dst_fps > cur_fps - dst_fps)
+ fit_mode = mode;
+ } else {
+ fit_mode = mode;
+ }
+ }
+ }
+ }
+ if (fit_mode) {
+ gc2093->cur_mode = fit_mode;
+ return;
+ }
+err_find_res:
+ dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!",
+ rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
+ gc2093->cur_mode = &supported_modes[0];
+}
+#else
+static void find_terminal_resolution(struct gc2093 *gc2093)
+{
+ u32 hdr_mode = 0;
+ struct device_node *node = gc2093->dev->of_node;
+ int i = 0;
+
+ of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
+ for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
+ if (hdr_mode == supported_modes[i].hdr_mode) {
+ gc2093->cur_mode = &supported_modes[i];
+ break;
+ }
+ }
+ if (i == ARRAY_SIZE(supported_modes))
+ gc2093->cur_mode = &supported_modes[0];
+
+}
+#endif
static int gc2093_probe(struct i2c_client *client,
const struct i2c_device_id *id)
@@ -1699,17 +1722,21 @@
return -EINVAL;
}
+ gc2093->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
+
gc2093->xvclk = devm_clk_get(gc2093->dev, "xvclk");
if (IS_ERR(gc2093->xvclk)) {
dev_err(gc2093->dev, "Failed to get xvclk\n");
return -EINVAL;
}
- gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ find_terminal_resolution(gc2093);
+
+ gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
if (IS_ERR(gc2093->reset_gpio))
dev_warn(dev, "Failed to get reset-gpios\n");
- gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
+ gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
if (IS_ERR(gc2093->pwdn_gpio))
dev_warn(dev, "Failed to get pwdn-gpios\n");
@@ -1720,11 +1747,6 @@
}
mutex_init(&gc2093->lock);
-
- /* set default mode */
- gc2093->cur_mode = &supported_modes[0];
- gc2093->cfg_num = ARRAY_SIZE(supported_modes);
- gc2093->cur_vts = gc2093->cur_mode->vts_def;
sd = &gc2093->subdev;
v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);
@@ -1771,7 +1793,10 @@
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
- pm_runtime_idle(dev);
+ if (gc2093->is_thunderboot)
+ pm_runtime_get_sync(dev);
+ else
+ pm_runtime_idle(dev);
return 0;
@@ -1839,7 +1864,11 @@
i2c_del_driver(&gc2093_i2c_driver);
}
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
+subsys_initcall(sensor_mod_init);
+#else
device_initcall_sync(sensor_mod_init);
+#endif
module_exit(sensor_mod_exit);
MODULE_DESCRIPTION("Galaxycore GC2093 Image Sensor driver");
--
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