From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c | 164 ++++++++++++++++++++++++++++--------------------------
1 files changed, 86 insertions(+), 78 deletions(-)
diff --git a/kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c b/kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c
index 9628d40..499b37b 100644
--- a/kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c
+++ b/kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c
@@ -380,10 +380,10 @@
*/
/*****************************************************************************/
-/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
-/* RAM adresses directly. This must be READ ONLY to avoid problems. */
-/* Writing to the interface adresses is more than only writing the RAM */
-/* locations */
+/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
+/* RAM addresses directly. This must be READ ONLY to avoid problems. */
+/* Writing to the interface addresses are more than only writing the RAM */
+/* locations */
/*****************************************************************************/
/*
* \brief RAM location of MODUS registers
@@ -656,8 +656,8 @@
false, /* flag: true=bypass */
ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
- true, /* flag CVBS ouput enable */
- false, /* flag SIF ouput enable */
+ true, /* flag CVBS output enable */
+ false, /* flag SIF output enable */
DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
{ /* qam_rf_agc_cfg */
DRX_STANDARD_ITU_B, /* standard */
@@ -832,7 +832,7 @@
false, /* If true mirror frequency spectrum */
{
/* MPEG output configuration */
- true, /* If true, enable MPEG ouput */
+ true, /* If true, enable MPEG output */
false, /* If true, insert RS byte */
false, /* If true, parallel out otherwise serial */
false, /* If true, invert DATA signals */
@@ -848,7 +848,7 @@
DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
},
/* Initilisations below can be omitted, they require no user input and
- are initialy 0, NULL or false. The compiler will initialize them to these
+ are initially 0, NULL or false. The compiler will initialize them to these
values when omitted. */
false, /* is_opened */
@@ -869,7 +869,7 @@
DRX_POWER_UP,
/* Tuner */
- 1, /* nr of I2C port to wich tuner is */
+ 1, /* nr of I2C port to which tuner is */
0L, /* minimum RF input frequency, in kHz */
0L, /* maximum RF input frequency, in kHz */
false, /* Rf Agc Polarity */
@@ -1656,7 +1656,7 @@
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
- Address must be rewriten because HI is reset after data transport and
+ Address must be rewritten because HI is reset after data transport and
expects an address.
*/
todo = (block_size < datasize ? block_size : datasize);
@@ -1820,7 +1820,7 @@
* \param wdata Data to write
* \param rdata Buffer for data to read
* \return int
-* \retval 0 Succes
+* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register read modify write access using short addressing format only.
@@ -1897,7 +1897,7 @@
* \param addr
* \param data
* \return int
-* \retval 0 Succes
+* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register read access via audio token ring interface.
@@ -2004,7 +2004,7 @@
* \param addr
* \param data
* \return int
-* \retval 0 Succes
+* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
* 16 bits register write access via audio token ring interface.
@@ -2094,7 +2094,7 @@
* \param datasize size of data buffer in bytes
* \param data pointer to data buffer
* \return int
-* \retval 0 Succes
+* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
*/
@@ -2182,7 +2182,7 @@
u32 *data, u32 flags)
{
u8 buf[sizeof(*data)] = { 0 };
- int rc = -EIO;
+ int rc;
u32 word = 0;
if (!data)
@@ -2306,7 +2306,7 @@
pr_err("error %d\n", rc);
goto rw_error;
}
- /* fallthrough */
+ fallthrough;
case SIO_HI_RA_RAM_CMD_BRDCTRL:
rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
if (rc != 0) {
@@ -2318,7 +2318,7 @@
pr_err("error %d\n", rc);
goto rw_error;
}
- /* fallthrough */
+ fallthrough;
case SIO_HI_RA_RAM_CMD_NULL:
/* No parameters */
break;
@@ -2338,7 +2338,7 @@
if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
msleep(1);
- /* Detect power down to ommit reading result */
+ /* Detect power down to omit reading result */
powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
(((cmd->
param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
@@ -2754,7 +2754,7 @@
common_attr = (struct drx_common_attr *) demod->my_common_attr;
if (cfg_data->enable_mpeg_output == true) {
- /* quick and dirty patch to set MPEG incase current std is not
+ /* quick and dirty patch to set MPEG in case current std is not
producing MPEG */
switch (ext_attr->standard) {
case DRX_STANDARD_8VSB:
@@ -2841,7 +2841,7 @@
/* coef = 188/204 */
max_bit_rate =
(ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
- /* fall-through - as b/c Annex A/C need following settings */
+ fallthrough; /* as b/c Annex A/C need following settings */
case DRX_STANDARD_ITU_B:
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
if (rc != 0) {
@@ -2894,7 +2894,7 @@
break;
default:
break;
- } /* swtich (standard) */
+ } /* switch (standard) */
/* Check insertion of the Reed-Solomon parity bytes */
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
@@ -3555,8 +3555,8 @@
if (!ext_attr->has_smatx)
return -EIO;
switch (uio_cfg->mode) {
- case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
- case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */
+ case DRX_UIO_MODE_FIRMWARE_SMA:
+ case DRX_UIO_MODE_FIRMWARE_SAW:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_sma_tx_mode = uio_cfg->mode;
break;
@@ -3579,7 +3579,7 @@
if (!ext_attr->has_smarx)
return -EIO;
switch (uio_cfg->mode) {
- case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
+ case DRX_UIO_MODE_FIRMWARE0:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_sma_rx_mode = uio_cfg->mode;
break;
@@ -3603,7 +3603,7 @@
if (!ext_attr->has_gpio)
return -EIO;
switch (uio_cfg->mode) {
- case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
+ case DRX_UIO_MODE_FIRMWARE0:
case DRX_UIO_MODE_READWRITE:
ext_attr->uio_gpio_mode = uio_cfg->mode;
break;
@@ -3639,7 +3639,7 @@
}
ext_attr->uio_irqn_mode = uio_cfg->mode;
break;
- case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
+ case DRX_UIO_MODE_FIRMWARE0:
default:
return -EINVAL;
break;
@@ -4004,31 +4004,36 @@
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 4:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 3:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 2:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 1:
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 0:
/* do nothing */
break;
@@ -4068,25 +4073,29 @@
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 3:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 2:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 1:
rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
- } /* fallthrough */
+ }
+ fallthrough;
case 0:
/* do nothing */
break;
@@ -4127,7 +4136,7 @@
* \param datasize size of data buffer in bytes
* \param data pointer to data buffer
* \return int
-* \retval 0 Succes
+* \retval 0 Success
* \retval -EIO Timeout, I2C error, illegal bank
*
*/
@@ -4201,7 +4210,7 @@
u16 *data, u32 flags)
{
u8 buf[2] = { 0 };
- int rc = -EIO;
+ int rc;
u16 word = 0;
if (!data)
@@ -4229,7 +4238,7 @@
u16 data, u32 flags)
{
u8 buf[2];
- int rc = -EIO;
+ int rc;
buf[0] = (u8) (data & 0xff);
buf[1] = (u8) ((data >> 8) & 0xff);
@@ -4791,7 +4800,7 @@
Sound carrier is already 3Mhz above centre frequency due
to tuner setting so now add an extra shift of 1MHz... */
fm_frequency_shift = 1000;
- /*fall through */
+ fallthrough;
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_NTSC:
case DRX_STANDARD_PAL_SECAM_BG:
@@ -8989,7 +8998,7 @@
((jiffies_to_msecs(jiffies) - start_time) <
(DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
);
- /* Returning control to apllication ... */
+ /* Returning control to application ... */
return 0;
rw_error:
@@ -9309,7 +9318,7 @@
return -EINVAL;
/* all reported errors are received in the */
- /* most recently finished measurment period */
+ /* most recently finished measurement period */
/* no of pre RS bit errors */
rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
if (rc != 0) {
@@ -9689,7 +9698,7 @@
(3) SIF AGC (used to amplify the output signal in case input to low)
The SIF AGC is now coupled to the RF/IF AGCs.
- The SIF AGC is needed for both SIF ouput and the internal SIF signal to
+ The SIF AGC is needed for both SIF output and the internal SIF signal to
the AUD block.
RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
@@ -9702,11 +9711,11 @@
later on because of the schedule)
Several HW/SCU "settings" can be used for ATV. The standard selection
- will reset most of these settings. To avoid that the end user apllication
+ will reset most of these settings. To avoid that the end user application
has to perform these settings each time the ATV or FM standards is
selected the driver will shadow these settings. This enables the end user
to perform the settings only once after a drx_open(). The driver must
- write the shadow settings to HW/SCU incase:
+ write the shadow settings to HW/SCU in case:
( setstandard FM/ATV) ||
( settings have changed && FM/ATV standard is active)
The shadow settings will be stored in the device specific data container.
@@ -9908,7 +9917,7 @@
#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
-/* Coefficients for the nyquist fitler (total: 27 taps) */
+/* Coefficients for the nyquist filter (total: 27 taps) */
#define NYQFILTERLEN 27
static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
@@ -10475,11 +10484,11 @@
(standard == DRX_STANDARD_NTSC)) {
switch (channel->bandwidth) {
case DRX_BANDWIDTH_6MHZ:
- case DRX_BANDWIDTH_UNKNOWN: /* fall through */
+ case DRX_BANDWIDTH_UNKNOWN:
channel->bandwidth = DRX_BANDWIDTH_6MHZ;
break;
- case DRX_BANDWIDTH_8MHZ: /* fall through */
- case DRX_BANDWIDTH_7MHZ: /* fall through */
+ case DRX_BANDWIDTH_8MHZ:
+ case DRX_BANDWIDTH_7MHZ:
default:
return -EINVAL;
}
@@ -10511,10 +10520,10 @@
}
switch (channel->constellation) {
- case DRX_CONSTELLATION_QAM16: /* fall through */
- case DRX_CONSTELLATION_QAM32: /* fall through */
- case DRX_CONSTELLATION_QAM64: /* fall through */
- case DRX_CONSTELLATION_QAM128: /* fall through */
+ case DRX_CONSTELLATION_QAM16:
+ case DRX_CONSTELLATION_QAM32:
+ case DRX_CONSTELLATION_QAM64:
+ case DRX_CONSTELLATION_QAM128:
case DRX_CONSTELLATION_QAM256:
bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
bandwidth = bandwidth_temp / 100;
@@ -10628,8 +10637,8 @@
}
break;
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = set_qam_channel(demod, channel, tuner_freq_offset);
if (rc != 0) {
@@ -10820,7 +10829,7 @@
SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
break;
#endif
- case DRX_STANDARD_UNKNOWN: /* fallthrough */
+ case DRX_STANDARD_UNKNOWN:
default:
return -EIO;
}
@@ -10888,8 +10897,8 @@
*/
switch (prev_standard) {
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
rc = power_down_qam(demod, false);
if (rc != 0) {
@@ -10908,7 +10917,7 @@
case DRX_STANDARD_UNKNOWN:
/* Do nothing */
break;
- case DRX_STANDARD_AUTO: /* fallthrough */
+ case DRX_STANDARD_AUTO:
default:
return -EINVAL;
}
@@ -10921,8 +10930,8 @@
switch (*standard) {
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
do {
u16 dummy;
@@ -11111,12 +11120,12 @@
goto rw_error;
}
break;
- case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
- case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
- case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
- case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */
- case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
- case DRX_STANDARD_NTSC: /* fallthrough */
+ case DRX_STANDARD_PAL_SECAM_BG:
+ case DRX_STANDARD_PAL_SECAM_DK:
+ case DRX_STANDARD_PAL_SECAM_I:
+ case DRX_STANDARD_PAL_SECAM_L:
+ case DRX_STANDARD_PAL_SECAM_LP:
+ case DRX_STANDARD_NTSC:
case DRX_STANDARD_FM:
rc = power_down_atv(demod, ext_attr->standard, true);
if (rc != 0) {
@@ -11127,7 +11136,7 @@
case DRX_STANDARD_UNKNOWN:
/* Do nothing */
break;
- case DRX_STANDARD_AUTO: /* fallthrough */
+ case DRX_STANDARD_AUTO:
default:
return -EIO;
}
@@ -11220,8 +11229,8 @@
ext_attr->vsb_pre_saw_cfg = *pre_saw;
break;
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_pre_saw_cfg = *pre_saw;
break;
@@ -11264,10 +11273,10 @@
ext_attr = (struct drxj_data *) demod->my_ext_attr;
switch (afe_gain->standard) {
- case DRX_STANDARD_8VSB: /* fallthrough */
+ case DRX_STANDARD_8VSB: fallthrough;
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
#endif
/* Do nothing */
@@ -11301,8 +11310,8 @@
ext_attr->vsb_pga_cfg = gain * 13 + 140;
break;
#ifndef DRXJ_VSB_ONLY
- case DRX_STANDARD_ITU_A: /* fallthrough */
- case DRX_STANDARD_ITU_B: /* fallthrough */
+ case DRX_STANDARD_ITU_A:
+ case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
ext_attr->qam_pga_cfg = gain * 13 + 140;
break;
@@ -12287,7 +12296,8 @@
if (state == NULL)
goto error;
- demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
+ demod = kmemdup(&drxj_default_demod_g,
+ sizeof(struct drx_demod_instance), GFP_KERNEL);
if (demod == NULL)
goto error;
@@ -12311,8 +12321,6 @@
state->demod = demod;
/* setup the demod data */
- memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
-
demod->my_i2c_dev_addr = demod_addr;
demod->my_common_attr = demod_comm_attr;
demod->my_i2c_dev_addr->user_data = state;
@@ -12367,7 +12375,7 @@
return NULL;
}
-EXPORT_SYMBOL(drx39xxj_attach);
+EXPORT_SYMBOL_GPL(drx39xxj_attach);
static const struct dvb_frontend_ops drx39xxj_ops = {
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
--
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