From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Thu, 19 Dec 2024 01:47:39 +0000 Subject: [PATCH] add wifi6 8852be driver --- kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h | 56 +++++++++++++++++++++++++++++++++++--------------------- 1 files changed, 35 insertions(+), 21 deletions(-) diff --git a/kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h b/kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h index 0b81183..08e1c14 100644 --- a/kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h +++ b/kernel/drivers/gpu/drm/meson/meson_dw_hdmi.h @@ -1,29 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2016 BayLibre, SAS * Author: Neil Armstrong <narmstrong@baylibre.com> * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. */ #ifndef __MESON_DW_HDMI_H #define __MESON_DW_HDMI_H /* - * Bit 7 RW Reserved. Default 1. - * Bit 6 RW Reserved. Default 1. - * Bit 5 RW Reserved. Default 1. + * Bit 15-10: RW Reserved. Default 1 starting from G12A + * Bit 9 RW sw_reset_i2c starting from G12A + * Bit 8 RW sw_reset_axiarb starting from G12A + * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A + * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A + * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. * Default 1. * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; @@ -39,12 +30,16 @@ #define HDMITX_TOP_SW_RESET (0x000) /* + * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. - * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. + * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable + * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable + * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable + * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. @@ -53,6 +48,8 @@ #define HDMITX_TOP_CLK_CNTL (0x001) /* + * Bit 31:28 RW rxsense_glitch_width: starting from G12A + * Bit 27:16 RW rxsense_valid_width: starting from G12A * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */ @@ -61,6 +58,9 @@ /* * intr_maskn: MASK_N, one bit per interrupt source. * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. + * [ 7] rxsense_fall starting from G12A + * [ 6] rxsense_rise starting from G12A + * [ 5] err_i2c_timeout starting from G12A * [ 4] hdcp22_rndnum_err * [ 3] nonce_rfrsh_rise * [ 2] hpd_fall_intr @@ -73,6 +73,9 @@ * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt * bit, read back the interrupt status. * Bit 31 R IP interrupt status + * Bit 7 RW rxsense_fall starting from G12A + * Bit 6 RW rxsense_rise starting from G12A + * Bit 5 RW err_i2c_timeout starting from G12A * Bit 2 RW hpd_fall * Bit 1 RW hpd_rise * Bit 0 RW IP interrupt @@ -80,6 +83,9 @@ #define HDMITX_TOP_INTR_STAT (0x004) /* + * [7] rxsense_fall starting from G12A + * [6] rxsense_rise starting from G12A + * [5] err_i2c_timeout starting from G12A * [4] hdcp22_rndnum_err * [3] nonce_rfrsh_rise * [2] hpd_fall @@ -91,8 +97,11 @@ #define HDMITX_TOP_INTR_CORE BIT(0) #define HDMITX_TOP_INTR_HPD_RISE BIT(1) #define HDMITX_TOP_INTR_HPD_FALL BIT(2) +#define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6) +#define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) -/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; +/* + * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. @@ -127,7 +136,8 @@ /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) -/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, +/* + * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, * used when TMDS CLK rate = TMDS character rate /4. Default 0. * Bit 0 R Reserved. Default 0. * [ 1] shift_tmds_clk_pttn @@ -135,12 +145,16 @@ */ #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) -/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM +/* + * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM * failure, write 1 to clear the failure flag. Default 0. */ #define HDMITX_TOP_REVOCMEM_STAT (0x00D) -/* Bit 0 R filtered HPD status. */ +/* + * Bit 1 R filtered RxSense status + * Bit 0 R filtered HPD status. + */ #define HDMITX_TOP_STAT0 (0x00E) #endif /* __MESON_DW_HDMI_H */ -- Gitblit v1.6.2