From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/clk/rockchip/clk-rv1108.c | 122 +++++++++++++++++++++-------------------
1 files changed, 63 insertions(+), 59 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-rv1108.c b/kernel/drivers/clk/rockchip/clk-rv1108.c
index 59de094..0a93b93 100644
--- a/kernel/drivers/clk/rockchip/clk-rv1108.c
+++ b/kernel/drivers/clk/rockchip/clk-rv1108.c
@@ -1,29 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Shawn Lin <shawn.lin@rock-chips.com>
* Andy Yan <andy.yan@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include "clk.h"
#define RV1108_GRF_SOC_STATUS0 0x480
-#define RV1108_I2S_FRAC_MAX_RATE 600000000
-#define RV1108_UART_FRAC_MAX_RATE 600000000
enum rv1108_plls {
apll, dpll, gpll,
@@ -128,12 +120,10 @@
PNAME(mux_pll_p) = { "xin24m", "xin24m"};
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
-PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
-PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
@@ -221,7 +211,7 @@
COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1108_CLKGATE_CON(0), 4, GFLAGS),
- GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
+ GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(11), 0, GFLAGS),
GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(11), 1, GFLAGS),
@@ -276,10 +266,10 @@
RV1108_CLKGATE_CON(19), 6, GFLAGS),
/* PD_PMU_wrapper */
- COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 12, GFLAGS),
- GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(10), 0, GFLAGS),
GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 1, GFLAGS),
@@ -317,7 +307,7 @@
RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 12, GFLAGS),
- GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(14), 6, GFLAGS),
GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 14, GFLAGS),
@@ -515,7 +505,7 @@
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(8), 0,
RV1108_CLKGATE_CON(2), 1, GFLAGS,
- &rv1108_i2s0_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ &rv1108_i2s0_fracmux),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
@@ -528,7 +518,7 @@
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 5, GFLAGS,
- &rv1108_i2s1_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ &rv1108_i2s1_fracmux),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 6, GFLAGS),
@@ -538,28 +528,28 @@
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(10), 0,
RV1108_CLKGATE_CON(2), 9, GFLAGS,
- &rv1108_i2s2_fracmux, RV1108_I2S_FRAC_MAX_RATE),
+ &rv1108_i2s2_fracmux),
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 10, GFLAGS),
/* PD_BUS */
- GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(1), 0, GFLAGS),
- GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_bus_src_apll", "apll", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(1), 1, GFLAGS),
- GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(1), 2, GFLAGS),
- COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
+ COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
- COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
+ COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(1), 4, GFLAGS),
- COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
+ COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(1), 5, GFLAGS),
- GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
+ GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(1), 6, GFLAGS),
- GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(1), 7, GFLAGS),
GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 8, GFLAGS),
@@ -604,15 +594,15 @@
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(16), 0,
RV1108_CLKGATE_CON(3), 2, GFLAGS,
- &rv1108_uart0_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ &rv1108_uart0_fracmux),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(17), 0,
RV1108_CLKGATE_CON(3), 4, GFLAGS,
- &rv1108_uart1_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ &rv1108_uart1_fracmux),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(18), 0,
RV1108_CLKGATE_CON(3), 6, GFLAGS,
- &rv1108_uart2_fracmux, RV1108_UART_FRAC_MAX_RATE),
+ &rv1108_uart2_fracmux),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 10, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
@@ -680,7 +670,7 @@
RV1108_CLKGATE_CON(0), 9, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 10, GFLAGS),
- COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+ COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
@@ -688,9 +678,9 @@
RV1108_CLKGATE_CON(10), 9, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 4, GFLAGS),
- GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
+ GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(12), 5, GFLAGS),
- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(12), 6, GFLAGS),
GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 11, GFLAGS),
@@ -704,22 +694,22 @@
*/
/* PD_PERI */
- COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
+ COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
RV1108_CLKGATE_CON(4), 5, GFLAGS),
- GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
+ GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(15), 13, GFLAGS),
- COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
+ COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
RV1108_CLKGATE_CON(4), 4, GFLAGS),
- GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
+ GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(15), 12, GFLAGS),
- GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(4), 1, GFLAGS),
- GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IS_CRITICAL,
RV1108_CLKGATE_CON(4), 2, GFLAGS),
- COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
+ COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, CLK_IS_CRITICAL,
RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(15), 11, GFLAGS),
@@ -779,20 +769,6 @@
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1),
};
-static const char *const rv1108_critical_clocks[] __initconst = {
- "aclk_core",
- "aclk_bus",
- "hclk_bus",
- "pclk_bus",
- "aclk_periph",
- "hclk_periph",
- "pclk_periph",
- "nclk_ddrupctl",
- "pclk_ddrmon",
- "pclk_acodecphy",
- "pclk_pmu",
-};
-
static void __iomem *rv1108_cru_base;
static void rv1108_dump_cru(void)
@@ -809,6 +785,7 @@
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
+ struct clk **clks;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -822,17 +799,16 @@
iounmap(reg_base);
return;
}
+ clks = ctx->clk_data.clks;
rockchip_clk_register_plls(ctx, rv1108_pll_clks,
ARRAY_SIZE(rv1108_pll_clks),
RV1108_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rv1108_clk_branches,
ARRAY_SIZE(rv1108_clk_branches));
- rockchip_clk_protect_critical(rv1108_critical_clocks,
- ARRAY_SIZE(rv1108_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
- mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ 3, clks[PLL_APLL], clks[PLL_GPLL],
&rv1108_cpuclk_data, rv1108_cpuclk_rates,
ARRAY_SIZE(rv1108_cpuclk_rates));
@@ -849,3 +825,31 @@
}
}
CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
+
+static int __init clk_rv1108_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ rv1108_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rv1108_match_table[] = {
+ {
+ .compatible = "rockchip,rv1108-cru",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rv1108_match_table);
+
+static struct platform_driver clk_rv1108_driver = {
+ .driver = {
+ .name = "clk-rv1108",
+ .of_match_table = clk_rv1108_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rv1108_driver, clk_rv1108_probe);
+
+MODULE_DESCRIPTION("Rockchip RV1108 Clock Driver");
+MODULE_LICENSE("GPL");
--
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