From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/clk/rockchip/clk-rk3528.c | 65 ++++++++++++++++----------------
1 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-rk3528.c b/kernel/drivers/clk/rockchip/clk-rk3528.c
index 3e1143b..1b14cd5 100644
--- a/kernel/drivers/clk/rockchip/clk-rk3528.c
+++ b/kernel/drivers/clk/rockchip/clk-rk3528.c
@@ -136,7 +136,6 @@
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
-PNAME(mux_apll_gpll_p) = { "apll", "gpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
@@ -197,8 +196,6 @@
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
-
-#define RK3528_FRAC_MAX_PRATE 1188000000
static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
@@ -304,7 +301,7 @@
RK3528_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(5), 0,
- RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux),
GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
RK3528_CLKGATE_CON(0), 14, GFLAGS),
@@ -313,7 +310,7 @@
RK3528_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(7), 0,
- RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux),
GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
RK3528_CLKGATE_CON(1), 1, GFLAGS),
@@ -322,7 +319,7 @@
RK3528_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(9), 0,
- RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux),
GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
RK3528_CLKGATE_CON(1), 4, GFLAGS),
@@ -331,7 +328,7 @@
RK3528_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(11), 0,
- RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux),
GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
RK3528_CLKGATE_CON(1), 7, GFLAGS),
@@ -340,7 +337,7 @@
RK3528_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(13), 0,
- RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux),
GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
RK3528_CLKGATE_CON(1), 10, GFLAGS),
@@ -349,7 +346,7 @@
RK3528_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(15), 0,
- RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux),
GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
RK3528_CLKGATE_CON(1), 13, GFLAGS),
@@ -358,7 +355,7 @@
RK3528_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(17), 0,
- RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux),
GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
RK3528_CLKGATE_CON(2), 0, GFLAGS),
@@ -367,7 +364,7 @@
RK3528_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(19), 0,
- RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux),
GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
RK3528_CLKGATE_CON(2), 3, GFLAGS),
@@ -376,7 +373,7 @@
RK3528_CLKGATE_CON(2), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(21), 0,
- RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux),
GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
RK3528_CLKGATE_CON(2), 7, GFLAGS),
@@ -385,7 +382,7 @@
RK3528_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(25), 0,
- RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux),
GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
RK3528_CLKGATE_CON(2), 13, GFLAGS),
@@ -394,7 +391,7 @@
RK3528_CLKGATE_CON(2), 14, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(27), 0,
- RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux),
GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
RK3528_CLKGATE_CON(3), 0, GFLAGS),
@@ -403,7 +400,7 @@
RK3528_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(23), 0,
- RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux),
GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
RK3528_CLKGATE_CON(2), 10, GFLAGS),
@@ -412,7 +409,7 @@
RK3528_CLKGATE_CON(3), 4, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
RK3528_CLKSEL_CON(31), 0,
- RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux, RK3528_FRAC_MAX_PRATE),
+ RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux),
GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
RK3528_CLKGATE_CON(3), 6, GFLAGS),
@@ -550,7 +547,7 @@
COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
RK3528_PMU_CLKSEL_CON(1), 0,
- RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS, 0),
+ RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
/* clk_32k: internal! No path from external osc 32k */
MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
@@ -803,12 +800,12 @@
COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
RK3528_CLKGATE_CON(39), 0, GFLAGS),
- GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
- RK3528_CLKGATE_CON(39), 8, GFLAGS | CLK_GATE_NO_SET_RATE),
- GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
- RK3528_CLKGATE_CON(39), 11, GFLAGS | CLK_GATE_NO_SET_RATE),
- GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
- RK3528_CLKGATE_CON(41), 0, GFLAGS | CLK_GATE_NO_SET_RATE),
+ GATE_NO_SET_RATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 8, GFLAGS),
+ GATE_NO_SET_RATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 11, GFLAGS),
+ GATE_NO_SET_RATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 0, GFLAGS),
COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
@@ -938,15 +935,15 @@
COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
RK3528_CLKGATE_CON(25), 0, GFLAGS),
- GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
- RK3528_CLKGATE_CON(26), 1, GFLAGS | CLK_GATE_NO_SET_RATE),
- GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
- RK3528_CLKGATE_CON(28), 5, GFLAGS | CLK_GATE_NO_SET_RATE),
- GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
- RK3528_CLKGATE_CON(30), 3, GFLAGS | CLK_GATE_NO_SET_RATE),
+ GATE_NO_SET_RATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(26), 1, GFLAGS),
+ GATE_NO_SET_RATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(28), 5, GFLAGS),
+ GATE_NO_SET_RATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(30), 3, GFLAGS),
- GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
- RK3528_CLKGATE_CON(33), 1, GFLAGS | CLK_GATE_NO_SET_RATE),
+ GATE_NO_SET_RATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(33), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
@@ -996,7 +993,7 @@
RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
RK3528_CLKGATE_CON(25), 3, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
- RK3528_CLKGATE_CON(25), 9, GFLAGS | CLK_GATE_NO_SET_RATE),
+ RK3528_CLKGATE_CON(25), 9, GFLAGS),
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
@@ -1108,6 +1105,7 @@
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
+ struct clk **clks;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -1123,13 +1121,14 @@
iounmap(reg_base);
return;
}
+ clks = ctx->clk_data.clks;
rockchip_clk_register_plls(ctx, rk3528_pll_clks,
ARRAY_SIZE(rk3528_pll_clks),
RK3528_GRF_SOC_STATUS0);
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
- mux_apll_gpll_p, ARRAY_SIZE(mux_apll_gpll_p),
+ 2, clks[PLL_APLL], clks[PLL_GPLL],
&rk3528_cpuclk_data, rk3528_cpuclk_rates,
ARRAY_SIZE(rk3528_cpuclk_rates));
rockchip_clk_register_branches(ctx, rk3528_clk_branches,
--
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