From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/clk/rockchip/clk-rk3368.c | 191 +++++++++++++++++++++--------------------------
1 files changed, 87 insertions(+), 104 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-rk3368.c b/kernel/drivers/clk/rockchip/clk-rk3368.c
index 009abde..c56ea32 100644
--- a/kernel/drivers/clk/rockchip/clk-rk3368.c
+++ b/kernel/drivers/clk/rockchip/clk-rk3368.c
@@ -1,29 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include "clk.h"
#define RK3368_GRF_SOC_STATUS0 0x480
-#define RK3368_I2S_FRAC_MAX_PRATE 600000000
-#define RK3368_UART_FRAC_MAX_PRATE 600000000
-#define RK3368_SPDIF_FRAC_MAX_PRATE 600000000
-#define RK3368_DCLK_PARENT_MAX_PRATE 600000000
enum rk3368_plls {
apllb, aplll, dpll, cpll, gpll, npll,
@@ -71,7 +61,6 @@
RK3066_PLL_RATE(1248000000, 1, 52, 1),
RK3066_PLL_RATE(1224000000, 1, 51, 1),
RK3066_PLL_RATE(1200000000, 1, 50, 1),
- RK3066_PLL_RATE(1188000000, 2, 99, 1),
RK3066_PLL_RATE(1176000000, 1, 49, 1),
RK3066_PLL_RATE(1128000000, 1, 47, 1),
RK3066_PLL_RATE(1104000000, 1, 46, 1),
@@ -119,8 +108,6 @@
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
-PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
-PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
@@ -143,7 +130,7 @@
PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
"dummy", "xin12m" };
-PNAME(mux_spdif_8ch_p) = { "spdif_8ch_src", "spdif_8ch_frac",
+PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
"ext_i2s", "xin12m" };
PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
@@ -166,7 +153,7 @@
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
RK3368_PLL_CON(11), 8, 2, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
- RK3368_PLL_CON(15), 8, 3, 0, rk3368_pll_rates),
+ RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
@@ -253,7 +240,6 @@
RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
- RK3368_CPUCLKL_RATE(1296000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
@@ -261,15 +247,12 @@
RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
- RK3368_CPUCLKB_RATE( 216000000, 1, 1, 1),
- RK3368_CPUCLKB_RATE( 126000000, 1, 1, 1),
};
static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
- RK3368_CPUCLKL_RATE(1296000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
@@ -277,8 +260,6 @@
RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
- RK3368_CPUCLKL_RATE( 216000000, 1, 1, 1),
- RK3368_CPUCLKL_RATE( 126000000, 1, 1, 1),
};
static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
@@ -364,9 +345,6 @@
RK3368_CLKGATE_CON(1), 8, GFLAGS),
GATE(0, "gpll_ddr", "gpll", 0,
RK3368_CLKGATE_CON(1), 9, GFLAGS),
- COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
- RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
-
COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
@@ -375,22 +353,22 @@
GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(6), 15, GFLAGS),
- GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "gpll_aclk_bus", "gpll", CLK_IS_CRITICAL,
RK3368_CLKGATE_CON(1), 10, GFLAGS),
- GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
+ GATE(0, "cpll_aclk_bus", "cpll", CLK_IS_CRITICAL,
RK3368_CLKGATE_CON(1), 11, GFLAGS),
- COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
+ COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
- GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
+ GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
RK3368_CLKGATE_CON(1), 0, GFLAGS),
- COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
RK3368_CLKGATE_CON(1), 2, GFLAGS),
- COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
RK3368_CLKGATE_CON(1), 1, GFLAGS),
- COMPOSITE_NOMUX(SCLK_CRYPTO, "sclk_crypto", "aclk_bus_src", 0,
+ COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
RK3368_CLKGATE_CON(7), 2, GFLAGS),
@@ -411,7 +389,7 @@
COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
- &rk3368_i2s_8ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
+ &rk3368_i2s_8ch_fracmux),
COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(6), 0, GFLAGS),
@@ -423,7 +401,7 @@
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(32), 0,
RK3368_CLKGATE_CON(6), 5, GFLAGS,
- &rk3368_spdif_8ch_fracmux, RK3368_SPDIF_FRAC_MAX_PRATE),
+ &rk3368_spdif_8ch_fracmux),
GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
@@ -432,14 +410,14 @@
COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(54), 0,
RK3368_CLKGATE_CON(5), 14, GFLAGS,
- &rk3368_i2s_2ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
+ &rk3368_i2s_2ch_fracmux),
GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(5), 15, GFLAGS),
- COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(6), 12, GFLAGS),
- GATE(SCLK_HSADC_TSP, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
+ GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
RK3368_CLKGATE_CON(13), 7, GFLAGS),
MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
@@ -481,16 +459,16 @@
DIV(0, "hclk_vio", "aclk_vio0", 0,
RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
- COMPOSITE(ACLK_RGA, "aclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
+ COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 3, GFLAGS),
COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 4, GFLAGS),
- COMPOSITE_DCLK(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
+ COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
- RK3368_CLKGATE_CON(4), 1, GFLAGS, RK3368_DCLK_PARENT_MAX_PRATE),
+ RK3368_CLKGATE_CON(4), 1, GFLAGS),
GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
RK3368_CLKGATE_CON(4), 2, GFLAGS),
@@ -514,10 +492,10 @@
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3368_CLKGATE_CON(4), 12, GFLAGS),
- COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
+ COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(4), 5, GFLAGS),
- COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
+ COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
@@ -531,12 +509,12 @@
RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3368_CLKGATE_CON(5), 5, GFLAGS),
- DIV(0, "pclk_pd_alive", "gpll", 0,
+ DIV(0, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
/* sclk_timer has a gate in the sgrf */
- COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
RK3368_CLKGATE_CON(7), 9, GFLAGS),
GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
@@ -555,19 +533,19 @@
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
RK3368_CLKGATE_CON(7), 11, GFLAGS),
- COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(3), 0, GFLAGS),
- COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
+ COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3368_CLKGATE_CON(3), 3, GFLAGS),
- COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3368_CLKGATE_CON(3), 2, GFLAGS),
- GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
RK3368_CLKGATE_CON(3), 1, GFLAGS),
- GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
+ GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
/*
* Clock-Architecture Diagram 4
@@ -603,7 +581,7 @@
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
- GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
+ GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(8), 1, GFLAGS),
/* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
@@ -633,7 +611,7 @@
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(34), 0,
RK3368_CLKGATE_CON(2), 1, GFLAGS,
- &rk3368_uart0_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ &rk3368_uart0_fracmux),
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
@@ -641,7 +619,7 @@
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(36), 0,
RK3368_CLKGATE_CON(2), 3, GFLAGS,
- &rk3368_uart1_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ &rk3368_uart1_fracmux),
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
@@ -649,7 +627,7 @@
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(40), 0,
RK3368_CLKGATE_CON(2), 7, GFLAGS,
- &rk3368_uart3_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ &rk3368_uart3_fracmux),
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
@@ -657,7 +635,7 @@
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(42), 0,
RK3368_CLKGATE_CON(2), 9, GFLAGS,
- &rk3368_uart4_fracmux, RK3368_UART_FRAC_MAX_PRATE),
+ &rk3368_uart4_fracmux),
COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -711,7 +689,7 @@
/* aclk_bus gates */
GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
- GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
+ GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 11, GFLAGS),
GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
@@ -737,17 +715,17 @@
GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
/* pclk_cpu gates */
- GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
- GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 14, GFLAGS),
+ GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 13, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
- GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
- GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
+ GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*
* video clk gates
@@ -759,9 +737,10 @@
GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
- /* aclk_rga gates */
- GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
- GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
+ /* aclk_rga_pre gates */
+ GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
+ GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
/* aclk_vio0 gates */
GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
@@ -772,7 +751,7 @@
/* sclk_isp gates */
GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
- FACTOR(ACLK_ISP, "aclk_isp", "sclk_isp", CLK_SET_RATE_PARENT, 1, 1),
+ GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
/* hclk_vio gates */
GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
@@ -816,12 +795,12 @@
GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
- GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
- GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
- GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 1, GFLAGS),
+ GATE(0, "pmu_hclk_otg0", "hclk_peri", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(20), 2, GFLAGS),
+ GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
@@ -847,18 +826,21 @@
/* pclk_pd_alive gates */
GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
- GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
- GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
+ GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 9, GFLAGS),
+ GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 8, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
+
+ /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
+ SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
/*
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
- GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", 0, RK3368_CLKGATE_CON(22), 11, GFLAGS),
- GATE(PCLK_DPHYTX0, "pclk_dphytx", "hclk_vio", 0, RK3368_CLKGATE_CON(22), 10, GFLAGS),
+ GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
/* pclk_pd_pmu gates */
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
@@ -883,24 +865,6 @@
GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
};
-static const char *const rk3368_critical_clocks[] __initconst = {
- "aclk_bus",
- "aclk_peri",
- /*
- * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
- * but needs to stay enabled there (including its parents) at all times.
- */
- "pclk_pwm1",
- "pclk_pd_pmu",
- "pclk_pd_alive",
- "pclk_peri",
- "hclk_peri",
- "pclk_ddrphy",
- "pclk_ddrupctl",
- "pmu_hclk_otg0",
- "aclk_dmac_bus",
-};
-
static void __iomem *rk3368_cru_base;
static void rk3368_dump_cru(void)
@@ -917,7 +881,7 @@
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
- struct clk *clk;
+ struct clk **clks;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -931,30 +895,21 @@
iounmap(reg_base);
return;
}
-
- /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
- clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
- if (IS_ERR(clk))
- pr_warn("%s: could not register clock pclk_wdt: %ld\n",
- __func__, PTR_ERR(clk));
- else
- rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
+ clks = ctx->clk_data.clks;
rockchip_clk_register_plls(ctx, rk3368_pll_clks,
ARRAY_SIZE(rk3368_pll_clks),
RK3368_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3368_clk_branches,
ARRAY_SIZE(rk3368_clk_branches));
- rockchip_clk_protect_critical(rk3368_critical_clocks,
- ARRAY_SIZE(rk3368_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
- mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
+ 2, clks[PLL_APLLB], clks[PLL_GPLL],
&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
ARRAY_SIZE(rk3368_cpuclkb_rates));
rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
- mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
+ 2, clks[PLL_APLLL], clks[PLL_GPLL],
&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
ARRAY_SIZE(rk3368_cpuclkl_rates));
@@ -971,3 +926,31 @@
}
}
CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
+
+static int __init clk_rk3368_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ rk3368_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk3368_match_table[] = {
+ {
+ .compatible = "rockchip,rk3368-cru",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3368_match_table);
+
+static struct platform_driver clk_rk3368_driver = {
+ .driver = {
+ .name = "clk-rk3368",
+ .of_match_table = clk_rk3368_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3368_driver, clk_rk3368_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3368 Clock Driver");
+MODULE_LICENSE("GPL");
--
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