From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/clk/rockchip/clk-rk3308.c | 209 ++++++++++++++++++++++-----------------------------
1 files changed, 91 insertions(+), 118 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-rk3308.c b/kernel/drivers/clk/rockchip/clk-rk3308.c
index d36dfcf..6a8e38f 100644
--- a/kernel/drivers/clk/rockchip/clk-rk3308.c
+++ b/kernel/drivers/clk/rockchip/clk-rk3308.c
@@ -1,33 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
+#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/rockchip/cpu.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3308-cru.h>
#include "clk.h"
#define RK3308_GRF_SOC_STATUS0 0x380
-#define RK3308_VOP_FRAC_MAX_PRATE 270000000
-#define RK3308B_VOP_FRAC_MAX_PRATE 800000000
-#define RK3308_UART_FRAC_MAX_PRATE 800000000
-#define RK3308_PDM_FRAC_MAX_PRATE 800000000
-#define RK3308_SPDIF_FRAC_MAX_PRATE 800000000
-#define RK3308_I2S_FRAC_MAX_PRATE 800000000
enum rk3308_plls {
apll, dpll, vpll0, vpll1,
@@ -136,7 +124,6 @@
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
-PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
@@ -149,7 +136,6 @@
PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
-PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
@@ -191,8 +177,8 @@
PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
-PNAME(mux_uart_src_p) = { "xin24m", "usb480m", "dpll", "vpll0", "vpll1" };
-static u32 uart_src_mux_idx[] = { 4, 3, 0, 1, 2 };
+PNAME(mux_uart_src_p) = { "usb480m", "xin24m", "dpll", "vpll0", "vpll1" };
+static u32 uart_src_mux_idx[] = { 3, 4, 0, 1, 2 };
static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@@ -330,18 +316,18 @@
* Clock-Architecture Diagram 3
*/
- COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
+ COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(1), 0, GFLAGS),
- COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 3, GFLAGS),
GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 15, GFLAGS),
- COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 2, GFLAGS),
- COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 1, GFLAGS),
@@ -349,9 +335,9 @@
RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
- RK3308_CLKSEL_CON(12), 0,
+ RK3308_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3308_CLKGATE_CON(1), 11, GFLAGS,
- &rk3308_uart0_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ &rk3308_uart0_fracmux),
GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
RK3308_CLKGATE_CON(1), 12, GFLAGS),
@@ -359,9 +345,9 @@
RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
- RK3308_CLKSEL_CON(15), 0,
+ RK3308_CLKSEL_CON(15), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3308_CLKGATE_CON(1), 15, GFLAGS,
- &rk3308_uart1_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ &rk3308_uart1_fracmux),
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
RK3308_CLKGATE_CON(2), 0, GFLAGS),
@@ -369,9 +355,9 @@
RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
- RK3308_CLKSEL_CON(18), 0,
+ RK3308_CLKSEL_CON(18), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3308_CLKGATE_CON(2), 3, GFLAGS,
- &rk3308_uart2_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ &rk3308_uart2_fracmux),
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
RK3308_CLKGATE_CON(2), 4, GFLAGS),
@@ -379,9 +365,9 @@
RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
- RK3308_CLKSEL_CON(21), 0,
+ RK3308_CLKSEL_CON(21), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3308_CLKGATE_CON(2), 7, GFLAGS,
- &rk3308_uart3_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ &rk3308_uart3_fracmux),
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
RK3308_CLKGATE_CON(2), 8, GFLAGS),
@@ -389,9 +375,9 @@
RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
- RK3308_CLKSEL_CON(24), 0,
+ RK3308_CLKSEL_CON(24), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3308_CLKGATE_CON(2), 11, GFLAGS,
- &rk3308_uart4_fracmux, RK3308_UART_FRAC_MAX_PRATE),
+ &rk3308_uart4_fracmux),
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
RK3308_CLKGATE_CON(2), 12, GFLAGS),
@@ -468,6 +454,10 @@
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(1), 6, GFLAGS),
+ COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
+ RK3308_CLKSEL_CON(9), 0,
+ RK3308_CLKGATE_CON(1), 7, GFLAGS,
+ &rk3308_dclk_vop_fracmux),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),
@@ -475,16 +465,16 @@
* Clock-Architecture Diagram 4
*/
- COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
+ COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(8), 0, GFLAGS),
- COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 1, GFLAGS),
- COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 2, GFLAGS),
- COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
+ COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 3, GFLAGS),
@@ -575,12 +565,10 @@
GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 13, GFLAGS),
- COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_vpll0_vpll1_p, 0,
- RK3308_CLKSEL_CON(1), 6, 2, 0, 0, ROCKCHIP_DDRCLK_SIP_V2),
- COMPOSITE(0, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
+ COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
RK3308_CLKGATE_CON(0), 10, GFLAGS),
- GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
+ GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IS_CRITICAL,
RK3308_CLKGATE_CON(0), 11, GFLAGS),
FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
RK3308_CLKGATE_CON(0), 13, GFLAGS),
@@ -600,7 +588,7 @@
COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(3), 0,
RK3308_CLKGATE_CON(4), 3, GFLAGS,
- &rk3308_rtc32k_fracmux, 0),
+ &rk3308_rtc32k_fracmux),
MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
@@ -634,13 +622,13 @@
* Clock-Architecture Diagram 7
*/
- COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
+ COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(10), 0, GFLAGS),
- COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
+ COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(10), 1, GFLAGS),
- COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
+ COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", CLK_IS_CRITICAL,
RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(10), 2, GFLAGS),
@@ -650,7 +638,7 @@
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(47), 0,
RK3308_CLKGATE_CON(10), 4, GFLAGS,
- &rk3308_pdm_fracmux, RK3308_PDM_FRAC_MAX_PRATE),
+ &rk3308_pdm_fracmux),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
RK3308_CLKGATE_CON(10), 5, GFLAGS),
@@ -660,7 +648,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(53), 0,
RK3308_CLKGATE_CON(10), 13, GFLAGS,
- &rk3308_i2s0_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s0_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(10), 14, GFLAGS),
@@ -674,7 +662,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(55), 0,
RK3308_CLKGATE_CON(11), 1, GFLAGS,
- &rk3308_i2s0_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s0_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 2, GFLAGS),
@@ -687,7 +675,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(57), 0,
RK3308_CLKGATE_CON(11), 5, GFLAGS,
- &rk3308_i2s1_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s1_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 6, GFLAGS),
@@ -701,7 +689,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(59), 0,
RK3308_CLKGATE_CON(11), 9, GFLAGS,
- &rk3308_i2s1_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s1_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 10, GFLAGS),
@@ -714,7 +702,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(61), 0,
RK3308_CLKGATE_CON(11), 13, GFLAGS,
- &rk3308_i2s2_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s2_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 14, GFLAGS),
@@ -728,7 +716,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(63), 0,
RK3308_CLKGATE_CON(12), 1, GFLAGS,
- &rk3308_i2s2_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s2_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 2, GFLAGS),
@@ -741,7 +729,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(65), 0,
RK3308_CLKGATE_CON(12), 5, GFLAGS,
- &rk3308_i2s3_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s3_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 6, GFLAGS),
@@ -755,7 +743,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(67), 0,
RK3308_CLKGATE_CON(12), 9, GFLAGS,
- &rk3308_i2s3_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s3_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 10, GFLAGS),
@@ -768,7 +756,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(69), 0,
RK3308_CLKGATE_CON(12), 13, GFLAGS,
- &rk3308_i2s0_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s0_2ch_fracmux),
GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
RK3308_CLKGATE_CON(12), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
@@ -781,7 +769,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(71), 0,
RK3308_CLKGATE_CON(13), 1, GFLAGS,
- &rk3308_i2s1_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
+ &rk3308_i2s1_2ch_fracmux),
GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
RK3308_CLKGATE_CON(13), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
@@ -799,7 +787,7 @@
COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(49), 0,
RK3308_CLKGATE_CON(10), 7, GFLAGS,
- &rk3308_spdif_tx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
+ &rk3308_spdif_tx_fracmux),
GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
RK3308_CLKGATE_CON(10), 8, GFLAGS),
@@ -814,7 +802,7 @@
COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(51), 0,
RK3308_CLKGATE_CON(10), 10, GFLAGS,
- &rk3308_spdif_rx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
+ &rk3308_spdif_rx_fracmux),
GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
RK3308_CLKGATE_CON(10), 11, GFLAGS),
@@ -865,6 +853,12 @@
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
+ /* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
+ /* aclk_dmac1 is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
+ /* watchdog pclk is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
@@ -915,26 +909,14 @@
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
- &rk3308_dclk_vop_fracmux, RK3308_VOP_FRAC_MAX_PRATE),
+ &rk3308_dclk_vop_fracmux),
};
static struct rockchip_clk_branch rk3308b_dclk_vop_frac[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
- &rk3308_dclk_vop_fracmux, RK3308B_VOP_FRAC_MAX_PRATE),
-};
-
-static const char *const rk3308_critical_clocks[] __initconst = {
- "aclk_bus",
- "hclk_bus",
- "pclk_bus",
- "aclk_peri",
- "hclk_peri",
- "pclk_peri",
- "hclk_audio",
- "pclk_audio",
- "sclk_ddrc",
+ &rk3308_dclk_vop_fracmux),
};
static void __iomem *rk3308_cru_base;
@@ -948,24 +930,12 @@
0x500, false);
}
}
-EXPORT_SYMBOL_GPL(rk3308_dump_cru);
-
-static int rk3308_clk_panic(struct notifier_block *this,
- unsigned long ev, void *ptr)
-{
- rk3308_dump_cru();
- return NOTIFY_DONE;
-}
-
-static struct notifier_block rk3308_clk_panic_block = {
- .notifier_call = rk3308_clk_panic,
-};
static void __init rk3308_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
- struct clk *clk;
+ struct clk **clks;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -973,38 +943,13 @@
return;
}
- rk3308_cru_base = reg_base;
-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
-
- /* aclk_dmac0 is controlled by sgrf. */
- clk = clk_register_fixed_factor(NULL, "aclk_dmac0", "aclk_bus", 0, 1, 1);
- if (IS_ERR(clk))
- pr_warn("%s: could not register clock aclk_dmac0: %ld\n",
- __func__, PTR_ERR(clk));
- else
- rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC0);
-
- /* aclk_dmac1 is controlled by sgrf. */
- clk = clk_register_fixed_factor(NULL, "aclk_dmac1", "aclk_bus", 0, 1, 1);
- if (IS_ERR(clk))
- pr_warn("%s: could not register clock aclk_dmac1: %ld\n",
- __func__, PTR_ERR(clk));
- else
- rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC1);
-
- /* watchdog pclk is controlled by sgrf. */
- clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_bus", 0, 1, 1);
- if (IS_ERR(clk))
- pr_warn("%s: could not register clock pclk_wdt: %ld\n",
- __func__, PTR_ERR(clk));
- else
- rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
+ clks = ctx->clk_data.clks;
rockchip_clk_register_plls(ctx, rk3308_pll_clks,
ARRAY_SIZE(rk3308_pll_clks),
@@ -1018,11 +963,9 @@
else
rockchip_clk_register_branches(ctx, rk3308_dclk_vop_frac,
ARRAY_SIZE(rk3308_dclk_vop_frac));
- rockchip_clk_protect_critical(rk3308_critical_clocks,
- ARRAY_SIZE(rk3308_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
- mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ 3, clks[PLL_APLL], clks[PLL_VPLL0],
&rk3308_cpuclk_data, rk3308_cpuclk_rates,
ARRAY_SIZE(rk3308_cpuclk_rates));
@@ -1033,8 +976,38 @@
rockchip_clk_of_add_provider(np, ctx);
- atomic_notifier_chain_register(&panic_notifier_list,
- &rk3308_clk_panic_block);
+ if (!rk_dump_cru) {
+ rk3308_cru_base = reg_base;
+ rk_dump_cru = rk3308_dump_cru;
+ }
}
CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
+
+static int __init clk_rk3308_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ rk3308_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk3308_match_table[] = {
+ {
+ .compatible = "rockchip,rk3308-cru",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3308_match_table);
+
+static struct platform_driver clk_rk3308_driver = {
+ .driver = {
+ .name = "clk-rk3308",
+ .of_match_table = clk_rk3308_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3308_driver, clk_rk3308_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3308 Clock Driver");
+MODULE_LICENSE("GPL");
--
Gitblit v1.6.2