From 9370bb92b2d16684ee45cf24e879c93c509162da Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 19 Dec 2024 01:47:39 +0000
Subject: [PATCH] add wifi6 8852be driver
---
kernel/drivers/clk/rockchip/clk-ddr.c | 226 +++++++++++---------------------------------------------
1 files changed, 45 insertions(+), 181 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-ddr.c b/kernel/drivers/clk/rockchip/clk-ddr.c
index 33d22e3..46df75f 100644
--- a/kernel/drivers/clk/rockchip/clk-ddr.c
+++ b/kernel/drivers/clk/rockchip/clk-ddr.c
@@ -1,19 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Lin Huang <hl@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
-#include <drm/drmP.h>
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
@@ -21,17 +11,12 @@
#include <linux/of.h>
#include <linux/rockchip/rockchip_sip.h>
#include <linux/slab.h>
-#include <soc/rockchip/rockchip_dmc.h>
#include <soc/rockchip/rockchip_sip.h>
-#include <soc/rockchip/scpi.h>
-#include <uapi/drm/drm_mode.h>
#ifdef CONFIG_ARM
#include <asm/psci.h>
#endif
#include "clk.h"
-
-#define MHZ (1000000)
struct rockchip_ddrclk {
struct clk_hw hw;
@@ -46,52 +31,29 @@
#define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
-static int rk_drm_get_lcdc_type(void)
+struct share_params_ddrclk {
+ u32 hz;
+ u32 lcdc_type;
+};
+
+struct rockchip_ddrclk_data {
+ void __iomem *params;
+ int (*dmcfreq_wait_complete)(void);
+};
+
+static struct rockchip_ddrclk_data ddr_data = {NULL, NULL};
+
+void rockchip_set_ddrclk_params(void __iomem *params)
{
- struct drm_device *drm;
- u32 lcdc_type = 0;
-
- drm = drm_device_get_by_name("rockchip");
- if (drm) {
- struct drm_connector *conn;
-
- list_for_each_entry(conn, &drm->mode_config.connector_list,
- head) {
- if (conn->encoder) {
- lcdc_type = conn->connector_type;
- break;
- }
- }
- }
-
- switch (lcdc_type) {
- case DRM_MODE_CONNECTOR_DPI:
- case DRM_MODE_CONNECTOR_LVDS:
- lcdc_type = SCREEN_LVDS;
- break;
- case DRM_MODE_CONNECTOR_DisplayPort:
- lcdc_type = SCREEN_DP;
- break;
- case DRM_MODE_CONNECTOR_HDMIA:
- case DRM_MODE_CONNECTOR_HDMIB:
- lcdc_type = SCREEN_HDMI;
- break;
- case DRM_MODE_CONNECTOR_TV:
- lcdc_type = SCREEN_TVOUT;
- break;
- case DRM_MODE_CONNECTOR_eDP:
- lcdc_type = SCREEN_EDP;
- break;
- case DRM_MODE_CONNECTOR_DSI:
- lcdc_type = SCREEN_MIPI;
- break;
- default:
- lcdc_type = SCREEN_NULL;
- break;
- }
-
- return lcdc_type;
+ ddr_data.params = params;
}
+EXPORT_SYMBOL(rockchip_set_ddrclk_params);
+
+void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void))
+{
+ ddr_data.dmcfreq_wait_complete = func;
+}
+EXPORT_SYMBOL(rockchip_set_ddrclk_dmcfreq_wait_complete);
static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
@@ -139,7 +101,7 @@
struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
u32 val;
- val = clk_readl(ddrclk->reg_base +
+ val = readl(ddrclk->reg_base +
ddrclk->mux_offset) >> ddrclk->mux_shift;
val &= GENMASK(ddrclk->mux_width - 1, 0);
@@ -153,116 +115,24 @@
.get_parent = rockchip_ddrclk_get_parent,
};
-static u32 ddr_clk_cached;
-
-static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long prate)
-{
- u32 ret;
- u32 lcdc_type;
-
- lcdc_type = rk_drm_get_lcdc_type();
-
- ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
- if (ret) {
- ddr_clk_cached = ret;
- ret = 0;
- } else {
- ddr_clk_cached = 0;
- ret = -1;
- }
-
- return ret;
-}
-
-static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- if (ddr_clk_cached)
- return (MHZ * ddr_clk_cached);
- else
- return (MHZ * scpi_ddr_get_clk_rate());
-}
-
-static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *prate)
-{
- rate = rate / MHZ;
- rate = (rate / 12) * 12;
-
- return (rate * MHZ);
-}
-
-static const struct clk_ops rockchip_ddrclk_scpi_ops = {
- .recalc_rate = rockchip_ddrclk_scpi_recalc_rate,
- .set_rate = rockchip_ddrclk_scpi_set_rate,
- .round_rate = rockchip_ddrclk_scpi_round_rate,
- .get_parent = rockchip_ddrclk_get_parent,
-};
-
-struct share_params {
- u32 hz;
- u32 lcdc_type;
- u32 vop;
- u32 vop_dclk_mode;
- u32 sr_idle_en;
- u32 addr_mcu_el3;
- /*
- * 1: need to wait flag1
- * 0: never wait flag1
- */
- u32 wait_flag1;
- /*
- * 1: need to wait flag1
- * 0: never wait flag1
- */
- u32 wait_flag0;
- u32 complt_hwirq;
- /* if need, add parameter after */
-};
-
-struct rockchip_ddrclk_data {
- u32 inited_flag;
- void __iomem *share_memory;
-};
-
-static struct rockchip_ddrclk_data ddr_data;
-
-static void rockchip_ddrclk_data_init(void)
-{
- struct arm_smccc_res res;
-
- res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDR);
-
- if (!res.a0) {
- ddr_data.share_memory = (void __iomem *)res.a1;
- ddr_data.inited_flag = 1;
- }
-}
-
static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
unsigned long drate,
unsigned long prate)
{
- struct share_params *p;
+ struct share_params_ddrclk *p;
struct arm_smccc_res res;
- if (!ddr_data.inited_flag)
- rockchip_ddrclk_data_init();
-
- p = (struct share_params *)ddr_data.share_memory;
-
- p->hz = drate;
- p->lcdc_type = rk_drm_get_lcdc_type();
- p->wait_flag1 = 1;
- p->wait_flag0 = 1;
+ p = (struct share_params_ddrclk *)ddr_data.params;
+ if (p)
+ p->hz = drate;
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE);
- if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT)
- rockchip_dmcfreq_wait_complete();
+ if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT) {
+ if (ddr_data.dmcfreq_wait_complete)
+ ddr_data.dmcfreq_wait_complete();
+ }
return res.a0;
}
@@ -284,15 +154,12 @@
unsigned long rate,
unsigned long *prate)
{
- struct share_params *p;
+ struct share_params_ddrclk *p;
struct arm_smccc_res res;
- if (!ddr_data.inited_flag)
- rockchip_ddrclk_data_init();
-
- p = (struct share_params *)ddr_data.share_memory;
-
- p->hz = rate;
+ p = (struct share_params_ddrclk *)ddr_data.params;
+ if (p)
+ p->hz = rate;
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE);
@@ -309,16 +176,15 @@
.get_parent = rockchip_ddrclk_get_parent,
};
-struct clk * __init
-rockchip_clk_register_ddrclk(const char *name, int flags,
- const char *const *parent_names,
- u8 num_parents, int mux_offset,
- int mux_shift, int mux_width,
- int div_shift, int div_width,
- int ddr_flag, void __iomem *reg_base)
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ const char *const *parent_names,
+ u8 num_parents, int mux_offset,
+ int mux_shift, int mux_width,
+ int div_shift, int div_width,
+ int ddr_flag, void __iomem *reg_base)
{
struct rockchip_ddrclk *ddrclk;
- struct clk_init_data init = {};
+ struct clk_init_data init;
struct clk *clk;
#ifdef CONFIG_ARM
@@ -343,14 +209,11 @@
init.ops = &rockchip_ddrclk_sip_ops;
break;
#endif
-#ifdef CONFIG_ROCKCHIP_DDRCLK_SCPI
- case ROCKCHIP_DDRCLK_SCPI:
- init.ops = &rockchip_ddrclk_scpi_ops;
- break;
-#endif
+#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP_V2
case ROCKCHIP_DDRCLK_SIP_V2:
init.ops = &rockchip_ddrclk_sip_ops_v2;
break;
+#endif
default:
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
kfree(ddrclk);
@@ -372,3 +235,4 @@
return clk;
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
--
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