From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/include/linux/mv643xx.h | 52 +---------------------------------------------------
1 files changed, 1 insertions(+), 51 deletions(-)
diff --git a/kernel/include/linux/mv643xx.h b/kernel/include/linux/mv643xx.h
index 69327b7..47e5679 100644
--- a/kernel/include/linux/mv643xx.h
+++ b/kernel/include/linux/mv643xx.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* mv643xx.h - MV-643XX Internal registers definition file.
*
* Copyright 2002 Momentum Computer, Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
* Copyright 2002 GALILEO TECHNOLOGY, LTD.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MV643XX_H
#define __ASM_MV643XX_H
@@ -921,52 +917,6 @@
#define MV64340_SERIAL_INIT_STATUS 0xf32c
extern void mv64340_irq_init(unsigned int base);
-
-/* MPSC Platform Device, Driver Data (Shared register regions) */
-#define MPSC_SHARED_NAME "mpsc_shared"
-
-#define MPSC_ROUTING_BASE_ORDER 0
-#define MPSC_SDMA_INTR_BASE_ORDER 1
-
-#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
-#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
-
-struct mpsc_shared_pdata {
- u32 mrr_val;
- u32 rcrr_val;
- u32 tcrr_val;
- u32 intr_cause_val;
- u32 intr_mask_val;
-};
-
-/* MPSC Platform Device, Driver Data */
-#define MPSC_CTLR_NAME "mpsc"
-
-#define MPSC_BASE_ORDER 0
-#define MPSC_SDMA_BASE_ORDER 1
-#define MPSC_BRG_BASE_ORDER 2
-
-#define MPSC_REG_BLOCK_SIZE 0x0038
-#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
-#define MPSC_BRG_REG_BLOCK_SIZE 0x0008
-
-struct mpsc_pdata {
- u8 mirror_regs;
- u8 cache_mgmt;
- u8 max_idle;
- int default_baud;
- int default_bits;
- int default_parity;
- int default_flow;
- u32 chr_1_val;
- u32 chr_2_val;
- u32 chr_10_val;
- u32 mpcr_val;
- u32 bcr_val;
- u8 brg_can_tune;
- u8 brg_clk_src;
- u32 brg_clk_freq;
-};
/* Watchdog Platform Device, Driver Data */
#define MV64x60_WDT_NAME "mv64x60_wdt"
--
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