From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/drivers/pinctrl/tegra/pinctrl-tegra.h | 30 ++++++++++++++----------------
1 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/kernel/drivers/pinctrl/tegra/pinctrl-tegra.h b/kernel/drivers/pinctrl/tegra/pinctrl-tegra.h
index 44c7194..fcad7f7 100644
--- a/kernel/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/kernel/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Driver for the NVIDIA Tegra pinmux
*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
*/
#ifndef __PINMUX_TEGRA_H__
@@ -25,6 +17,7 @@
int nbanks;
void __iomem **regs;
+ u32 *backup_regs;
};
enum tegra_pinconf_param {
@@ -104,7 +97,6 @@
* @tri_reg: Tri-state register offset.
* @tri_bank: Tri-state register bank.
* @tri_bit: Tri-state register bit.
- * @parked_bit: Parked register bit. -1 if unsupported.
* @einput_bit: Enable-input register bit.
* @odrain_bit: Open-drain register bit.
* @lock_bit: Lock register bit.
@@ -115,7 +107,8 @@
* drvup, slwr, slwf, and drvtype parameters.
* @drv_bank: Drive fields register bank.
* @hsm_bit: High Speed Mode register bit.
- * @schmitt_bit: Scmitt register bit.
+ * @sfsel_bit: GPIO/SFIO selection register bit.
+ * @schmitt_bit: Schmitt register bit.
* @lpmd_bit: Low Power Mode register bit.
* @drvdn_bit: Drive Down register bit.
* @drvdn_width: Drive Down field width.
@@ -126,6 +119,7 @@
* @slwf_bit: Slew Falling register bit.
* @slwf_width: Slew Falling field width.
* @drvtype_bit: Drive type register bit.
+ * @parked_bitmask: Parked register mask. 0 if unsupported.
*
* -1 in a *_reg field means that feature is unsupported for this group.
* *_bank and *_reg values are irrelevant when *_reg is -1.
@@ -143,10 +137,10 @@
const unsigned *pins;
u8 npins;
u8 funcs[4];
- s16 mux_reg;
- s16 pupd_reg;
- s16 tri_reg;
- s16 drv_reg;
+ s32 mux_reg;
+ s32 pupd_reg;
+ s32 tri_reg;
+ s32 drv_reg;
u32 mux_bank:2;
u32 pupd_bank:2;
u32 tri_bank:2;
@@ -154,13 +148,13 @@
s32 mux_bit:6;
s32 pupd_bit:6;
s32 tri_bit:6;
- s32 parked_bit:6;
s32 einput_bit:6;
s32 odrain_bit:6;
s32 lock_bit:6;
s32 ioreset_bit:6;
s32 rcv_sel_bit:6;
s32 hsm_bit:6;
+ s32 sfsel_bit:6;
s32 schmitt_bit:6;
s32 lpmd_bit:6;
s32 drvdn_bit:6;
@@ -172,6 +166,7 @@
s32 drvup_width:6;
s32 slwr_width:6;
s32 slwf_width:6;
+ u32 parked_bitmask;
};
/**
@@ -199,8 +194,11 @@
bool hsm_in_mux;
bool schmitt_in_mux;
bool drvtype_in_mux;
+ bool sfsel_in_mux;
};
+extern const struct dev_pm_ops tegra_pinctrl_pm;
+
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data);
#endif
--
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