From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 86 ++++++++++++++++++++++++++-----------------
1 files changed, 52 insertions(+), 34 deletions(-)
diff --git a/kernel/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/kernel/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
index 20b9864..e2bd2dc 100644
--- a/kernel/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+++ b/kernel/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/*
@@ -114,6 +106,7 @@
raw_spinlock_t lock;
+ struct irq_chip irqchip;
struct gpio_chip gc;
unsigned num_banks;
@@ -138,7 +131,7 @@
* iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Iproc GPIO register
*
- * @iproc_gpio: Iproc GPIO device
+ * @chip: Iproc GPIO device
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
@@ -293,6 +286,12 @@
iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
rising_or_high);
+
+ if (type & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev,
@@ -301,14 +300,6 @@
return 0;
}
-
-static struct irq_chip iproc_gpio_irq_chip = {
- .name = "bcm-iproc-gpio",
- .irq_ack = iproc_gpio_irq_ack,
- .irq_mask = iproc_gpio_irq_mask,
- .irq_unmask = iproc_gpio_irq_unmask,
- .irq_set_type = iproc_gpio_irq_set_type,
-};
/*
* Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
@@ -364,6 +355,18 @@
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
return 0;
+}
+
+static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct iproc_gpio *chip = gpiochip_get_data(gc);
+ unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
+ unsigned int shift = IPROC_GPIO_SHIFT(gpio);
+
+ if (readl(chip->base + offset) & BIT(shift))
+ return GPIO_LINE_DIRECTION_OUT;
+
+ return GPIO_LINE_DIRECTION_IN;
}
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
@@ -801,8 +804,7 @@
chip->dev = dev;
platform_set_drvdata(pdev, chip);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- chip->base = devm_ioremap_resource(dev, res);
+ chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->base);
@@ -842,11 +844,41 @@
gc->free = iproc_gpio_free;
gc->direction_input = iproc_gpio_direction_input;
gc->direction_output = iproc_gpio_direction_output;
+ gc->get_direction = iproc_gpio_get_direction;
gc->set = iproc_gpio_set;
gc->get = iproc_gpio_get;
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
"gpio-ranges");
+
+ /* optional GPIO interrupt support */
+ irq = platform_get_irq_optional(pdev, 0);
+ if (irq > 0) {
+ struct irq_chip *irqc;
+ struct gpio_irq_chip *girq;
+
+ irqc = &chip->irqchip;
+ irqc->name = dev_name(dev);
+ irqc->irq_ack = iproc_gpio_irq_ack;
+ irqc->irq_mask = iproc_gpio_irq_mask;
+ irqc->irq_unmask = iproc_gpio_irq_unmask;
+ irqc->irq_set_type = iproc_gpio_irq_set_type;
+ irqc->irq_enable = iproc_gpio_irq_unmask;
+ irqc->irq_disable = iproc_gpio_irq_mask;
+
+ girq = &gc->irq;
+ girq->chip = irqc;
+ girq->parent_handler = iproc_gpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(dev, 1,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+ girq->parents[0] = irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ }
ret = gpiochip_add_data(gc, chip);
if (ret < 0) {
@@ -870,20 +902,6 @@
goto err_rm_gpiochip;
}
}
- }
-
- /* optional GPIO interrupt support */
- irq = platform_get_irq(pdev, 0);
- if (irq) {
- ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0,
- handle_simple_irq, IRQ_TYPE_NONE);
- if (ret) {
- dev_err(dev, "no GPIO irqchip\n");
- goto err_rm_gpiochip;
- }
-
- gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq,
- iproc_gpio_irq_handler);
}
return 0;
--
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