From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/arch/arm/boot/dts/rk3288.dtsi | 1140 ++++++++++++++---------------------------------------------
1 files changed, 278 insertions(+), 862 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/rk3288.dtsi b/kernel/arch/arm/boot/dts/rk3288.dtsi
index c1373a9..c5b3c01 100644
--- a/kernel/arch/arm/boot/dts/rk3288.dtsi
+++ b/kernel/arch/arm/boot/dts/rk3288.dtsi
@@ -9,7 +9,6 @@
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/suspend/rockchip-rk3288.h>
-#include <dt-bindings/display/drm_mipi_dsi.h>
/ {
#address-cells = <2>;
@@ -20,7 +19,18 @@
interrupt-parent = <&gic>;
aliases {
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ gpio8 = &gpio8;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -39,8 +49,6 @@
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
- dsi0 = &dsi0;
- dsi1 = &dsi1;
};
arm-pmu {
@@ -50,6 +58,11 @@
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
};
cpus {
@@ -62,36 +75,53 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x500>;
+ enable-method = "psci";
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <322>;
+ clock-latency = <40000>;
clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
cpu1: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x501>;
+ enable-method = "psci";
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
cpu2: cpu@502 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x502>;
+ enable-method = "psci";
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
cpu3: cpu@503 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x503>;
+ enable-method = "psci";
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ dynamic-power-coefficient = <370>;
};
};
- cpu_opp_table: opp_table0 {
+ cpu_opp_table: cpu-opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -124,7 +154,7 @@
rockchip,pvtm-error = <1000>;
rockchip,pvtm-ref-temp = <35>;
rockchip,pvtm-temp-prop = <(-18) (-18)>;
- rockchip,thermal-zone = "soc-thermal";
+ rockchip,thermal-zone = "cpu-thermal";
opp-126000000 {
opp-hz = /bits/ 64 <126000000>;
@@ -228,7 +258,7 @@
};
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -322,7 +352,7 @@
ports = <&vopl_out>, <&vopb_out>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
@@ -336,7 +366,7 @@
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
@@ -350,7 +380,7 @@
status = "disabled";
};
- sdio1: dwmmc@ff0e0000 {
+ sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
@@ -364,7 +394,7 @@
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
@@ -376,7 +406,6 @@
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
- supports-emmc;
};
saradc: saradc@ff100000 {
@@ -509,6 +538,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
@@ -522,6 +553,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 3>, <&dmac_peri 4>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -548,6 +581,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 7>, <&dmac_peri 8>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
status = "disabled";
@@ -561,31 +596,40 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 9>, <&dmac_peri 10>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
- thermal_zones: thermal-zones {
- cpu_thermal: soc-thermal {
- polling-delay-passive = <200>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- sustainable-power = <1200>; /* milliwatts */
+ thermal-zones {
+ reserve_thermal: reserve_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ };
+
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
+
trips {
- cpu_alert0: trip-point@0 {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
- cpu_alert1: trip-point@1 {
- temperature = <85000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- soc_crit: soc-crit {
- temperature = <115000>; /* millicelsius */
+ cpu_crit: cpu_crit {
+ temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
@@ -593,24 +637,50 @@
cooling-maps {
map0 {
- trip = <&cpu_alert1>;
+ trip = <&cpu_alert0>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
+ <&cpu0 THERMAL_NO_LIMIT 6>,
+ <&cpu1 THERMAL_NO_LIMIT 6>,
+ <&cpu2 THERMAL_NO_LIMIT 6>,
+ <&cpu3 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu-thermal {
- polling-delay-passive = <200>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
thermal-sensors = <&tsadc 2>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
@@ -625,11 +695,11 @@
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "gpio", "otpout";
- pinctrl-0 = <&otp_gpio>;
- pinctrl-1 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
- rockchip,hw-tshut-temp = <120000>;
- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@@ -655,7 +725,7 @@
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0x0 0xff500000 0x0 0x20000>;
+ reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
clock-names = "usbhost", "utmi";
@@ -664,13 +734,10 @@
status = "disabled";
};
- /*
- * NOTE: ohci@ff520000 doesn't actually work on rk3288
- * hardware, but can work on rk3288w hardware.
- */
+ /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
usb_host0_ohci: usb@ff520000 {
compatible = "generic-ohci";
- reg = <0x0 0xff520000 0x0 0x20000>;
+ reg = <0x0 0xff520000 0x0 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
clock-names = "usbhost", "utmi";
@@ -689,6 +756,7 @@
dr_mode = "host";
phys = <&usbphy2>;
phy-names = "usb2-phy";
+ snps,reset-phy-on-wake;
status = "disabled";
};
@@ -703,7 +771,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -714,28 +781,7 @@
reg = <0x0 0xff5c0000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HSIC>;
- clock-names = "usbhost";
status = "disabled";
- };
-
- dmc: dmc@ff610000 {
- compatible = "rockchip,rk3288-dmc", "syscon";
- rockchip,cru = <&cru>;
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmu>;
- rockchip,sgrf = <&sgrf>;
- rockchip,noc = <&noc>;
- reg = <0x0 0xff610000 0x0 0x3fc
- 0x0 0xff620000 0x0 0x294
- 0x0 0xff630000 0x0 0x3fc
- 0x0 0xff640000 0x0 0x294>;
- rockchip,sram = <&ddr_sram>;
- clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
- <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
- <&cru ARMCLK>, <&cru ACLK_DMAC1>;
- clock-names = "pclk_ddrupctl0", "pclk_publ0",
- "pclk_ddrupctl1", "pclk_publ1",
- "arm_clk", "aclk_dmac1";
};
i2c2: i2c@ff660000 {
@@ -757,7 +803,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -768,7 +814,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -779,7 +825,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -790,7 +836,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -803,7 +849,7 @@
clock-names = "pclk", "timer";
};
- bus_intmem@ff700000 {
+ bus_intmem: sram@ff700000 {
compatible = "mmio-sram";
reg = <0x0 0xff700000 0x0 0x18000>;
#address-cells = <1>;
@@ -813,85 +859,11 @@
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
- ddr_sram: ddr-sram@1000 {
- compatible = "rockchip,rk3288-ddr-sram";
- reg = <0x1000 0x4000>;
- };
};
- sram@ff720000 {
+ pmu_sram: sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0x0 0xff720000 0x0 0x1000>;
- };
-
- qos_gpu_r: qos@ffaa0000 {
- compatible = "syscon";
- reg = <0x0 0xffaa0000 0x0 0x20>;
- };
-
- qos_gpu_w: qos@ffaa0080 {
- compatible = "syscon";
- reg = <0x0 0xffaa0080 0x0 0x20>;
- };
-
- qos_vio1_vop: qos@ffad0000 {
- compatible = "syscon";
- reg = <0x0 0xffad0000 0x0 0x20>;
- };
-
- qos_vio1_isp_w0: qos@ffad0100 {
- compatible = "syscon";
- reg = <0x0 0xffad0100 0x0 0x20>;
- };
-
- qos_vio1_isp_w1: qos@ffad0180 {
- compatible = "syscon";
- reg = <0x0 0xffad0180 0x0 0x20>;
- };
-
- qos_vio0_vop: qos@ffad0400 {
- compatible = "syscon";
- reg = <0x0 0xffad0400 0x0 0x20>;
- };
-
- qos_vio0_vip: qos@ffad0480 {
- compatible = "syscon";
- reg = <0x0 0xffad0480 0x0 0x20>;
- };
-
- qos_vio0_iep: qos@ffad0500 {
- compatible = "syscon";
- reg = <0x0 0xffad0500 0x0 0x20>;
- };
-
- qos_vio2_rga_r: qos@ffad0800 {
- compatible = "syscon";
- reg = <0x0 0xffad0800 0x0 0x20>;
- };
-
- qos_vio2_rga_w: qos@ffad0880 {
- compatible = "syscon";
- reg = <0x0 0xffad0880 0x0 0x20>;
- };
-
- qos_vio1_isp_r: qos@ffad0900 {
- compatible = "syscon";
- reg = <0x0 0xffad0900 0x0 0x20>;
- };
-
- qos_video: qos@ffae0000 {
- compatible = "syscon";
- reg = <0x0 0xffae0000 0x0 0x20>;
- };
-
- qos_hevc_r: qos@ffaf0000 {
- compatible = "syscon";
- reg = <0x0 0xffaf0000 0x0 0x20>;
- };
-
- qos_hevc_w: qos@ffaf0080 {
- compatible = "syscon";
- reg = <0x0 0xffaf0080 0x0 0x20>;
};
pmu: power-management@ff730000 {
@@ -903,6 +875,9 @@
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
+
+ assigned-clocks = <&cru SCLK_EDP_24M>;
+ assigned-clock-parents = <&xin24m>;
/*
* Note: Although SCLK_* are the working clocks
@@ -927,7 +902,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
- pd_vio@RK3288_PD_VIO {
+ power-domain@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@@ -970,7 +945,7 @@
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@RK3288_PD_HEVC {
+ power-domain@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
@@ -984,7 +959,7 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@RK3288_PD_VIDEO {
+ power-domain@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
@@ -995,7 +970,7 @@
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@RK3288_PD_GPU {
+ power-domain@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
@@ -1003,7 +978,7 @@
};
};
- reboot_mode: reboot-mode {
+ reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x94>;
mode-normal = <BOOT_NORMAL>;
@@ -1025,35 +1000,39 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks =
- <&cru PLL_GPLL>, <&cru PLL_NPLL>,
- <&cru ACLK_CPU>, <&cru HCLK_CPU>,
- <&cru PCLK_CPU>, <&cru ACLK_PERI>,
- <&cru HCLK_PERI>, <&cru PCLK_PERI>,
- <&cru ACLK_VIO0>, <&cru ACLK_VIO1>,
- <&cru ACLK_GPU>;
- assigned-clock-rates =
- <594000000>, <500000000>,
- <300000000>, <150000000>,
- <75000000>, <300000000>,
- <150000000>, <75000000>,
- <594000000>, <297000000>,
- <200000000>;
+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+ <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_VIO0>, <&cru ACLK_VIO1>;
+ assigned-clock-rates = <594000000>, <500000000>,
+ <300000000>, <150000000>,
+ <75000000>, <300000000>,
+ <150000000>, <75000000>,
+ <594000000>, <297000000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
- mipi_phy_rx0: mipi-phy-rx0 {
- compatible = "rockchip,rk3288-mipi-dphy";
- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
- clock-names = "dphy-ref", "pclk";
+ edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
status = "disabled";
};
io_domains: io-domains {
compatible = "rockchip,rk3288-io-voltage-domain";
+ status = "disabled";
+ };
+
+ mipi_phy_rx0: mipi-phy-rx0 {
+ compatible = "rockchip,rk3288-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
+ clock-names = "dphy-ref", "pclk";
status = "disabled";
};
@@ -1140,6 +1119,8 @@
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
+ resets = <&cru SRST_USBHOST0_PHY>;
+ reset-names = "phy-reset";
};
usbphy2: usb-phy@348 {
@@ -1188,8 +1169,8 @@
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff880000 0x0 0x10000>;
#sound-dai-cells = <0>;
- clock-names = "hclk", "mclk";
- clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
dmas = <&dmac_bus_s 2>;
dma-names = "tx";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -1204,14 +1185,12 @@
reg = <0x0 0xff890000 0x0 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
- dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
+ clock-names = "i2s_clk", "i2s_hclk";
assigned-clocks = <&cru SCLK_I2S_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
+ dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
resets = <&cru SRST_I2S0>;
@@ -1231,7 +1210,7 @@
status = "disabled";
};
- crypto: cypto-controller@ff8a0000 {
+ crypto: crypto@ff8a0000 {
compatible = "rockchip,rk3288-crypto";
reg = <0x0 0xff8a0000 0x0 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -1247,8 +1226,8 @@
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
- clock-names = "hclk", "mclk";
- clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
+ clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
+ clock-names = "mclk", "hclk";
dmas = <&dmac_bus_s 3>;
dma-names = "tx";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -1280,29 +1259,6 @@
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
- };
-
- cif_isp0: cif_isp@ff910000 {
- compatible = "rockchip,rk3288-cif-isp";
- rockchip,grf = <&grf>;
- reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
- reg-names = "register", "csihost-register";
- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
- <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
- <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
- <&cru SCLK_MIPIDSI_24M>;
- clock-names = "aclk_isp", "hclk_isp",
- "sclk_isp", "sclk_isp_jpe",
- "pclk_mipi_csi", "pclk_isp_in",
- "sclk_mipidsi_24m";
- resets = <&cru SRST_ISP>;
- reset-names = "rst_isp";
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cif_isp10_irq";
- power-domains = <&power RK3288_PD_VIO>;
- rockchip,isp,iommu-enable = <1>;
- iommus = <&isp_mmu>;
status = "disabled";
};
@@ -1420,14 +1376,14 @@
remote-endpoint = <&dsi0_in_vopb>;
};
- vopb_out_lvds: endpoint@3 {
+ vopb_out_dsi1: endpoint@3 {
reg = <3>;
- remote-endpoint = <&lvds_in_vopb>;
+ remote-endpoint = <&dsi1_in_vopb>;
};
- vopb_out_dsi1: endpoint@4 {
+ vopb_out_lvds: endpoint@4 {
reg = <4>;
- remote-endpoint = <&dsi1_in_vopb>;
+ remote-endpoint = <&lvds_in_vopb>;
};
vopb_out_rgb: endpoint@5 {
@@ -1482,14 +1438,14 @@
remote-endpoint = <&dsi0_in_vopl>;
};
- vopl_out_lvds: endpoint@3 {
+ vopl_out_dsi1: endpoint@3 {
reg = <3>;
- remote-endpoint = <&lvds_in_vopl>;
+ remote-endpoint = <&dsi1_in_vopl>;
};
- vopl_out_dsi1: endpoint@4 {
+ vopl_out_lvds: endpoint@4 {
reg = <4>;
- remote-endpoint = <&dsi1_in_vopl>;
+ remote-endpoint = <&lvds_in_vopl>;
};
vopl_out_rgb: endpoint@5 {
@@ -1606,7 +1562,7 @@
status = "disabled";
};
- edp: edp@ff970000 {
+ edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0x0 0xff970000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -1624,17 +1580,14 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
-
- port@0 {
+ edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
-
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
-
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
@@ -1649,8 +1602,7 @@
reg-io-width = <4>;
#sound-dai-cells = <0>;
rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hdmi", "hdmi_wakeup";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec";
pinctrl-names = "default", "sleep";
@@ -1674,6 +1626,19 @@
};
};
};
+ };
+
+ vpu: video-codec@ff9a0000 {
+ compatible = "rockchip,rk3288-vpu";
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3288_PD_VIDEO>;
+ status = "disabled";
};
mpp_srv: mpp-srv {
@@ -1730,8 +1695,8 @@
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
- power-domains = <&power RK3288_PD_VIDEO>;
#iommu-cells = <0>;
+ power-domains = <&power RK3288_PD_VIDEO>;
status = "disabled";
};
@@ -1771,8 +1736,7 @@
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
- reg = <0x0 0xff9c0440 0x0 0x40>,
- <0x0 0xff9c0480 0x0 0x40>;
+ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
@@ -1783,15 +1747,14 @@
};
gpu: gpu@ffa30000 {
- compatible = "arm,malit764",
- "arm,malit76x",
- "arm,malit7xx",
+ compatible = "rockchip,rk3288-mali", "arm,mali-t760",
+ "arm,malit764", "arm,malit76x", "arm,malit7xx",
"arm,mali-midgard";
reg = <0x0 0xffa30000 0x0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "JOB", "MMU", "GPU";
+ interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
operating-points-v2 = <&gpu_opp_table>;
@@ -1811,7 +1774,7 @@
};
};
- gpu_opp_table: opp-table1 {
+ gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
clocks = <&cru PLL_GPLL>;
@@ -1824,6 +1787,10 @@
3 61
>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ };
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
@@ -1836,54 +1803,84 @@
opp-hz = /bits/ 64 <420000000>;
opp-microvolt = <1100000>;
};
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <1200000>;
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1250000>;
};
};
- noc: syscon@ffac0000 {
- compatible = "rockchip,rk3288-noc", "syscon";
- reg = <0x0 0xffac0000 0x0 0x2000>;
+ qos_gpu_r: qos@ffaa0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffaa0000 0x0 0x20>;
};
- nocp_core: nocp-core@ffac0400 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac0400 0x0 0x400>;
+ qos_gpu_w: qos@ffaa0080 {
+ compatible = "syscon";
+ reg = <0x0 0xffaa0080 0x0 0x20>;
};
- nocp_gpu: nocp-gpu@ffac0800 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac0800 0x0 0x400>;
+ qos_vio1_vop: qos@ffad0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0000 0x0 0x20>;
};
- nocp_peri: nocp-peri@ffac0c00 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac0c00 0x0 0x400>;
+ qos_vio1_isp_w0: qos@ffad0100 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0100 0x0 0x20>;
};
- nocp_vpu: nocp-vpu@ffac1000 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac1000 0x0 0x400>;
+ qos_vio1_isp_w1: qos@ffad0180 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0180 0x0 0x20>;
};
- nocp_vio0: nocp-vio0@ffac1400 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac1400 0x0 0x400>;
+ qos_vio0_vop: qos@ffad0400 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0400 0x0 0x20>;
};
- nocp_vio1: nocp-vio1@ffac1800 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac1800 0x0 0x400>;
+ qos_vio0_vip: qos@ffad0480 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0480 0x0 0x20>;
};
- nocp_vio2: nocp-vio2@ffac1c00 {
- compatible = "rockchip,rk3288-nocp";
- reg = <0x0 0xffac1c00 0x0 0x400>;
+ qos_vio0_iep: qos@ffad0500 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0500 0x0 0x20>;
+ };
+
+ qos_vio2_rga_r: qos@ffad0800 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0800 0x0 0x20>;
+ };
+
+ qos_vio2_rga_w: qos@ffad0880 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0880 0x0 0x20>;
+ };
+
+ qos_vio1_isp_r: qos@ffad0900 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0900 0x0 0x20>;
+ };
+
+ qos_video: qos@ffae0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffae0000 0x0 0x20>;
+ };
+
+ qos_hevc_r: qos@ffaf0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffaf0000 0x0 0x20>;
+ };
+
+ qos_hevc_w: qos@ffaf0080 {
+ compatible = "syscon";
+ reg = <0x0 0xffaf0080 0x0 0x20>;
};
efuse: efuse@ffb40000 {
- compatible = "rockchip,rockchip-efuse";
+ compatible = "rockchip,rk3288-efuse";
reg = <0x0 0xffb40000 0x0 0x20>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1902,10 +1899,10 @@
reg = <0x6 0x1>;
bits = <0 4>;
};
- efuse_id: id@7 {
- reg = <0x7 0x10>;
+ cpu_id: cpu-id@7 {
+ reg = <0x07 0x10>;
};
- cpu_leakage: cpu-leakage@17 {
+ cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
performance_w: performance@1c {
@@ -1933,6 +1930,30 @@
rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor";
+ };
+
+ rockchip_suspend: rockchip-suspend {
+ compatible = "rockchip,pm-rk3288";
+ status = "disabled";
+ rockchip,sleep-mode-config = <
+ (0
+ |RKPM_CTR_PWR_DMNS
+ |RKPM_CTR_GTCLKS
+ |RKPM_CTR_PLLS
+ |RKPM_CTR_ARMOFF_LPMD
+ |RKPM_CTR_SYSCLK_OSC_DIS
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_GPIO_WKUP_EN
+ )
+ >;
+ rockchip,pwm-regulator-config = <
+ (0
+ | PWM2_REGULATOR_EN
+ )
+ >;
};
pinctrl: pinctrl {
@@ -2060,616 +2081,11 @@
#interrupt-cells = <2>;
};
- hdmi {
- hdmi_gpio: hdmi-gpio {
- rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO
- &pcfg_pull_none>,
- <7 RK_PC4 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- hdmi_cec: hdmi-cec {
- rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
- };
-
- hdmi_ddc: hdmi-ddc {
- rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
- <7 RK_PC4 2 &pcfg_pull_none>;
- };
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
bias-disable;
drive-strength = <12>;
};
-
- suspend {
- global_pwroff: global-pwroff {
- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
- };
-
- ddrio_pwroff: ddrio-pwroff {
- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
- };
-
- ddr0_retention: ddr0-retention {
- rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
- };
-
- ddr1_retention: ddr1-retention {
- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
- };
- };
-
- edp {
- edp_hpd: edp-hpd {
- rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
- };
- };
-
- i2c0 {
- i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
- <0 RK_PC0 1 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
- <8 RK_PA5 1 &pcfg_pull_none>;
- };
- };
-
- i2c2 {
- i2c2_xfer: i2c2-xfer {
- rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
- <6 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- i2c3 {
- i2c3_xfer: i2c3-xfer {
- rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
- <2 RK_PC1 1 &pcfg_pull_none>;
- };
- };
-
- i2c4 {
- i2c4_xfer: i2c4-xfer {
- rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
- <7 RK_PC2 1 &pcfg_pull_none>;
- };
- };
-
- i2c5 {
- i2c5_xfer: i2c5-xfer {
- rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
- <7 RK_PC4 1 &pcfg_pull_none>;
- };
- };
-
- i2s0 {
- i2s0_bus: i2s0-bus {
- rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
- <6 RK_PA1 1 &pcfg_pull_none>,
- <6 RK_PA2 1 &pcfg_pull_none>,
- <6 RK_PA3 1 &pcfg_pull_none>,
- <6 RK_PA4 1 &pcfg_pull_none>;
- };
-
- i2s0_mclk: i2s0-mclk {
- rockchip,pins = <6 RK_PB0 1 &pcfg_pull_none>;
- };
- };
-
- lcdc {
- lcdc_rgb_pins: lcdc-rgb-pins {
- rockchip,pins = <1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
- <1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
- <1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
- <1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
- };
-
- lcdc_sleep_pins: lcdc-sleep-pins {
- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
- };
- };
-
- sdmmc {
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
- };
-
- sdmmc_cd: sdmmc-cd {
- rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
- };
-
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
- <6 RK_PC1 1 &pcfg_pull_up>,
- <6 RK_PC2 1 &pcfg_pull_up>,
- <6 RK_PC3 1 &pcfg_pull_up>;
- };
- };
-
- sdio0 {
- sdio0_bus1: sdio0-bus1 {
- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
- };
-
- sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
- <4 RK_PC5 1 &pcfg_pull_up>,
- <4 RK_PC6 1 &pcfg_pull_up>,
- <4 RK_PC7 1 &pcfg_pull_up>;
- };
-
- sdio0_cmd: sdio0-cmd {
- rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
- };
-
- sdio0_clk: sdio0-clk {
- rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
- };
-
- sdio0_cd: sdio0-cd {
- rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
- };
-
- sdio0_wp: sdio0-wp {
- rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
- };
-
- sdio0_pwr: sdio0-pwr {
- rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
- };
-
- sdio0_bkpwr: sdio0-bkpwr {
- rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
- };
-
- sdio0_int: sdio0-int {
- rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
- };
- };
-
- sdio1 {
- sdio1_bus1: sdio1-bus1 {
- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
- };
-
- sdio1_bus4: sdio1-bus4 {
- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
- <3 RK_PD1 4 &pcfg_pull_up>,
- <3 RK_PD2 4 &pcfg_pull_up>,
- <3 RK_PD3 4 &pcfg_pull_up>;
- };
-
- sdio1_cd: sdio1-cd {
- rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
- };
-
- sdio1_wp: sdio1-wp {
- rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
- };
-
- sdio1_bkpwr: sdio1-bkpwr {
- rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
- };
-
- sdio1_int: sdio1-int {
- rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
- };
-
- sdio1_cmd: sdio1-cmd {
- rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
- };
-
- sdio1_clk: sdio1-clk {
- rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
- };
-
- sdio1_pwr: sdio1-pwr {
- rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
- };
- };
-
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
- };
-
- emmc_pwr: emmc-pwr {
- rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
- };
-
- emmc_bus1: emmc-bus1 {
- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
- };
-
- emmc_bus4: emmc-bus4 {
- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
- <3 RK_PA1 2 &pcfg_pull_up>,
- <3 RK_PA2 2 &pcfg_pull_up>,
- <3 RK_PA3 2 &pcfg_pull_up>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
- <3 RK_PA1 2 &pcfg_pull_up>,
- <3 RK_PA2 2 &pcfg_pull_up>,
- <3 RK_PA3 2 &pcfg_pull_up>,
- <3 RK_PA4 2 &pcfg_pull_up>,
- <3 RK_PA5 2 &pcfg_pull_up>,
- <3 RK_PA6 2 &pcfg_pull_up>,
- <3 RK_PA7 2 &pcfg_pull_up>;
- };
- };
-
- spi0 {
- spi0_clk: spi0-clk {
- rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
- };
- spi0_cs0: spi0-cs0 {
- rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
- };
- spi0_tx: spi0-tx {
- rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
- };
- spi0_rx: spi0-rx {
- rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
- };
- spi0_cs1: spi0-cs1 {
- rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
- };
- };
- spi1 {
- spi1_clk: spi1-clk {
- rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
- };
- spi1_cs0: spi1-cs0 {
- rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
- };
- spi1_rx: spi1-rx {
- rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
- };
- spi1_tx: spi1-tx {
- rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
- };
- };
-
- spi2 {
- spi2_cs1: spi2-cs1 {
- rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
- };
- spi2_clk: spi2-clk {
- rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
- };
- spi2_cs0: spi2-cs0 {
- rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
- };
- spi2_rx: spi2-rx {
- rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
- };
- spi2_tx: spi2-tx {
- rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
- <4 RK_PC1 1 &pcfg_pull_up>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
- <5 RK_PB1 1 &pcfg_pull_up>;
- };
-
- uart1_cts: uart1-cts {
- rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
- };
-
- uart1_rts: uart1-rts {
- rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
- };
- };
-
- uart2 {
- uart2_xfer: uart2-xfer {
- rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
- <7 RK_PC7 1 &pcfg_pull_up>;
- };
- /* no rts / cts for uart2 */
- };
-
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
- <7 RK_PB0 1 &pcfg_pull_up>;
- };
-
- uart3_cts: uart3-cts {
- rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
- };
-
- uart3_rts: uart3-rts {
- rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- uart4 {
- uart4_xfer: uart4-xfer {
- rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
- <5 RK_PB6 3 &pcfg_pull_up>;
- };
-
- uart4_cts: uart4-cts {
- rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
- };
-
- uart4_rts: uart4-rts {
- rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
- };
- };
-
- tsadc {
- otp_gpio: otp-gpio {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- otp_out: otp-out {
- rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
- };
-
- pwm0_pin_pull_down: pwm0-pin-pull-down {
- rockchip,pins = <7 RK_PA0 1 &pcfg_pull_down>;
- };
-
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
- };
-
- pwm1_pin_pull_down: pwm1-pin-pull-down {
- rockchip,pins = <7 RK_PA1 1 &pcfg_pull_down>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
- };
-
- pwm2_pin_pull_down: pwm2-pin-pull-down {
- rockchip,pins = <7 RK_PC6 3 &pcfg_pull_down>;
- };
- };
-
- pwm3 {
- pwm3_pin: pwm3-pin {
- rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
- };
-
- pwm3_pin_pull_down: pwm3-pin-pull-down {
- rockchip,pins = <7 RK_PC7 3 &pcfg_pull_down>;
- };
- };
-
- gmac {
- rgmii_pins: rgmii-pins {
- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
- <3 RK_PD7 3 &pcfg_pull_none>,
- <3 RK_PD2 3 &pcfg_pull_none>,
- <3 RK_PD3 3 &pcfg_pull_none>,
- <3 RK_PD4 3 &pcfg_pull_none_12ma>,
- <3 RK_PD5 3 &pcfg_pull_none_12ma>,
- <3 RK_PD0 3 &pcfg_pull_none_12ma>,
- <3 RK_PD1 3 &pcfg_pull_none_12ma>,
- <4 RK_PA0 3 &pcfg_pull_none>,
- <4 RK_PA5 3 &pcfg_pull_none>,
- <4 RK_PA6 3 &pcfg_pull_none>,
- <4 RK_PB1 3 &pcfg_pull_none_12ma>,
- <4 RK_PA4 3 &pcfg_pull_none_12ma>,
- <4 RK_PA1 3 &pcfg_pull_none>,
- <4 RK_PA3 3 &pcfg_pull_none>;
- };
-
- rmii_pins: rmii-pins {
- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
- <3 RK_PD7 3 &pcfg_pull_none>,
- <3 RK_PD4 3 &pcfg_pull_none>,
- <3 RK_PD5 3 &pcfg_pull_none>,
- <4 RK_PA0 3 &pcfg_pull_none>,
- <4 RK_PA5 3 &pcfg_pull_none>,
- <4 RK_PA4 3 &pcfg_pull_none>,
- <4 RK_PA1 3 &pcfg_pull_none>,
- <4 RK_PA2 3 &pcfg_pull_none>,
- <4 RK_PA3 3 &pcfg_pull_none>;
- };
- };
-
- spdif {
- spdif_tx: spdif-tx {
- rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
- };
- };
-
- isp_pin {
- isp_mipi: isp-mipi {
- rockchip,pins =
- /* cif_clkout */
- <2 RK_PB3 1 &pcfg_pull_none>;
- };
-
- isp_dvp_d2d9: isp-d2d9 {
- rockchip,pins =
- /* cif_data2 ... cif_data9 */
- <2 RK_PA0 1 &pcfg_pull_none>,
- <2 RK_PA1 1 &pcfg_pull_none>,
- <2 RK_PA2 1 &pcfg_pull_none>,
- <2 RK_PA3 1 &pcfg_pull_none>,
- <2 RK_PA4 1 &pcfg_pull_none>,
- <2 RK_PA5 1 &pcfg_pull_none>,
- <2 RK_PA6 1 &pcfg_pull_none>,
- <2 RK_PA7 1 &pcfg_pull_none>,
- /* cif_sync, cif_href */
- <2 RK_PB0 1 &pcfg_pull_none>,
- <2 RK_PB1 1 &pcfg_pull_none>,
- /* cif_clkin */
- <2 RK_PB2 1 &pcfg_pull_none>;
- };
-
- isp_dvp_d0d1: isp-d0d1 {
- rockchip,pins =
- /* cif_data0, cif_data1 */
- <2 RK_PB4 1 &pcfg_pull_none>,
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- isp_dvp_d10d11: isp-d10d11 {
- rockchip,pins =
- /* cif_data10, cif_data11 */
- <2 RK_PB6 1 &pcfg_pull_none>,
- <2 RK_PB7 1 &pcfg_pull_none>;
- };
-
- isp_dvp_d0d7: isp-d0d7 {
- rockchip,pins =
- /* cif_data0 ... cif_data7 */
- <2 RK_PB4 1 &pcfg_pull_none>,
- <2 RK_PB5 1 &pcfg_pull_none>,
- <2 RK_PA0 1 &pcfg_pull_none>,
- <2 RK_PA1 1 &pcfg_pull_none>,
- <2 RK_PA2 1 &pcfg_pull_none>,
- <2 RK_PA3 1 &pcfg_pull_none>,
- <2 RK_PA4 1 &pcfg_pull_none>,
- <2 RK_PA5 1 &pcfg_pull_none>;
- };
-
- isp_shutter: isp-shutter {
- rockchip,pins =
- /* SHUTTEREN, SHUTTERTRIG */
- <7 RK_PB4 2 &pcfg_pull_none>,
- <7 RK_PB7 2 &pcfg_pull_none>;
- };
-
- isp_flash_trigger: isp-flash-trigger {
- rockchip,pins =
- /* ISP_FLASHTRIGOU */
- <7 RK_PB5 2 &pcfg_pull_none>;
- };
-
- isp_prelight: isp-prelight {
- rockchip,pins =
- /* ISP_PRELIGHTTRIG */
- <7 RK_PB6 2 &pcfg_pull_none>;
- };
-
- isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
- rockchip,pins =
- /* ISP_FLASHTRIGOU */
- <7 RK_PB5 2 &pcfg_pull_none>;
- };
- };
-
- cif_pin {
- cif_dvp_d0d1: cif-dvp-d0d1 {
- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
- <2 RK_PB5 1 &pcfg_pull_none>; /* cif_data1 */
- };
-
- cif_dvp_d2d9: cif-dvp-d2d9 {
- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
- <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
- <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
- <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
- <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
- <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
- <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
- <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
- <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
- <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
- <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
- <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
- };
-
- cif_dvp_d10d11: cif-dvp-d10d11 {
- rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, /* cif_data10 */
- <2 RK_PB7 1 &pcfg_pull_none>; /* cif_data11 */
- };
- };
-
- };
-
- rockchip_suspend: rockchip-suspend {
- compatible = "rockchip,pm-rk3288";
- status = "disabled";
- rockchip,sleep-mode-config = <
- (0
- |RKPM_CTR_PWR_DMNS
- |RKPM_CTR_GTCLKS
- |RKPM_CTR_PLLS
- |RKPM_CTR_ARMOFF_LPMD
- |RKPM_CTR_SYSCLK_OSC_DIS
- )
- >;
- rockchip,wakeup-config = <
- (0
- | RKPM_GPIO_WKUP_EN
- )
- >;
- rockchip,pwm-regulator-config = <
- (0
- | PWM2_REGULATOR_EN
- )
- >;
};
};
+
+#include "rk3288-pinctrl.dtsi"
--
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