From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/arch/arm/boot/dts/r8a7778.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++----------
1 files changed, 42 insertions(+), 10 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/r8a7778.dtsi b/kernel/arch/arm/boot/dts/r8a7778.dtsi
index 1bce16c..c9f8735 100644
--- a/kernel/arch/arm/boot/dts/r8a7778.dtsi
+++ b/kernel/arch/arm/boot/dts/r8a7778.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for Renesas r8a7778
+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
@@ -78,11 +78,12 @@
<0xfe780010 4>,
<0xfe780024 4>,
<0xfe780044 4>,
- <0xfe780064 4>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ <0xfe780064 4>,
+ <0xfe780000 4>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>;
};
@@ -141,7 +142,7 @@
interrupt-controller;
};
- pfc: pin-controller@fffc0000 {
+ pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7778";
reg = <0xfffc0000 0x118>;
};
@@ -367,6 +368,30 @@
status = "disabled";
};
+ hscif0: serial@ffe48000 {
+ compatible = "renesas,hscif-r8a7778",
+ "renesas,rcar-gen1-hscif", "renesas,hscif";
+ reg = <0xffe48000 96>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
+ <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ hscif1: serial@ffe49000 {
+ compatible = "renesas,hscif-r8a7778",
+ "renesas,rcar-gen1-hscif", "renesas,hscif";
+ reg = <0xffe49000 96>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
+ <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
mmcif: mmc@ffe4e000 {
compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
reg = <0xffe4e000 0x100>;
@@ -376,7 +401,7 @@
status = "disabled";
};
- sdhi0: sd@ffe4c000 {
+ sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
@@ -386,7 +411,7 @@
status = "disabled";
};
- sdhi1: sd@ffe4d000 {
+ sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
@@ -396,7 +421,7 @@
status = "disabled";
};
- sdhi2: sd@ffe4f000 {
+ sdhi2: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
@@ -474,14 +499,17 @@
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
/* Fixed ratio clocks */
@@ -535,6 +563,8 @@
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
+ <&cpg_clocks R8A7778_CLK_S>,
+ <&cpg_clocks R8A7778_CLK_S>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
@@ -551,6 +581,7 @@
R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
+ R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
@@ -560,6 +591,7 @@
clock-output-names =
"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
"scif1", "scif2", "scif3", "scif4", "scif5",
+ "hscif0", "hscif1",
"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
"ssi2", "ssi3", "sru", "hspi";
};
--
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