From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/arch/arm/boot/dts/nspire.dtsi | 32 +++++++++++++++++++-------------
1 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/nspire.dtsi b/kernel/arch/arm/boot/dts/nspire.dtsi
index 1a5ae4c..90e033d 100644
--- a/kernel/arch/arm/boot/dts/nspire.dtsi
+++ b/kernel/arch/arm/boot/dts/nspire.dtsi
@@ -1,17 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/boot/nspire.dtsi
*
* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- *
*/
-/include/ "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
@@ -99,8 +95,14 @@
reg = <0xC0000000 0x1000>;
interrupts = <21>;
- clocks = <&apb_pclk>;
- clock-names = "apb_pclk";
+ /*
+ * We assume the same clock is fed to APB and CLCDCLK.
+ * There is some code to scale the clock down by a factor
+ * 48 for the display so likely the frequency to the
+ * display is 1MHz and the CLCDCLK is 48 MHz.
+ */
+ clocks = <&apb_pclk>, <&apb_pclk>;
+ clock-names = "clcdclk", "apb_pclk";
};
adc: adc@C4000000 {
@@ -143,15 +145,19 @@
timer0: timer@900C0000 {
reg = <0x900C0000 0x1000>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
timer1: timer@900D0000 {
reg = <0x900D0000 0x1000>;
interrupts = <19>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
watchdog: watchdog@90060000 {
--
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