From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 29 +++++++++++++++++++----------
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 25462f7..33a70f4 100644
--- a/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
@@ -16,6 +10,7 @@
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory@10000000 {
+ device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@@ -76,9 +71,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
- cs-gpios = <&gpio4 24 0>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
- flash@0 {
+ som_flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
@@ -88,11 +83,24 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
+ phy-handle = <ðphy>;
phy-mode = "rgmii";
phy-reset-duration = <10>; /* in msecs */
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
phy-supply = <&vdd_eth_io_reg>;
status = "disabled";
+
+ fec_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ txc-skew-ps = <1680>;
+ rxc-skew-ps = <1860>;
+ };
+ };
};
&gpmi {
@@ -107,7 +115,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- eeprom@50 {
+ som_eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
@@ -117,6 +125,7 @@
reg = <0x58>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
+ interrupt-controller;
regulators {
vddcore_reg: bcore1 {
--
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