From f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 01:04:47 +0000
Subject: [PATCH] add driver 5G
---
kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 42 +++++++++++++++++++++++++++---------------
1 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 82d8df0..16addb3 100644
--- a/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
@@ -37,7 +31,6 @@
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
- fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
@@ -142,14 +135,15 @@
pwgt2spi_reg: pwgt2spi {
regulator-always-on;
};
-
- vcoincell_reg: vcoincell {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
};
};
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ max-frequency = <50000000>;
+ bus-width = <1>;
};
&esdhc2 {
@@ -174,9 +168,12 @@
};
&i2c2 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
clock-frequency = <400000>;
+ scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
status = "okay";
mma7455l@1d {
@@ -241,6 +238,14 @@
>;
};
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5
+ >;
+ };
+
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
@@ -282,6 +287,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed
+ MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed
+ >;
+ };
+
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
--
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