From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/sound/soc/tegra/tegra_asoc_utils.c | 129 +++++++++++++++++++------------------------
1 files changed, 57 insertions(+), 72 deletions(-)
diff --git a/kernel/sound/soc/tegra/tegra_asoc_utils.c b/kernel/sound/soc/tegra/tegra_asoc_utils.c
index 1be311c..587f62a 100644
--- a/kernel/sound/soc/tegra/tegra_asoc_utils.c
+++ b/kernel/sound/soc/tegra/tegra_asoc_utils.c
@@ -1,23 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra_asoc_utils.c - Harmony machine ASoC driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (C) 2010,2012 - NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
*/
#include <linux/clk.h>
@@ -74,8 +60,6 @@
data->set_mclk = 0;
clk_disable_unprepare(data->clk_cdev1);
- clk_disable_unprepare(data->clk_pll_a_out0);
- clk_disable_unprepare(data->clk_pll_a);
err = clk_set_rate(data->clk_pll_a, new_baseclock);
if (err) {
@@ -90,18 +74,6 @@
}
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
-
- err = clk_prepare_enable(data->clk_pll_a);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a: %d\n", err);
- return err;
- }
-
- err = clk_prepare_enable(data->clk_pll_a_out0);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
- return err;
- }
err = clk_prepare_enable(data->clk_cdev1);
if (err) {
@@ -123,8 +95,6 @@
int err;
clk_disable_unprepare(data->clk_cdev1);
- clk_disable_unprepare(data->clk_pll_a_out0);
- clk_disable_unprepare(data->clk_pll_a);
/*
* AC97 rate is fixed at 24.576MHz and is used for both the host
@@ -144,18 +114,6 @@
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
- err = clk_prepare_enable(data->clk_pll_a);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a: %d\n", err);
- return err;
- }
-
- err = clk_prepare_enable(data->clk_pll_a_out0);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
- return err;
- }
-
err = clk_prepare_enable(data->clk_cdev1);
if (err) {
dev_err(data->dev, "Can't enable cdev1: %d\n", err);
@@ -172,6 +130,7 @@
int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
struct device *dev)
{
+ struct clk *clk_out_1, *clk_extern1;
int ret;
data->dev = dev;
@@ -189,51 +148,77 @@
return -EINVAL;
}
- data->clk_pll_a = clk_get(dev, "pll_a");
+ data->clk_pll_a = devm_clk_get(dev, "pll_a");
if (IS_ERR(data->clk_pll_a)) {
dev_err(data->dev, "Can't retrieve clk pll_a\n");
- ret = PTR_ERR(data->clk_pll_a);
- goto err;
+ return PTR_ERR(data->clk_pll_a);
}
- data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
+ data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
if (IS_ERR(data->clk_pll_a_out0)) {
dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
- ret = PTR_ERR(data->clk_pll_a_out0);
- goto err_put_pll_a;
+ return PTR_ERR(data->clk_pll_a_out0);
}
- data->clk_cdev1 = clk_get(dev, "mclk");
+ data->clk_cdev1 = devm_clk_get(dev, "mclk");
if (IS_ERR(data->clk_cdev1)) {
dev_err(data->dev, "Can't retrieve clk cdev1\n");
- ret = PTR_ERR(data->clk_cdev1);
- goto err_put_pll_a_out0;
+ return PTR_ERR(data->clk_cdev1);
}
- ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
- if (ret)
- goto err_put_cdev1;
+ /*
+ * If clock parents are not set in DT, configure here to use clk_out_1
+ * as mclk and extern1 as parent for Tegra30 and higher.
+ */
+ if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
+ data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
+ dev_warn(data->dev,
+ "Configuring clocks for a legacy device-tree\n");
+ dev_warn(data->dev,
+ "Please update DT to use assigned-clock-parents\n");
+ clk_extern1 = devm_clk_get(dev, "extern1");
+ if (IS_ERR(clk_extern1)) {
+ dev_err(data->dev, "Can't retrieve clk extern1\n");
+ return PTR_ERR(clk_extern1);
+ }
+
+ ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
+ if (ret < 0) {
+ dev_err(data->dev,
+ "Set parent failed for clk extern1\n");
+ return ret;
+ }
+
+ clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
+ if (IS_ERR(clk_out_1)) {
+ dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
+ return PTR_ERR(clk_out_1);
+ }
+
+ ret = clk_set_parent(clk_out_1, clk_extern1);
+ if (ret < 0) {
+ dev_err(data->dev,
+ "Set parent failed for pmc_clk_out_1\n");
+ return ret;
+ }
+
+ data->clk_cdev1 = clk_out_1;
+ }
+
+ /*
+ * FIXME: There is some unknown dependency between audio mclk disable
+ * and suspend-resume functionality on Tegra30, although audio mclk is
+ * only needed for audio.
+ */
+ ret = clk_prepare_enable(data->clk_cdev1);
+ if (ret) {
+ dev_err(data->dev, "Can't enable cdev1: %d\n", ret);
+ return ret;
+ }
return 0;
-
-err_put_cdev1:
- clk_put(data->clk_cdev1);
-err_put_pll_a_out0:
- clk_put(data->clk_pll_a_out0);
-err_put_pll_a:
- clk_put(data->clk_pll_a);
-err:
- return ret;
}
EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
-
-void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
-{
- clk_put(data->clk_cdev1);
- clk_put(data->clk_pll_a_out0);
- clk_put(data->clk_pll_a);
-}
-EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra ASoC utility code");
--
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