From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/sound/soc/stm/stm32_sai.h | 71 +++++++++++++++++++++++------------
1 files changed, 47 insertions(+), 24 deletions(-)
diff --git a/kernel/sound/soc/stm/stm32_sai.h b/kernel/sound/soc/stm/stm32_sai.h
index f254221..33e4bff 100644
--- a/kernel/sound/soc/stm/stm32_sai.h
+++ b/kernel/sound/soc/stm/stm32_sai.h
@@ -1,19 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* STM32 ALSA SoC Digital Audio Interface (SAI) driver.
*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
- *
- * License terms: GPL V2.0.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
- * details.
*/
#include <linux/bitfield.h>
@@ -36,6 +26,12 @@
/* Sub-block A registers, relative to sub-block A address */
#define STM_SAI_PDMCR_REGX 0x40
#define STM_SAI_PDMLY_REGX 0x44
+
+/* Hardware configuration registers */
+#define STM_SAI_HWCFGR 0x3F0
+#define STM_SAI_VERR 0x3F4
+#define STM_SAI_IDR 0x3F8
+#define STM_SAI_SIDR 0x3FC
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_SHIFT 0
@@ -82,7 +78,7 @@
#define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT)
#define SAI_XCR1_MCKDIV_SHIFT 20
-#define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6)
+#define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6)
#define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
SAI_XCR1_MCKDIV_SHIFT)
#define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT)
@@ -90,6 +86,9 @@
#define SAI_XCR1_OSR_SHIFT 26
#define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
+
+#define SAI_XCR1_MCKEN_SHIFT 27
+#define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT)
/******************* Bit definition for SAI_XCR2 register *******************/
#define SAI_XCR2_FTH_SHIFT 0
@@ -231,8 +230,33 @@
#define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)
#define SAI_PDMDLY_4R_WIDTH 3
-#define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4)
-#define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7)
+/* Registers below apply to SAI version 2.1 and more */
+
+/* Bit definition for SAI_HWCFGR register */
+#define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0)
+#define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8)
+#define SAI_HWCFGR_REGOUT GENMASK(19, 12)
+
+/* Bit definition for SAI_VERR register */
+#define SAI_VERR_MIN_MASK GENMASK(3, 0)
+#define SAI_VERR_MAJ_MASK GENMASK(7, 4)
+
+/* Bit definition for SAI_IDR register */
+#define SAI_IDR_ID_MASK GENMASK(31, 0)
+
+/* Bit definition for SAI_SIDR register */
+#define SAI_SIDR_ID_MASK GENMASK(31, 0)
+
+#define SAI_IPIDR_NUMBER 0x00130031
+
+/* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
+#define STM_SAI_STM32F4 BIT(4)
+/* Dummy version number for H7 socs and next */
+#define STM_SAI_STM32H7 0x0
+
+#define STM_SAI_IS_F4(ip) ((ip)->conf.version == STM_SAI_STM32F4)
+#define STM_SAI_HAS_SPDIF_PDM(ip)\
+ ((ip)->pdata->conf.has_spdif_pdm)
enum stm32_sai_syncout {
STM_SAI_SYNC_OUT_NONE,
@@ -240,19 +264,16 @@
STM_SAI_SYNC_OUT_B,
};
-enum stm32_sai_version {
- SAI_STM32F4,
- SAI_STM32H7
-};
-
/**
* struct stm32_sai_conf - SAI configuration
* @version: SAI version
- * @has_spdif: SAI S/PDIF support flag
+ * @fifo_size: SAI fifo size as words number
+ * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
*/
struct stm32_sai_conf {
- int version;
- bool has_spdif;
+ u32 version;
+ u32 fifo_size;
+ bool has_spdif_pdm;
};
/**
@@ -262,9 +283,10 @@
* @pclk: SAI bus clock
* @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
* @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
- * @version: SOC version
+ * @conf: SAI hardware capabitilites
* @irq: SAI interrupt line
* @set_sync: pointer to synchro mode configuration callback
+ * @gcr: SAI Global Configuration Register
*/
struct stm32_sai_data {
struct platform_device *pdev;
@@ -272,8 +294,9 @@
struct clk *pclk;
struct clk *clk_x8k;
struct clk *clk_x11k;
- struct stm32_sai_conf *conf;
+ struct stm32_sai_conf conf;
int irq;
int (*set_sync)(struct stm32_sai_data *sai,
struct device_node *np_provider, int synco, int synci);
+ u32 gcr;
};
--
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