From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/drivers/rk_nand/rk_ftl_arm_v7.S | 33712 ++++++++++++++++++++++++++++++-----------------------------
1 files changed, 17,122 insertions(+), 16,590 deletions(-)
diff --git a/kernel/drivers/rk_nand/rk_ftl_arm_v7.S b/kernel/drivers/rk_nand/rk_ftl_arm_v7.S
index 65ad9ed..da6f8a9 100644
--- a/kernel/drivers/rk_nand/rk_ftl_arm_v7.S
+++ b/kernel/drivers/rk_nand/rk_ftl_arm_v7.S
@@ -5,10 +5,9 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- * date: 2020-09-23
+ * date: 2021-07-26
*/
.arch armv7-a
- .fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
@@ -17,139 +16,246 @@
.eabi_attribute 26, 2
.eabi_attribute 30, 4
.eabi_attribute 34, 1
- .eabi_attribute 18, 4
- .file "rk_ftl_arm_v7.S"
-#APP
+ .file "rk_ftl_arm_v7.c"
.syntax unified
.text
.align 2
+ .fpu softvfp
+ .type ndelay, %function
+ndelay:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ @ link register save eliminated.
+ ldr r3, .L2
+ add r0, r0, #996
+ add r0, r0, #3
+ umull r0, r1, r0, r3
+ ldr r3, .L2+4
+ ldr r3, [r3, #8]
+ lsr r0, r1, #6
+ bx r3 @ indirect register sibling call
+.L3:
+ .align 2
+.L2:
+ .word 274877907
+ .word arm_delay_ops
+ .fnend
+ .size ndelay, .-ndelay
+ .align 2
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type flash_read_ecc, %function
+flash_read_ecc:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ ldr r3, .L6
+ push {r4, lr}
+ .save {r4, lr}
+ ldr r4, [r3, r0, lsl #3]
+ add r3, r3, r0, lsl #3
+ mov r0, #80
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ add r4, r4, r3, lsl #8
+ mov r3, #122
+ str r3, [r4, #2056]
+ bl ndelay
+ ldr r3, [r4, #2048]
+ ldr r0, [r4, #2048]
+ and r3, r3, #15
+ and r0, r0, #15
+ cmp r0, r3
+ movcc r0, r3
+ ldr r3, [r4, #2048]
+ and r3, r3, #15
+ cmp r3, r0
+ movcc r3, r0
+ ldr r0, [r4, #2048]
+ and r0, r0, #15
+ cmp r0, r3
+ movcc r0, r3
+ pop {r4, pc}
+.L7:
+ .align 2
+.L6:
+ .word .LANCHOR0
+ .fnend
+ .size flash_read_ecc, .-flash_read_ecc
+ .align 2
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type ftl_set_blk_mode.part.9, %function
+ftl_set_blk_mode.part.9:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ @ link register save eliminated.
+ ldr r3, .L9
+ lsr r1, r0, #5
+ mov ip, #1
+ and r0, r0, #31
+ ldr r2, [r3, #32]
+ ldr r3, [r2, r1, lsl #2]
+ orr r0, r3, ip, lsl r0
+ str r0, [r2, r1, lsl #2]
+ bx lr
+.L10:
+ .align 2
+.L9:
+ .word .LANCHOR0
+ .fnend
+ .size ftl_set_blk_mode.part.9, .-ftl_set_blk_mode.part.9
+ .align 2
.global FlashMemCmp8
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashMemCmp8, %function
FlashMemCmp8:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L11
- str lr, [sp, #-4]!
- .save {lr}
- ldrb r3, [r3] @ zero_extendqisi2
+ ldr r3, .L25
+ ldrb r3, [r3, #36] @ zero_extendqisi2
cmp r3, #0
- beq .L4
+ beq .L20
ldrb r3, [r1, #1] @ zero_extendqisi2
ldrb ip, [r0, #1] @ zero_extendqisi2
cmp ip, r3
movne r3, #0
- beq .L8
-.L4:
+ bne .L20
+.L24:
+ mov r0, #0
+ bx lr
+.L14:
cmp r3, r2
- beq .L8
+ bne .L16
+ mov r0, #0
+ ldr pc, [sp], #4
+.L20:
+ cmp r3, r2
+ beq .L24
+ str lr, [sp, #-4]!
+ .save {lr}
+.L16:
ldrb lr, [r0, r3] @ zero_extendqisi2
ldrb ip, [r1, r3] @ zero_extendqisi2
add r3, r3, #1
cmp lr, ip
- beq .L4
+ beq .L14
mov r0, r3
ldr pc, [sp], #4
-.L8:
- mov r0, #0
- ldr pc, [sp], #4
-.L12:
+.L26:
.align 2
-.L11:
+.L25:
.word .LANCHOR0
.fnend
.size FlashMemCmp8, .-FlashMemCmp8
.align 2
.global FlashRsvdBlkChk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashRsvdBlkChk, %function
FlashRsvdBlkChk:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L14
- ldrb r2, [r3, #1] @ zero_extendqisi2
- ldr r3, [r3, #4]
- mul r3, r3, r2
- cmp r1, r3
- movcs r2, #0
- movcc r2, #1
+ ldr r2, .L28
+ ldrb ip, [r2, #37] @ zero_extendqisi2
+ ldr r3, [r2, #40]
+ mul r3, r3, ip
+ cmp r3, r1
+ movls r2, #0
+ movhi r2, #1
cmp r0, #0
movne r2, #0
eor r0, r2, #1
bx lr
-.L15:
+.L29:
.align 2
-.L14:
+.L28:
.word .LANCHOR0
.fnend
.size FlashRsvdBlkChk, .-FlashRsvdBlkChk
.align 2
.global FlashGetRandomizer
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashGetRandomizer, %function
FlashGetRandomizer:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
and r3, r1, #127
- ldr r2, .L25
- stmfd sp!, {r4, lr}
+ ldr r2, .L39
+ lsl r3, r3, #1
+ push {r4, lr}
.save {r4, lr}
- mov r3, r3, asl #1
ldrh r4, [r2, r3]
- ldr r3, .L25+4
- ldrb r3, [r3, #8] @ zero_extendqisi2
+ ldr r3, .L39+4
+ ldrb r3, [r3, #44] @ zero_extendqisi2
cmp r3, #0
- beq .L17
+ beq .L30
bl FlashRsvdBlkChk
cmp r0, #0
orrne r4, r4, #-1073741824
-.L17:
+.L30:
mov r0, r4
- ldmfd sp!, {r4, pc}
-.L26:
+ pop {r4, pc}
+.L40:
.align 2
-.L25:
+.L39:
.word .LANCHOR1
.word .LANCHOR0
.fnend
.size FlashGetRandomizer, .-FlashGetRandomizer
.align 2
.global FlashSetRandomizer
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashSetRandomizer, %function
FlashSetRandomizer:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
+ ldr r2, .L50
and r3, r1, #127
- ldr r2, .L36
- stmfd sp!, {r4, r5, r6, lr}
+ lsl r3, r3, #1
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- mov r3, r3, asl #1
mov r6, r0
ldrh r5, [r2, r3]
- ldr r3, .L36+4
- ldrb r2, [r3, #8] @ zero_extendqisi2
+ ldr r3, .L50+4
+ ldrb r2, [r3, #44] @ zero_extendqisi2
mov r4, r3
cmp r2, #0
- beq .L28
+ beq .L42
bl FlashRsvdBlkChk
cmp r0, #0
orrne r5, r5, #-1073741824
-.L28:
- add r4, r4, r6, asl #3
- ldr r3, [r4, #12]
+.L42:
+ ldr r3, [r4, r6, lsl #3]
str r5, [r3, #336]
- ldmfd sp!, {r4, r5, r6, pc}
-.L37:
+ pop {r4, r5, r6, pc}
+.L51:
.align 2
-.L36:
+.L50:
.word .LANCHOR1
.word .LANCHOR0
.fnend
.size FlashSetRandomizer, .-FlashSetRandomizer
.align 2
.global FlashBlockAlignInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashBlockAlignInit, %function
FlashBlockAlignInit:
.fnstart
@@ -157,45 +263,49 @@
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
cmp r0, #512
- ldr r3, .L44
+ ldr r3, .L58
movhi r2, #1024
- bhi .L43
+ bhi .L57
cmp r0, #256
movhi r2, #512
- bhi .L43
+ bhi .L57
cmp r0, #128
- strls r0, [r3, #4]
- bxls lr
- mov r2, #256
-.L43:
- str r2, [r3, #4]
+ movhi r2, #256
+ bhi .L57
+ str r0, [r3, #40]
bx lr
-.L45:
+.L57:
+ str r2, [r3, #40]
+ bx lr
+.L59:
.align 2
-.L44:
+.L58:
.word .LANCHOR0
.fnend
.size FlashBlockAlignInit, .-FlashBlockAlignInit
.align 2
.global FlashReadCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadCmd, %function
FlashReadCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L49
+ ldr ip, .L63
str lr, [sp, #-4]!
.save {lr}
- add r3, ip, r0, asl #3
- ldr ip, [ip, #44]
- ldr r2, [r3, #12]
- ldrb r3, [r3, #16] @ zero_extendqisi2
+ add r2, ip, r0, lsl #3
+ ldr r3, [ip, r0, lsl #3]
+ ldr ip, [ip, #48]
+ ldrb r2, [r2, #4] @ zero_extendqisi2
ldrb ip, [ip, #7] @ zero_extendqisi2
- mov r3, r3, asl #8
+ lsl r2, r2, #8
cmp ip, #1
- addeq ip, r2, r3
- add r3, r2, r3
+ addeq ip, r3, r2
moveq lr, #38
+ add r3, r3, r2
mov r2, #0
streq lr, [ip, #2056]
str r2, [r3, #2056]
@@ -203,41 +313,44 @@
str r2, [r3, #2052]
uxtb r2, r1
str r2, [r3, #2052]
- mov r2, r1, lsr #8
+ lsr r2, r1, #8
str r2, [r3, #2052]
- mov r2, r1, lsr #16
+ lsr r2, r1, #16
str r2, [r3, #2052]
mov r2, #48
str r2, [r3, #2056]
ldr lr, [sp], #4
b FlashSetRandomizer
-.L50:
+.L64:
.align 2
-.L49:
+.L63:
.word .LANCHOR0
.fnend
.size FlashReadCmd, .-FlashReadCmd
.align 2
.global FlashReadDpDataOutCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadDpDataOutCmd, %function
FlashReadDpDataOutCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L56
- stmfd sp!, {r4, lr}
+ ldr ip, .L70
+ push {r4, lr}
.save {r4, lr}
- add r3, ip, r0, asl #3
- ldrb ip, [ip, #64] @ zero_extendqisi2
uxtb r4, r1
- ldr r2, [r3, #12]
- mov lr, r1, lsr #8
- ldrb r3, [r3, #16] @ zero_extendqisi2
+ lsr lr, r1, #8
+ add r2, ip, r0, lsl #3
+ ldr r3, [ip, r0, lsl #3]
+ ldrb ip, [ip, #68] @ zero_extendqisi2
+ ldrb r2, [r2, #4] @ zero_extendqisi2
cmp ip, #1
- mov ip, r1, lsr #16
- mov r3, r3, asl #8
- add r3, r2, r3
- bne .L52
+ lsr ip, r1, #16
+ lsl r2, r2, #8
+ add r3, r3, r2
+ bne .L66
mov r2, #6
str r2, [r3, #2056]
mov r2, #0
@@ -246,8 +359,12 @@
str r4, [r3, #2052]
str lr, [r3, #2052]
str ip, [r3, #2052]
- b .L55
-.L52:
+.L69:
+ mov r2, #224
+ str r2, [r3, #2056]
+ pop {r4, lr}
+ b FlashSetRandomizer
+.L66:
mov r2, #0
str r2, [r3, #2056]
str r2, [r3, #2052]
@@ -259,31 +376,31 @@
str ip, [r3, #2056]
str r2, [r3, #2052]
str r2, [r3, #2052]
-.L55:
- mov r2, #224
- str r2, [r3, #2056]
- ldmfd sp!, {r4, lr}
- b FlashSetRandomizer
-.L57:
+ b .L69
+.L71:
.align 2
-.L56:
+.L70:
.word .LANCHOR0
.fnend
.size FlashReadDpDataOutCmd, .-FlashReadDpDataOutCmd
.align 2
.global FlashProgFirstCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgFirstCmd, %function
FlashProgFirstCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- @ link register save eliminated.
- ldr ip, .L59
- mov r2, r1, lsr #16
- add ip, ip, r0, asl #3
- ldr r3, [ip, #12]
- ldrb ip, [ip, #16] @ zero_extendqisi2
- add r3, r3, ip, asl #8
+ ldr ip, .L74
+ lsr r2, r1, #16
+ str lr, [sp, #-4]!
+ .save {lr}
+ ldr r3, [ip, r0, lsl #3]
+ add ip, ip, r0, lsl #3
+ ldrb ip, [ip, #4] @ zero_extendqisi2
+ add r3, r3, ip, lsl #8
mov ip, #128
str ip, [r3, #2056]
mov ip, #0
@@ -291,176 +408,225 @@
str ip, [r3, #2052]
uxtb ip, r1
str ip, [r3, #2052]
- mov ip, r1, lsr #8
+ lsr ip, r1, #8
str ip, [r3, #2052]
str r2, [r3, #2052]
+ ldr lr, [sp], #4
b FlashSetRandomizer
-.L60:
+.L75:
.align 2
-.L59:
+.L74:
.word .LANCHOR0
.fnend
.size FlashProgFirstCmd, .-FlashProgFirstCmd
.align 2
.global FlashEraseCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashEraseCmd, %function
FlashEraseCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
+ ldr ip, .L82
+ cmp r2, #0
str lr, [sp, #-4]!
.save {lr}
- cmp r2, #0
- ldr lr, .L67
- add r0, lr, r0, asl #3
- ldrb r3, [r0, #16] @ zero_extendqisi2
- ldr ip, [r0, #12]
- mov r3, r3, asl #8
- beq .L62
- add r2, ip, r3
- mov r0, #96
- str r0, [r2, #2056]
- uxtb r0, r1
- str r0, [r2, #2052]
- mov r0, r1, lsr #8
- str r0, [r2, #2052]
- mov r0, r1, lsr #16
- str r0, [r2, #2052]
- ldr r2, [lr, #4]
+ ldr r3, [ip, r0, lsl #3]
+ add r0, ip, r0, lsl #3
+ ldrb r0, [r0, #4] @ zero_extendqisi2
+ lsl r0, r0, #8
+ beq .L77
+ add r2, r3, r0
+ mov lr, #96
+ str lr, [r2, #2056]
+ uxtb lr, r1
+ str lr, [r2, #2052]
+ lsr lr, r1, #8
+ str lr, [r2, #2052]
+ lsr lr, r1, #16
+ str lr, [r2, #2052]
+ ldr r2, [ip, #40]
add r1, r1, r2
-.L62:
- add r3, ip, r3
+.L77:
+ add r3, r3, r0
mov r2, #96
str r2, [r3, #2056]
uxtb r2, r1
str r2, [r3, #2052]
- mov r2, r1, lsr #8
- mov r1, r1, lsr #16
+ lsr r2, r1, #8
+ lsr r1, r1, #16
str r2, [r3, #2052]
- str r1, [r3, #2052]
mov r2, #208
+ str r1, [r3, #2052]
str r2, [r3, #2056]
ldr pc, [sp], #4
-.L68:
+.L83:
.align 2
-.L67:
+.L82:
.word .LANCHOR0
.fnend
.size FlashEraseCmd, .-FlashEraseCmd
.align 2
.global FlashProgDpSecondCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgDpSecondCmd, %function
FlashProgDpSecondCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L71
- mov r2, r1, lsr #16
- str lr, [sp, #-4]!
- .save {lr}
- add lr, ip, r0, asl #3
- ldrb ip, [ip, #59] @ zero_extendqisi2
- ldr r3, [lr, #12]
- ldrb lr, [lr, #16] @ zero_extendqisi2
- add r3, r3, lr, asl #8
+ push {r4, lr}
+ .save {r4, lr}
+ lsr r2, r1, #16
+ ldr lr, .L86
+ ldr r3, [lr, r0, lsl #3]
+ add ip, lr, r0, lsl #3
+ ldrb r4, [ip, #4] @ zero_extendqisi2
+ ldrb ip, [lr, #63] @ zero_extendqisi2
+ add r3, r3, r4, lsl #8
str ip, [r3, #2056]
mov ip, #0
str ip, [r3, #2052]
str ip, [r3, #2052]
uxtb ip, r1
str ip, [r3, #2052]
- mov ip, r1, lsr #8
+ lsr ip, r1, #8
str ip, [r3, #2052]
str r2, [r3, #2052]
- ldr lr, [sp], #4
+ pop {r4, lr}
b FlashSetRandomizer
-.L72:
+.L87:
.align 2
-.L71:
+.L86:
.word .LANCHOR0
.fnend
.size FlashProgDpSecondCmd, .-FlashProgDpSecondCmd
.align 2
.global FlashProgSecondCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgSecondCmd, %function
FlashProgSecondCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- ldr r3, .L75
- add r0, r3, r0, asl #3
- ldr r3, .L75+4
- ldrb r5, [r0, #16] @ zero_extendqisi2
- ldr r4, [r0, #12]
+ ldr r3, .L90
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r4, [r3, r0, lsl #3]
+ add r3, r3, r0, lsl #3
+ ldr r0, .L90+4
+ ldrb r5, [r3, #4] @ zero_extendqisi2
+ ldr r3, .L90+8
+ add r4, r4, r5, lsl #8
ldr r3, [r3, #4]
- add r4, r4, r5, asl #8
- ldr r0, .L75+8
blx r3
mov r3, #16
str r3, [r4, #2056]
- ldmfd sp!, {r3, r4, r5, pc}
-.L76:
+ pop {r4, r5, r6, pc}
+.L91:
.align 2
-.L75:
+.L90:
.word .LANCHOR0
+ .word 64424500
.word arm_delay_ops
- .word 214748300
.fnend
.size FlashProgSecondCmd, .-FlashProgSecondCmd
.align 2
.global FlashProgDpFirstCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgDpFirstCmd, %function
FlashProgDpFirstCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L78
- add r0, r2, r0, asl #3
- ldrb r2, [r2, #58] @ zero_extendqisi2
- ldrb r1, [r0, #16] @ zero_extendqisi2
- ldr r3, [r0, #12]
- add r3, r3, r1, asl #8
+ ldr r2, .L93
+ ldr r3, [r2, r0, lsl #3]
+ add r0, r2, r0, lsl #3
+ ldrb r2, [r2, #62] @ zero_extendqisi2
+ ldrb r1, [r0, #4] @ zero_extendqisi2
+ add r3, r3, r1, lsl #8
str r2, [r3, #2056]
bx lr
-.L79:
+.L94:
.align 2
-.L78:
+.L93:
.word .LANCHOR0
.fnend
.size FlashProgDpFirstCmd, .-FlashProgDpFirstCmd
.align 2
+ .global FlashReadStatus
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type FlashReadStatus, %function
+FlashReadStatus:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ ldr r3, .L97
+ mov r2, #112
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r5, [r3, r0, lsl #3]
+ add r3, r3, r0, lsl #3
+ mov r0, #80
+ ldrb r4, [r3, #4] @ zero_extendqisi2
+ add r3, r5, r4, lsl #8
+ add r4, r4, #8
+ str r2, [r3, #2056]
+ bl ndelay
+ ldr r0, [r5, r4, lsl #8]
+ pop {r4, r5, r6, pc}
+.L98:
+ .align 2
+.L97:
+ .word .LANCHOR0
+ .fnend
+ .size FlashReadStatus, .-FlashReadStatus
+ .align 2
.global js_hash
+ .syntax unified
+ .arm
+ .fpu softvfp
.type js_hash, %function
js_hash:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L84
+ ldr r3, .L102
add r1, r0, r1
-.L81:
+.L100:
cmp r0, r1
- beq .L83
- mov r2, r3, asl #5
- ldrb ip, [r0], #1 @ zero_extendqisi2
- add r2, r2, r3, lsr #2
- add r2, r2, ip
- eor r3, r3, r2
- b .L81
-.L83:
+ bne .L101
mov r0, r3
bx lr
-.L85:
+.L101:
+ lsr r2, r3, #2
+ ldrb ip, [r0], #1 @ zero_extendqisi2
+ add r2, r2, r3, lsl #5
+ add r2, r2, ip
+ eor r3, r3, r2
+ b .L100
+.L103:
.align 2
-.L84:
+.L102:
.word 1204201446
.fnend
.size js_hash, .-js_hash
.align 2
.global FlashLoadIdbInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashLoadIdbInfo, %function
FlashLoadIdbInfo:
.fnstart
@@ -473,6 +639,9 @@
.size FlashLoadIdbInfo, .-FlashLoadIdbInfo
.align 2
.global FlashPrintInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashPrintInfo, %function
FlashPrintInfo:
.fnstart
@@ -483,148 +652,350 @@
.fnend
.size FlashPrintInfo, .-FlashPrintInfo
.align 2
+ .global ToshibaSetRRPara
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type ToshibaSetRRPara, %function
+ToshibaSetRRPara:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ add r9, r1, r1, lsl #2
+ ldr r7, .L114
+ mov r6, r0
+ mov r5, #0
+ add r7, r1, r7
+.L107:
+ ldr r8, .L114+4
+ ldrb r3, [r8, #85] @ zero_extendqisi2
+ cmp r5, r3
+ bcc .L111
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L111:
+ ldr r4, .L114+8
+ mov r3, #85
+ str r3, [r6, #8]
+ mov r0, #200
+ ldrsb r3, [r5, r4]
+ str r3, [r6, #4]
+ bl ndelay
+ ldrb r3, [r8, #84] @ zero_extendqisi2
+ cmp r3, #34
+ addeq r3, r5, r9
+ addeq r4, r4, r3
+ ldrsbeq r3, [r4, #5]
+ beq .L113
+ cmp r3, #35
+ addeq r3, r5, r9
+ ldrsbne r3, [r7]
+ addeq r4, r4, r3
+ ldrsbeq r3, [r4, #50]
+.L113:
+ str r3, [r6]
+ add r5, r5, #1
+ b .L107
+.L115:
+ .align 2
+.L114:
+ .word .LANCHOR1+396
+ .word .LANCHOR0
+ .word .LANCHOR1+256
+ .fnend
+ .size ToshibaSetRRPara, .-ToshibaSetRRPara
+ .align 2
+ .global SamsungSetRRPara
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type SamsungSetRRPara, %function
+SamsungSetRRPara:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ ldr r3, .L120
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ mov r4, #0
+ ldr r8, .L120+4
+ mov r6, r0
+ mov r7, r3
+ mov r9, #161
+ add r1, r3, r1, lsl #2
+ mov r10, r4
+ add r5, r1, #3
+.L117:
+ ldrb r3, [r8, #85] @ zero_extendqisi2
+ cmp r4, r3
+ bcc .L118
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L118:
+ str r9, [r6, #8]
+ mov r0, #300
+ str r10, [r6]
+ ldrsb r3, [r7, r4]
+ add r4, r4, #1
+ str r3, [r6]
+ ldrsb r3, [r5, #1]!
+ str r3, [r6]
+ bl ndelay
+ b .L117
+.L121:
+ .align 2
+.L120:
+ .word .LANCHOR1+404
+ .word .LANCHOR0
+ .fnend
+ .size SamsungSetRRPara, .-SamsungSetRRPara
+ .align 2
.global ftl_flash_suspend
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_flash_suspend, %function
ftl_flash_suspend:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L89
- ldr r2, [r3, #80]
+ ldr r3, .L123
+ ldr r2, [r3, #88]
ldr r1, [r2]
- str r1, [r3, #84]
- ldr r1, [r2, #4]
- str r1, [r3, #88]
- ldr r1, [r2, #8]
str r1, [r3, #92]
- ldr r1, [r2, #12]
+ ldr r1, [r2, #4]
str r1, [r3, #96]
- ldr r1, [r2, #304]
+ ldr r1, [r2, #8]
str r1, [r3, #100]
- ldr r1, [r2, #308]
+ ldr r1, [r2, #12]
str r1, [r3, #104]
+ ldr r1, [r2, #304]
+ str r1, [r3, #108]
+ ldr r1, [r2, #308]
+ str r1, [r3, #112]
ldr r1, [r2, #336]
ldr r2, [r2, #344]
- str r1, [r3, #108]
- str r2, [r3, #112]
+ str r1, [r3, #116]
+ str r2, [r3, #120]
bx lr
-.L90:
+.L124:
.align 2
-.L89:
+.L123:
.word .LANCHOR0
.fnend
.size ftl_flash_suspend, .-ftl_flash_suspend
.global __aeabi_uidiv
+ .global __aeabi_uidivmod
.align 2
.global LogAddr2PhyAddr
+ .syntax unified
+ .arm
+ .fpu softvfp
.type LogAddr2PhyAddr, %function
LogAddr2PhyAddr:
.fnstart
@ args = 4, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- mov r5, r0
- ldr r0, .L97
- mov r8, r3
- ldr ip, [r5, #4]
- mov r9, r1
- mov r7, r2
- ldrh r3, [r0, #130]
- bic ip, ip, #-2147483648
- ldrh r4, [r0, #128]
- ubfx r6, ip, #10, #16
- ldrh r10, [r0, #4]
- mov fp, r0
- str ip, [sp, #4]
- smulbb r4, r4, r3
- ldrb r3, [r0] @ zero_extendqisi2
- mov r0, r6
- cmp r3, #1
- moveq r10, r10, asl #1
- uxth r4, r4
- uxtheq r10, r10
- mov r1, r4
+ mov r9, r2
+ ldr r4, .L131
+ mov fp, r3
+ mov r10, r1
+ mov r7, r0
+ ldr r5, [r0, #4]
+ ldrh r2, [r4, #136]
+ ldrh r3, [r4, #138]
+ ldrh r6, [r4, #40]
+ smulbb r3, r3, r2
+ ldrb r2, [r4, #36] @ zero_extendqisi2
+ uxth r3, r3
+ cmp r2, #1
+ lsleq r6, r6, #1
+ ubfx r2, r5, #10, #16
+ mov r1, r3
+ str r3, [sp, #4]
+ mov r0, r2
+ uxtheq r6, r6
+ str r2, [sp]
bl __aeabi_uidiv
- cmp r9, #1
- uxth r0, r0
- ldr ip, [sp, #4]
- smulbb r4, r0, r4
- rsb r6, r4, r6
- ubfx r4, ip, #0, #10
- uxth r6, r6
- bne .L93
- ldrb r3, [fp, #144] @ zero_extendqisi2
+ ldr r3, [sp, #4]
+ uxth r8, r0
+ ldr r2, [sp]
+ mov r1, r3
+ mov r0, r2
+ bl __aeabi_uidivmod
+ cmp r10, #1
+ uxth r1, r1
+ ubfx r0, r5, #0, #10
+ bne .L127
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- ldreq r3, .L97
- addeq r4, r3, r4, asl #1
- ldreqh r4, [r4, #148]
-.L93:
- add ip, fp, r0, asl #2
+ addeq r0, r4, r0, lsl #1
+ ldrheq r0, [r0, #156]
+.L127:
+ add r4, r4, r8, lsl #2
+ ldr r3, [r4, #1180]
+ mla r6, r6, r1, r3
ldrb r3, [sp, #48] @ zero_extendqisi2
- ldr r1, [ip, #1172]
cmp r3, #1
- mla r1, r10, r6, r1
- add r4, r1, r4
- str r4, [r7]
- str r0, [r8]
+ add r0, r6, r0
+ str r0, [r9]
movls r0, #0
- ldrhi r0, [r5, #4]
- ldrhi r3, [r5, #40]
+ str r8, [fp]
+ ldrhi r0, [r7, #4]
+ ldrhi r3, [r7, #40]
addhi r0, r0, #1024
- rsbhi r0, r3, r0
+ subhi r0, r0, r3
clzhi r0, r0
- movhi r0, r0, lsr #5
+ lsrhi r0, r0, #5
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L98:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L132:
.align 2
-.L97:
+.L131:
.word .LANCHOR0
.fnend
.size LogAddr2PhyAddr, .-LogAddr2PhyAddr
.align 2
+ .global FlashReadStatusEN
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type FlashReadStatusEN, %function
+FlashReadStatusEN:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ ldr r3, .L146
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r4, [r3, r0, lsl #3]
+ add r0, r3, r0, lsl #3
+ ldrb r5, [r0, #4] @ zero_extendqisi2
+ ldr r0, [r3, #48]
+ ldrb r0, [r0, #8] @ zero_extendqisi2
+ cmp r0, #2
+ mov r0, r3
+ lsl r3, r5, #8
+ movne r2, #112
+ add r5, r5, #8
+ addne r3, r4, r3
+ strne r2, [r3, #2056]
+ bne .L139
+ cmp r2, #0
+ add r3, r4, r3
+ ldrbne r2, [r0, #66] @ zero_extendqisi2
+ ldrbeq r2, [r0, #65] @ zero_extendqisi2
+ str r2, [r3, #2056]
+ ldrb r0, [r0, #67] @ zero_extendqisi2
+ cmp r0, #0
+ movne r2, #0
+ addne ip, r4, r5, lsl #8
+ bne .L138
+.L139:
+ mov r0, #80
+ bl ndelay
+ ldr r0, [r4, r5, lsl #8]
+ uxtb r0, r0
+ pop {r4, r5, r6, pc}
+.L140:
+ lsl r3, r2, #3
+ add r2, r2, #1
+ lsr r3, r1, r3
+ uxtb r3, r3
+ str r3, [ip, #4]
+.L138:
+ cmp r2, r0
+ bcc .L140
+ b .L139
+.L147:
+ .align 2
+.L146:
+ .word .LANCHOR0
+ .fnend
+ .size FlashReadStatusEN, .-FlashReadStatusEN
+ .align 2
+ .global FlashWaitReadyEN
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type FlashWaitReadyEN, %function
+FlashWaitReadyEN:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r4, r0
+ mov r5, r1
+ mov r6, r2
+.L149:
+ mov r2, r6
+ mov r1, r5
+ mov r0, r4
+ bl FlashReadStatusEN
+ cmp r0, #255
+ beq .L149
+ tst r0, #64
+ popne {r4, r5, r6, pc}
+ mov r1, #3
+ mov r0, #1
+ bl usleep_range
+ b .L149
+ .fnend
+ .size FlashWaitReadyEN, .-FlashWaitReadyEN
+ .align 2
.global FlashScheduleEnSet
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashScheduleEnSet, %function
FlashScheduleEnSet:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L100
- ldr r2, [r3, #1204]
- str r0, [r3, #1204]
+ ldr r3, .L156
+ ldr r2, [r3, #1212]
+ str r0, [r3, #1212]
mov r0, r2
bx lr
-.L101:
+.L157:
.align 2
-.L100:
+.L156:
.word .LANCHOR0
.fnend
.size FlashScheduleEnSet, .-FlashScheduleEnSet
.align 2
.global FlashGetPageSize
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashGetPageSize, %function
FlashGetPageSize:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L103
- ldr r3, [r3, #44]
+ ldr r3, .L159
+ ldr r3, [r3, #48]
ldrb r0, [r3, #9] @ zero_extendqisi2
bx lr
-.L104:
+.L160:
.align 2
-.L103:
+.L159:
.word .LANCHOR0
.fnend
.size FlashGetPageSize, .-FlashGetPageSize
.align 2
.global NandcReadDontCaseBusyEn
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcReadDontCaseBusyEn, %function
NandcReadDontCaseBusyEn:
.fnstart
@@ -636,107 +1007,122 @@
.size NandcReadDontCaseBusyEn, .-NandcReadDontCaseBusyEn
.align 2
.global NandcGetChipIf
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcGetChipIf, %function
NandcGetChipIf:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L107
- add r0, r3, r0, asl #3
- ldrb r2, [r0, #16] @ zero_extendqisi2
- ldr r0, [r0, #12]
- add r2, r2, #8
- add r0, r0, r2, asl #8
+ ldr r2, .L163
+ add r3, r2, r0, lsl #3
+ ldr r0, [r2, r0, lsl #3]
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ add r3, r3, #8
+ add r0, r0, r3, lsl #8
bx lr
-.L108:
+.L164:
.align 2
-.L107:
+.L163:
.word .LANCHOR0
.fnend
.size NandcGetChipIf, .-NandcGetChipIf
.align 2
.global NandcSetDdrPara
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSetDdrPara, %function
NandcSetDdrPara:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L110
- ldr r2, [r3, #80]
- mov r3, r0, asl #8
- orr r0, r3, r0, asl #16
- orr r3, r0, #1
- str r3, [r2, #304]
+ ldr r3, .L166
+ ldr r2, [r3, #88]
+ lsl r3, r0, #8
+ orr r0, r3, r0, lsl #16
+ orr r0, r0, #1
+ str r0, [r2, #304]
bx lr
-.L111:
+.L167:
.align 2
-.L110:
+.L166:
.word .LANCHOR0
.fnend
.size NandcSetDdrPara, .-NandcSetDdrPara
.align 2
.global NandcSetDdrDiv
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSetDdrDiv, %function
NandcSetDdrDiv:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L113
+ ldr r3, .L169
orr r0, r0, #16640
- ldr r3, [r3, #80]
+ ldr r3, [r3, #88]
str r0, [r3, #344]
bx lr
-.L114:
+.L170:
.align 2
-.L113:
+.L169:
.word .LANCHOR0
.fnend
.size NandcSetDdrDiv, .-NandcSetDdrDiv
.align 2
.global NandcSetDdrMode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSetDdrMode, %function
NandcSetDdrMode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L118
+ ldr r3, .L174
cmp r0, #0
- ldr r2, [r3, #80]
+ ldr r2, [r3, #88]
ldr r3, [r2]
bfieq r3, r0, #13, #1
orrne r3, r3, #253952
str r3, [r2]
bx lr
-.L119:
+.L175:
.align 2
-.L118:
+.L174:
.word .LANCHOR0
.fnend
.size NandcSetDdrMode, .-NandcSetDdrMode
.align 2
.global NandcSetMode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSetMode, %function
NandcSetMode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L127
+ ldr r3, .L183
ands r1, r0, #6
- ldr r2, [r3, #80]
+ ldr r2, [r3, #88]
ldr r3, [r2]
bfieq r3, r1, #13, #1
- beq .L123
- orr r3, r3, #24576
+ beq .L179
movw r1, #8322
- bfc r3, #15, #1
+ orr r3, r3, #24576
str r1, [r2, #344]
+ bfc r3, #15, #1
+ ldr r1, .L183+4
orr r3, r3, #196608
- ldr r1, .L127+4
tst r0, #4
orrne r3, r3, #32768
str r1, [r2, #304]
@@ -744,642 +1130,416 @@
str r1, [r2, #308]
mov r1, #39
str r1, [r2, #308]
-.L123:
+.L179:
str r3, [r2]
mov r0, #0
bx lr
-.L128:
+.L184:
.align 2
-.L127:
+.L183:
.word .LANCHOR0
.word 1052675
.fnend
.size NandcSetMode, .-NandcSetMode
.align 2
.global NandcFlashCs
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcFlashCs, %function
NandcFlashCs:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L130
- add r0, r2, r0, asl #3
+ ldr r3, .L186
mov r2, #1
- ldr r1, [r0, #12]
- ldrb r0, [r0, #16] @ zero_extendqisi2
+ ldr r1, [r3, r0, lsl #3]
+ add r0, r3, r0, lsl #3
+ ldrb r0, [r0, #4] @ zero_extendqisi2
ldr r3, [r1]
- mov r2, r2, asl r0
+ lsl r2, r2, r0
bfi r3, r2, #0, #8
str r3, [r1]
bx lr
-.L131:
+.L187:
.align 2
-.L130:
+.L186:
.word .LANCHOR0
.fnend
.size NandcFlashCs, .-NandcFlashCs
.align 2
.global NandcFlashDeCs
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcFlashDeCs, %function
NandcFlashDeCs:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L133
- add r0, r3, r0, asl #3
- ldr r2, [r0, #12]
+ ldr r3, .L189
+ ldr r2, [r3, r0, lsl #3]
ldr r3, [r2]
bfc r3, #0, #8
bfc r3, #17, #1
str r3, [r2]
bx lr
-.L134:
+.L190:
.align 2
-.L133:
+.L189:
.word .LANCHOR0
.fnend
.size NandcFlashDeCs, .-NandcFlashDeCs
.align 2
- .global NandcDelayns
- .type NandcDelayns, %function
-NandcDelayns:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
- add r0, r0, #996
- ldr r3, .L137
- add r0, r0, #3
- umull r0, r1, r0, r3
- ldr r3, .L137+4
- ldr r3, [r3, #8]
- mov r0, r1, lsr #6
- blx r3
- mov r0, #0
- ldmfd sp!, {r3, pc}
-.L138:
- .align 2
-.L137:
- .word 274877907
- .word arm_delay_ops
- .fnend
- .size NandcDelayns, .-NandcDelayns
- .align 2
- .global FlashReadStatus
- .type FlashReadStatus, %function
-FlashReadStatus:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r2, #112
- ldr r3, .L141
- add r0, r3, r0, asl #3
- ldrb r4, [r0, #16] @ zero_extendqisi2
- ldr r5, [r0, #12]
- mov r0, #80
- add r3, r5, r4, asl #8
- add r4, r4, #8
- str r2, [r3, #2056]
- bl NandcDelayns
- ldr r0, [r5, r4, asl #8]
- ldmfd sp!, {r3, r4, r5, pc}
-.L142:
- .align 2
-.L141:
- .word .LANCHOR0
- .fnend
- .size FlashReadStatus, .-FlashReadStatus
- .align 2
- .global ToshibaSetRRPara
- .type ToshibaSetRRPara, %function
-ToshibaSetRRPara:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, lr}
- add r8, r1, r1, asl #2
- ldr r9, .L153
- mov r5, r0
- ldr r7, .L153+4
- mov r6, r1
- add r10, r9, #256
- mov r4, #0
-.L144:
- ldrb r3, [r7, #1209] @ zero_extendqisi2
- cmp r4, r3
- bcs .L152
- mov r3, #85
- str r3, [r5, #8]
- ldrsb r3, [r4, r10]
- mov r0, #200
- str r3, [r5, #4]
- bl NandcDelayns
- ldrb r3, [r7, #1208] @ zero_extendqisi2
- cmp r3, #34
- addeq r3, r4, r8
- addeq r3, r10, r3
- beq .L151
- cmp r3, #35
- addne r3, r9, r6
- addne r3, r3, #400
- ldrnesb r3, [r3]
- bne .L150
- ldr r3, .L153+8
- add r2, r4, r8
- add r3, r3, r2
-.L151:
- ldrsb r3, [r3, #5]
-.L150:
- str r3, [r5]
- add r4, r4, #1
- b .L144
-.L152:
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L154:
- .align 2
-.L153:
- .word .LANCHOR1
- .word .LANCHOR0
- .word .LANCHOR1+304
- .fnend
- .size ToshibaSetRRPara, .-ToshibaSetRRPara
- .align 2
- .global SamsungSetRRPara
- .type SamsungSetRRPara, %function
-SamsungSetRRPara:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L160
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, lr}
- add r1, r3, r1, asl #2
- ldr r8, .L160+4
- mov r4, #0
- add r5, r1, #3
- mov r6, r0
- mov r7, r3
- mov r9, #161
- mov r10, r4
-.L156:
- ldrb r3, [r8, #1209] @ zero_extendqisi2
- cmp r4, r3
- bcs .L159
- str r9, [r6, #8]
- mov r0, #300
- str r10, [r6]
- ldrsb r3, [r7, r4]
- add r4, r4, #1
- str r3, [r6]
- ldrsb r3, [r5, #1]!
- str r3, [r6]
- bl NandcDelayns
- b .L156
-.L159:
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L161:
- .align 2
-.L160:
- .word .LANCHOR1+408
- .word .LANCHOR0
- .fnend
- .size SamsungSetRRPara, .-SamsungSetRRPara
- .align 2
.global HynixSetRRPara
+ .syntax unified
+ .arm
+ .fpu softvfp
.type HynixSetRRPara, %function
HynixSetRRPara:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- mov r6, r3
- ldr r5, .L171
- mov r9, r2
- ldr r4, .L171+4
- mov r7, r0
+ mov r6, r0
+ ldr r0, .L200
+ mov r7, r3
mov r8, r1
- ldr r3, [r5, #44]
- ldrb r2, [r3, #19] @ zero_extendqisi2
- mov r3, r0, asl #3
- cmp r2, #6
- addeq r4, r4, r0, asl #6
- addeq r4, r4, #20
- addeq r4, r4, r6, asl #2
- beq .L164
- cmp r2, #7
- bne .L165
- mov r2, #160
- mla r4, r2, r0, r4
- add r2, r6, r6, asl #2
- add r4, r4, #28
- add r4, r4, r2, asl #1
- b .L164
-.L165:
- cmp r2, #8
- addne r2, r6, r3
- addeq r2, r6, r6, asl #2
- ldreq r4, .L171+8
- addne r4, r4, r2, asl #3
- addeq r4, r4, r2
- addne r4, r4, #20
-.L164:
- add r3, r5, r3
- mov r0, r7
+ mov r10, r2
+ ldr r3, [r0, #48]
+ mov r5, r0
+ add r4, r0, #1216
+ ldrb r3, [r3, #19] @ zero_extendqisi2
+ cmp r3, #6
+ moveq r3, #20
+ addeq r3, r3, r6, lsl #6
+ addeq r3, r3, r7, lsl #2
+ beq .L199
+ cmp r3, #7
+ bne .L194
+ mov r3, #160
+ mov r2, #28
+ smlabb r2, r3, r6, r2
+ mov r3, #10
+ smlabb r3, r3, r7, r2
+.L199:
+ add r4, r4, r3
+.L193:
+ add r3, r5, r6, lsl #3
+ ldr r9, [r5, r6, lsl #3]
+ mov r0, r6
+ ldrb fp, [r3, #4] @ zero_extendqisi2
sub r8, r8, #1
- sub r4, r4, #1
- ldrb fp, [r3, #16] @ zero_extendqisi2
- ldr r10, [r3, #12]
bl NandcFlashCs
- sub ip, r9, #1
- add r9, r9, r8
- mov r3, fp, asl #8
- mov r2, #54
- add fp, r10, r3
- str r2, [fp, #2056]
-.L167:
- cmp ip, r9
- beq .L170
- ldrb r2, [ip, #1]! @ zero_extendqisi2
- mov r0, #200
- str r3, [sp, #4]
- str r2, [fp, #2052]
- str ip, [sp]
- bl NandcDelayns
- ldrsb r2, [r4, #1]!
- str r2, [fp, #2048]
- ldr r3, [sp, #4]
- ldr ip, [sp]
- b .L167
-.L170:
- add r10, r10, r3
- mov r0, r7
+ mov r3, #54
+ add r8, r10, r8
+ sub r4, r4, #1
+ lsl fp, fp, #8
+ add r0, r9, fp
+ str r3, [r0, #2056]
+ sub r3, r10, #1
+ mov r10, r0
+.L196:
+ cmp r3, r8
+ bne .L197
mov r3, #22
- add r5, r5, r7
- str r3, [r10, #2056]
+ add r9, r9, fp
+ mov r0, r6
+ str r3, [r9, #2056]
bl NandcFlashDeCs
- strb r6, [r5, #2064]
+ add r0, r5, r6
+ strb r7, [r0, #2068]
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L172:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L194:
+ cmp r3, #8
+ addeq r4, r4, #28
+ addeq r3, r7, r7, lsl #2
+ beq .L199
+ add r3, r7, #2
+ add r3, r3, r6, lsl #3
+ add r4, r4, r3, lsl #3
+ add r4, r4, #4
+ b .L193
+.L197:
+ ldrb r2, [r3, #1]! @ zero_extendqisi2
+ mov r0, #200
+ str r2, [r10, #2052]
+ str r3, [sp, #4]
+ bl ndelay
+ ldrsb r2, [r4, #1]!
+ ldr r3, [sp, #4]
+ str r2, [r10, #2048]
+ b .L196
+.L201:
.align 2
-.L171:
+.L200:
.word .LANCHOR0
- .word .LANCHOR0+1210
- .word .LANCHOR0+1238
.fnend
.size HynixSetRRPara, .-HynixSetRRPara
.align 2
.global FlashSetReadRetryDefault
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashSetReadRetryDefault, %function
FlashSetReadRetryDefault:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L181
- ldr r2, [r3, #44]
- ldrb r2, [r2, #19] @ zero_extendqisi2
- sub r2, r2, #1
- cmp r2, #7
- bxhi lr
- stmfd sp!, {r4, r5, r6, lr}
- .save {r4, r5, r6, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ ldr r5, .L209
+ ldr r3, [r5, #48]
+ ldrb r3, [r3, #19] @ zero_extendqisi2
+ sub r3, r3, #1
+ cmp r3, #7
+ pophi {r4, r5, r6, r7, r8, pc}
+ ldr r7, .L209+4
+ add r6, r5, #1216
mov r4, #0
- ldr r6, .L181+4
- mov r5, r3
-.L174:
- ldrb r3, [r6, r4, asl #3] @ zero_extendqisi2
+ add r6, r6, #4
+.L205:
+ ldrb r3, [r7, r4, lsl #3] @ zero_extendqisi2
uxtb r0, r4
cmp r3, #173
- bne .L175
- ldrb r1, [r5, #1211] @ zero_extendqisi2
+ bne .L204
mov r3, #0
- ldr r2, .L181+8
+ mov r2, r6
+ ldrb r1, [r5, #1217] @ zero_extendqisi2
bl HynixSetRRPara
-.L175:
+.L204:
add r4, r4, #1
cmp r4, #4
- bne .L174
- ldmfd sp!, {r4, r5, r6, pc}
-.L182:
+ bne .L205
+ pop {r4, r5, r6, r7, r8, pc}
+.L210:
.align 2
-.L181:
+.L209:
.word .LANCHOR0
- .word .LANCHOR0+2068
- .word .LANCHOR0+1214
+ .word .LANCHOR0+2072
.fnend
.size FlashSetReadRetryDefault, .-FlashSetReadRetryDefault
.align 2
- .global FlashReadStatusEN
- .type FlashReadStatusEN, %function
-FlashReadStatusEN:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L194
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- add r0, ip, r0, asl #3
- ldr r3, [ip, #44]
- ldrb r5, [r0, #16] @ zero_extendqisi2
- ldr r4, [r0, #12]
- ldrb r3, [r3, #8] @ zero_extendqisi2
- cmp r3, #2
- mov r3, r5, asl #8
- addne r3, r4, r3
- add r5, r5, #8
- movne r2, #112
- strne r2, [r3, #2056]
- bne .L188
- cmp r2, #0
- add r3, r4, r3
- ldrneb r2, [ip, #62] @ zero_extendqisi2
- ldreqb r2, [ip, #61] @ zero_extendqisi2
- str r2, [r3, #2056]
- ldrb r0, [ip, #63] @ zero_extendqisi2
- cmp r0, #0
- addne ip, r4, r5, asl #8
- movne r2, #0
- beq .L188
-.L187:
- cmp r2, r0
- bcs .L188
- mov r3, r2, asl #3
- add r2, r2, #1
- mov r3, r1, lsr r3
- uxtb r3, r3
- str r3, [ip, #4]
- b .L187
-.L188:
- mov r0, #80
- bl NandcDelayns
- ldr r0, [r4, r5, asl #8]
- uxtb r0, r0
- ldmfd sp!, {r3, r4, r5, pc}
-.L195:
- .align 2
-.L194:
- .word .LANCHOR0
- .fnend
- .size FlashReadStatusEN, .-FlashReadStatusEN
- .align 2
- .global FlashWaitReadyEN
- .type FlashWaitReadyEN, %function
-FlashWaitReadyEN:
- .fnstart
- @ args = 0, pretend = 0, frame = 0
- @ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
- .save {r4, r5, r6, lr}
- mov r4, r0
- mov r5, r1
- mov r6, r2
-.L197:
- mov r0, r4
- mov r1, r5
- mov r2, r6
- bl FlashReadStatusEN
- cmp r0, #255
- beq .L197
- tst r0, #64
- ldmnefd sp!, {r4, r5, r6, pc}
- mov r0, #1
- mov r1, #3
- bl usleep_range
- b .L197
- .fnend
- .size FlashWaitReadyEN, .-FlashWaitReadyEN
- .align 2
.global FlashWaitCmdDone
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashWaitCmdDone, %function
FlashWaitCmdDone:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- ldr r5, .L211
- add r4, r5, r0, asl #4
- ldr r3, [r4, #2108]
- ldrb r7, [r4, #2100] @ zero_extendqisi2
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ ldr r5, .L219
+ add r4, r5, r0, lsl #4
+ ldr r3, [r4, #2112]
cmp r3, #0
- beq .L205
+ beq .L213
+ ldrb r7, [r4, #2104] @ zero_extendqisi2
mov r6, r0
+ add r5, r5, r6, lsl #2
mov r0, r7
- add r5, r5, r6, asl #2
bl NandcFlashCs
- ldr r1, [r4, #2104]
+ ldr r2, [r5, #1180]
mov r0, r7
- ldr r2, [r5, #1172]
+ ldr r1, [r4, #2108]
adds r2, r2, #0
movne r2, #1
bl FlashWaitReadyEN
- mov r5, r0
+ mov r1, r0
mov r0, r7
bl NandcFlashDeCs
- ldr r2, [r4, #2108]
- sbfx r3, r5, #0, #1
- str r3, [r2]
- mov r2, #0
- ldr r1, [r4, #2112]
- str r2, [r4, #2108]
- cmp r1, r2
- strne r3, [r1]
- strne r2, [r4, #2112]
-.L205:
+ ldr r3, [r4, #2112]
+ sbfx r0, r1, #0, #1
+ str r0, [r3]
+ mov r3, #0
+ ldr r2, [r4, #2116]
+ str r3, [r4, #2112]
+ cmp r2, r3
+ strne r0, [r2]
+ strne r3, [r4, #2116]
+.L213:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L212:
+ pop {r4, r5, r6, r7, r8, pc}
+.L220:
.align 2
-.L211:
+.L219:
.word .LANCHOR0
.fnend
.size FlashWaitCmdDone, .-FlashWaitCmdDone
.align 2
- .type flash_read_ecc, %function
-flash_read_ecc:
+ .global NandcDelayns
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type NandcDelayns, %function
+NandcDelayns:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L215
- stmfd sp!, {r4, lr}
+ push {r4, lr}
.save {r4, lr}
- add r0, r2, r0, asl #3
- ldrb r4, [r0, #16] @ zero_extendqisi2
- ldr r3, [r0, #12]
- mov r0, #80
- add r4, r3, r4, asl #8
- mov r3, #122
- str r3, [r4, #2056]
- bl NandcDelayns
- ldr r3, [r4, #2048]
- ldr r0, [r4, #2048]
- and r3, r3, #15
- and r0, r0, #15
- cmp r0, r3
- movcc r0, r3
- ldr r3, [r4, #2048]
- and r3, r3, #15
- cmp r0, r3
- movcc r0, r3
- ldr r3, [r4, #2048]
- and r3, r3, #15
- cmp r0, r3
- movcc r0, r3
- ldmfd sp!, {r4, pc}
-.L216:
- .align 2
-.L215:
- .word .LANCHOR0
+ bl ndelay
+ mov r0, #0
+ pop {r4, pc}
.fnend
- .size flash_read_ecc, .-flash_read_ecc
+ .size NandcDelayns, .-NandcDelayns
.align 2
.global NandcWaitFlashReadyNoDelay
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcWaitFlashReadyNoDelay, %function
NandcWaitFlashReadyNoDelay:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L223
- stmfd sp!, {r0, r1, r2, r4, r5, lr}
+ ldr r3, .L229
+ push {r0, r1, r2, r4, r5, lr}
.save {r4, r5, lr}
.pad #12
- add r0, r3, r0, asl #3
- ldr r4, .L223+4
- ldr r5, [r0, #12]
-.L219:
+ ldr r4, .L229+4
+ ldr r5, [r3, r0, lsl #3]
+.L225:
ldr r3, [r5]
str r3, [sp, #4]
ldr r3, [sp, #4]
tst r3, #512
- bne .L220
+ bne .L226
mov r0, #10
- bl NandcDelayns
+ bl ndelay
subs r4, r4, #1
- bne .L219
+ bne .L225
mvn r0, #0
- b .L218
-.L220:
- mov r0, #0
-.L218:
+.L223:
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, pc}
-.L224:
+ pop {r4, r5, pc}
+.L226:
+ mov r0, #0
+ b .L223
+.L230:
.align 2
-.L223:
+.L229:
.word .LANCHOR0
.word 100000
.fnend
.size NandcWaitFlashReadyNoDelay, .-NandcWaitFlashReadyNoDelay
.align 2
.global NandcWaitFlashReady
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcWaitFlashReady, %function
NandcWaitFlashReady:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L231
- stmfd sp!, {r0, r1, r2, r4, r5, lr}
+ push {r0, r1, r2, r4, r5, lr}
.save {r4, r5, lr}
.pad #12
- add r0, r3, r0, asl #3
- ldr r4, .L231+4
- ldr r5, [r0, #12]
+ ldr r3, .L237
+ ldr r4, .L237+4
+ ldr r5, [r3, r0, lsl #3]
mov r0, #130
- bl NandcDelayns
-.L227:
+ bl ndelay
+.L233:
ldr r3, [r5]
str r3, [sp, #4]
ldr r3, [sp, #4]
tst r3, #512
- bne .L228
- mov r0, #1
+ bne .L234
mov r1, #2
+ mov r0, #1
bl usleep_range
subs r4, r4, #1
- bne .L227
+ bne .L233
mvn r0, #0
- b .L226
-.L228:
- mov r0, #0
-.L226:
+.L231:
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, pc}
-.L232:
+ pop {r4, r5, pc}
+.L234:
+ mov r0, #0
+ b .L231
+.L238:
.align 2
-.L231:
+.L237:
.word .LANCHOR0
.word 100000
.fnend
.size NandcWaitFlashReady, .-NandcWaitFlashReady
.align 2
.global FlashReset
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReset, %function
FlashReset:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L235
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r3, .L241
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- add r3, r3, r0, asl #3
mov r4, r0
- ldrb r6, [r3, #16] @ zero_extendqisi2
- ldr r5, [r3, #12]
+ ldr r5, [r3, r0, lsl #3]
+ add r3, r3, r0, lsl #3
+ ldrb r6, [r3, #4] @ zero_extendqisi2
bl NandcFlashCs
mov r3, #255
mov r0, r4
- add r5, r5, r6, asl #8
+ add r5, r5, r6, lsl #8
str r3, [r5, #2056]
bl NandcWaitFlashReady
mov r0, r4
- ldmfd sp!, {r4, r5, r6, lr}
+ pop {r4, r5, r6, lr}
b NandcFlashDeCs
-.L236:
+.L242:
.align 2
-.L235:
+.L241:
.word .LANCHOR0
.fnend
.size FlashReset, .-FlashReset
.align 2
.global flash_enter_slc_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type flash_enter_slc_mode, %function
flash_enter_slc_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
- ldr r5, .L244
- ldrb r3, [r5, #144] @ zero_extendqisi2
+ ldr r5, .L250
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- ldmeqfd sp!, {r4, r5, r6, r7, r8, pc}
+ popeq {r4, r5, r6, r7, r8, pc}
mov r6, r0
bl NandcFlashCs
- add r4, r5, r6, asl #3
- ldrb r3, [r4, #2068] @ zero_extendqisi2
- ldrb r8, [r4, #16] @ zero_extendqisi2
+ add r3, r5, r6, lsl #3
+ ldr r7, [r5, r6, lsl #3]
+ ldrb r8, [r3, #4] @ zero_extendqisi2
+ ldrb r3, [r3, #2072] @ zero_extendqisi2
cmp r3, #44
- ldr r7, [r4, #12]
- mov r8, r8, asl #8
- bne .L239
+ lsl r8, r8, #8
+ bne .L245
add r4, r7, r8
mov r3, #239
- mov r0, #50
str r3, [r4, #2056]
mov r3, #145
str r3, [r4, #2052]
- bl NandcDelayns
+ mov r0, #50
+ bl ndelay
mov r3, #0
mov r2, #1
str r3, [r4, #2048]
@@ -1387,53 +1547,56 @@
str r2, [r4, #2048]
str r3, [r4, #2048]
str r3, [r4, #2048]
- bl NandcDelayns
-.L239:
- add r7, r7, r8
+ bl ndelay
+.L245:
mov r0, r6
+ add r7, r7, r8
bl NandcWaitFlashReadyNoDelay
mov r3, #218
mov r0, r6
str r3, [r7, #2056]
bl NandcWaitFlashReady
mov r3, #2
- strb r3, [r5, #2228]
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L245:
+ strb r3, [r5, #2232]
+ pop {r4, r5, r6, r7, r8, pc}
+.L251:
.align 2
-.L244:
+.L250:
.word .LANCHOR0
.fnend
.size flash_enter_slc_mode, .-flash_enter_slc_mode
.align 2
.global flash_exit_slc_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type flash_exit_slc_mode, %function
flash_exit_slc_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
- ldr r5, .L253
- ldrb r3, [r5, #144] @ zero_extendqisi2
+ ldr r5, .L259
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- ldmeqfd sp!, {r4, r5, r6, r7, r8, pc}
+ popeq {r4, r5, r6, r7, r8, pc}
mov r6, r0
bl NandcFlashCs
- add r4, r5, r6, asl #3
- ldrb r3, [r4, #2068] @ zero_extendqisi2
- ldrb r8, [r4, #16] @ zero_extendqisi2
+ add r3, r5, r6, lsl #3
+ ldr r7, [r5, r6, lsl #3]
+ ldrb r8, [r3, #4] @ zero_extendqisi2
+ ldrb r3, [r3, #2072] @ zero_extendqisi2
cmp r3, #44
- ldr r7, [r4, #12]
- mov r8, r8, asl #8
- bne .L248
+ lsl r8, r8, #8
+ bne .L254
add r4, r7, r8
mov r3, #239
- mov r0, #50
str r3, [r4, #2056]
mov r3, #145
str r3, [r4, #2052]
- bl NandcDelayns
+ mov r0, #50
+ bl ndelay
mov r3, #2
mov r0, #100
str r3, [r4, #2048]
@@ -1442,32 +1605,35 @@
mov r3, #0
str r3, [r4, #2048]
str r3, [r4, #2048]
- bl NandcDelayns
-.L248:
- add r7, r7, r8
+ bl ndelay
+.L254:
mov r0, r6
+ add r7, r7, r8
bl NandcWaitFlashReadyNoDelay
mov r3, #223
mov r0, r6
str r3, [r7, #2056]
bl NandcWaitFlashReady
mov r3, #0
- strb r3, [r5, #2228]
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L254:
+ strb r3, [r5, #2232]
+ pop {r4, r5, r6, r7, r8, pc}
+.L260:
.align 2
-.L253:
+.L259:
.word .LANCHOR0
.fnend
.size flash_exit_slc_mode, .-flash_exit_slc_mode
.align 2
.global FlashEraseBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashEraseBlock, %function
FlashEraseBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r4, r0
mov r5, r1
@@ -1484,138 +1650,140 @@
mov r1, r5
mov r0, r4
bl FlashReadStatus
- mov r5, r0
+ mov r1, r0
mov r0, r4
bl NandcFlashDeCs
- and r0, r5, #1
- ldmfd sp!, {r4, r5, r6, pc}
+ and r0, r1, #1
+ pop {r4, r5, r6, pc}
.fnend
.size FlashEraseBlock, .-FlashEraseBlock
.align 2
.global FlashSetInterfaceMode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashSetInterfaceMode, %function
FlashSetInterfaceMode:
.fnstart
- @ args = 0, pretend = 0, frame = 16
+ @ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r1, .L280
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #20
- sub sp, sp, #20
- ldrb fp, [r1, #2229] @ zero_extendqisi2
+ .pad #12
mov lr, #0
- ldr r7, .L280+4
- mov r4, #239
- and r2, fp, #4
- and r3, fp, #1
- mov r5, #128
- str r3, [sp, #8]
- mov r6, #1
- uxtb r3, r2
+ ldr r4, .L286
+ mov r5, #239
+ mov r6, #128
+ mov r7, #1
mov r8, #35
- mov r2, lr
mov r9, #32
+ ldrb r3, [r4, #2233] @ zero_extendqisi2
mov r10, #5
- str r3, [sp, #4]
- add r3, r1, #12
- str r3, [sp, #12]
-.L267:
- ldr r3, [sp, #12]
- ldrb ip, [lr, r7] @ zero_extendqisi2
- ldr r1, [r3, lr]!
+ and r2, r3, #4
+ and r3, r3, #1
+ str r2, [sp, #4]
+ mov r2, lr
+ str r3, [sp]
+.L273:
+ ldr r1, .L286+4
+ add r3, r4, lr
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ ldrb ip, [lr, r1] @ zero_extendqisi2
cmp ip, #69
cmpne ip, #152
- ldrb r3, [r3, #4] @ zero_extendqisi2
- beq .L258
+ beq .L264
cmp ip, #44
cmpne ip, #173
- bne .L259
-.L258:
+ bne .L265
+.L264:
cmp r0, #1
- bne .L260
- ldr fp, [sp, #8]
+ ldr r1, [r4, lr]
+ bne .L266
+ ldr fp, [sp]
cmp fp, #0
- beq .L259
- mov r3, r3, asl #8
+ beq .L265
+ lsl r3, r3, #8
cmp ip, #173
add fp, r1, r3
- str r4, [fp, #2056]
+ str r5, [fp, #2056]
streq r0, [fp, #2052]
- beq .L279
+ beq .L285
cmp ip, #44
streq r0, [fp, #2052]
- strne r5, [fp, #2052]
+ strne r6, [fp, #2052]
streq r10, [fp, #2048]
strne r0, [fp, #2048]
- b .L265
-.L260:
- ldr fp, [sp, #4]
- cmp fp, #0
- beq .L259
- mov r3, r3, asl #8
- cmp ip, #173
- add fp, r1, r3
- str r4, [fp, #2056]
- streq r6, [fp, #2052]
- streq r9, [fp, #2048]
- beq .L265
- cmp ip, #44
- streq r6, [fp, #2052]
- streq r8, [fp, #2048]
- beq .L265
- str r5, [fp, #2052]
-.L279:
- str r2, [fp, #2048]
-.L265:
+.L271:
add r3, r1, r3
str r2, [r3, #2048]
str r2, [r3, #2048]
str r2, [r3, #2048]
-.L259:
+.L265:
add lr, lr, #8
cmp lr, #32
- bne .L267
+ bne .L273
mov r0, #0
bl NandcWaitFlashReady
mov r0, #0
- add sp, sp, #20
+ add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L281:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L266:
+ ldr fp, [sp, #4]
+ cmp fp, #0
+ beq .L265
+ lsl r3, r3, #8
+ cmp ip, #173
+ add fp, r1, r3
+ str r5, [fp, #2056]
+ streq r7, [fp, #2052]
+ streq r9, [fp, #2048]
+ beq .L271
+ cmp ip, #44
+ streq r7, [fp, #2052]
+ streq r8, [fp, #2048]
+ beq .L271
+ str r6, [fp, #2052]
+.L285:
+ str r2, [fp, #2048]
+ b .L271
+.L287:
.align 2
-.L280:
+.L286:
.word .LANCHOR0
- .word .LANCHOR0+2068
+ .word .LANCHOR0+2072
.fnend
.size FlashSetInterfaceMode, .-FlashSetInterfaceMode
.align 2
.global FlashReadSpare
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadSpare, %function
FlashReadSpare:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L284
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- add ip, ip, r0, asl #3
- ldr r3, .L284+4
+ ldr ip, .L290
+ ldr r3, .L290+4
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r5, r2
- ldrb r2, [ip, #16] @ zero_extendqisi2
- ldr r4, [ip, #12]
- ldrb r3, [r3, #481] @ zero_extendqisi2
- add r4, r4, r2, asl #8
+ ldr r4, [ip, r0, lsl #3]
+ add ip, ip, r0, lsl #3
+ ldrb r3, [r3, #477] @ zero_extendqisi2
+ ldrb r2, [ip, #4] @ zero_extendqisi2
+ lsl r3, r3, #9
+ add r4, r4, r2, lsl #8
mov r2, #0
- mov r3, r3, asl #9
str r2, [r4, #2056]
str r3, [r4, #2052]
- mov r3, r3, lsr #8
+ lsr r3, r3, #8
str r3, [r4, #2052]
uxtb r3, r1
str r3, [r4, #2052]
- mov r3, r1, lsr #8
- mov r1, r1, lsr #16
+ lsr r3, r1, #8
+ lsr r1, r1, #16
str r3, [r4, #2052]
mov r3, #48
str r1, [r4, #2052]
@@ -1623,28 +1791,31 @@
bl NandcWaitFlashReady
ldr r3, [r4, #2048]
strb r3, [r5]
- ldmfd sp!, {r3, r4, r5, pc}
-.L285:
+ pop {r4, r5, r6, pc}
+.L291:
.align 2
-.L284:
+.L290:
.word .LANCHOR0
.word .LANCHOR1
.fnend
.size FlashReadSpare, .-FlashReadSpare
.align 2
.global SandiskProgTestBadBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type SandiskProgTestBadBlock, %function
SandiskProgTestBadBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L288
- stmfd sp!, {r4, lr}
+ ldr r3, .L294
+ push {r4, lr}
.save {r4, lr}
- add r2, r2, r0, asl #3
- ldrb r4, [r2, #16] @ zero_extendqisi2
- ldr r3, [r2, #12]
- add r4, r3, r4, asl #8
+ ldr r4, [r3, r0, lsl #3]
+ add r3, r3, r0, lsl #3
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ add r4, r4, r3, lsl #8
mov r3, #162
str r3, [r4, #2056]
mov r3, #128
@@ -1654,163 +1825,177 @@
str r3, [r4, #2052]
uxtb r3, r1
str r3, [r4, #2052]
- mov r3, r1, lsr #8
- mov r1, r1, lsr #16
+ lsr r3, r1, #8
+ lsr r1, r1, #16
str r3, [r4, #2052]
- str r1, [r4, #2052]
mov r3, #16
+ str r1, [r4, #2052]
str r3, [r4, #2056]
bl NandcWaitFlashReady
mov r3, #112
mov r0, #80
str r3, [r4, #2056]
- bl NandcDelayns
+ bl ndelay
ldr r0, [r4, #2048]
and r0, r0, #1
- ldmfd sp!, {r4, pc}
-.L289:
+ pop {r4, pc}
+.L295:
.align 2
-.L288:
+.L294:
.word .LANCHOR0
.fnend
.size SandiskProgTestBadBlock, .-SandiskProgTestBadBlock
.align 2
.global SandiskSetRRPara
+ .syntax unified
+ .arm
+ .fpu softvfp
.type SandiskSetRRPara, %function
SandiskSetRRPara:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
mov r3, #239
- mov r5, r0
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
str r3, [r0, #8]
mov r3, #17
+ mov r5, r0
+ mov r4, r1
str r3, [r0, #4]
mov r0, #200
- mov r4, r1
- bl NandcDelayns
- ldr r0, .L298
- ldr r1, .L298+4
- add r4, r4, r4, asl #2
- sub ip, r0, #48
+ bl ndelay
+ ldr r0, .L303
+ add r4, r4, r4, lsl #2
+ ldr r1, .L303+4
mov r2, #0
-.L291:
- ldrb r3, [r1, #1209] @ zero_extendqisi2
+ sub ip, r0, #45
+.L297:
+ ldrb r3, [r1, #85] @ zero_extendqisi2
cmp r2, r3
- bcs .L297
- ldrb r3, [r1, #1208] @ zero_extendqisi2
+ bcc .L300
+ mov r0, #0
+ pop {r4, r5, r6, lr}
+ b NandcWaitFlashReady
+.L300:
+ ldrb r3, [r1, #84] @ zero_extendqisi2
cmp r3, #67
add r3, r2, r4
addeq r3, ip, r3
addne r3, r0, r3
- add r2, r2, #1
ldrsb r3, [r3, #5]
+ add r2, r2, #1
str r3, [r5]
- b .L291
-.L297:
- mov r0, #0
- ldmfd sp!, {r3, r4, r5, lr}
- b NandcWaitFlashReady
-.L299:
+ b .L297
+.L304:
.align 2
-.L298:
- .word .LANCHOR1+304
+.L303:
+ .word .LANCHOR1+301
.word .LANCHOR0
.fnend
.size SandiskSetRRPara, .-SandiskSetRRPara
.align 2
.global micron_auto_read_calibration_config
+ .syntax unified
+ .arm
+ .fpu softvfp
.type micron_auto_read_calibration_config, %function
micron_auto_read_calibration_config:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r4, r0
- mov r5, r1
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r5, r0
+ mov r6, r1
bl NandcWaitFlashReady
- ldr r3, .L302
+ ldr r0, .L307
+ ldr r4, [r0, r5, lsl #3]
+ add r0, r0, r5, lsl #3
+ ldrb r3, [r0, #4] @ zero_extendqisi2
mov r0, #200
- add r2, r3, r4, asl #3
- ldrb r4, [r2, #16] @ zero_extendqisi2
- ldr r3, [r2, #12]
- add r4, r3, r4, asl #8
+ add r4, r4, r3, lsl #8
mov r3, #239
str r3, [r4, #2056]
mov r3, #150
str r3, [r4, #2052]
- bl NandcDelayns
- str r5, [r4, #2048]
+ bl ndelay
mov r3, #0
+ str r6, [r4, #2048]
str r3, [r4, #2048]
str r3, [r4, #2048]
str r3, [r4, #2048]
- ldmfd sp!, {r3, r4, r5, pc}
-.L303:
+ pop {r4, r5, r6, pc}
+.L308:
.align 2
-.L302:
+.L307:
.word .LANCHOR0
.fnend
.size micron_auto_read_calibration_config, .-micron_auto_read_calibration_config
.align 2
.global FlashEraseSLc2KBlocks
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashEraseSLc2KBlocks, %function
FlashEraseSLc2KBlocks:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
- .save {r4, r5, r6, r7, r8, r9, lr}
+ push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ .pad #16
mov r5, #0
- ldr r8, .L316
- .pad #20
- sub sp, sp, #20
+ ldr r8, .L320
mov r6, r0
mov r9, r1
mov r7, r5
-.L305:
+ ldr r10, .L320+4
+.L310:
cmp r7, r9
- beq .L315
- rsb r3, r7, r9
+ bne .L315
+ mov r0, #0
+ add sp, sp, #16
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L315:
+ sub r3, r9, r7
add r2, sp, #8
- add r0, r6, r5
- mov r1, #0
uxtb r3, r3
+ mov r1, #0
+ add r0, r6, r5
str r3, [sp]
add r3, sp, #12
bl LogAddr2PhyAddr
- ldrb r2, [r8, #2230] @ zero_extendqisi2
+ ldrb r2, [r8, #2234] @ zero_extendqisi2
ldr r3, [sp, #12]
- cmp r3, r2
- mvncs r3, #0
- strcs r3, [r6, r5]
- bcs .L307
+ cmp r2, r3
+ mvnls r3, #0
+ strls r3, [r6, r5]
+ bls .L312
add r2, r8, r3
- add r3, r8, r3, asl #4
- ldrb r4, [r2, #2232] @ zero_extendqisi2
- strb r4, [r3, #2100]
+ add r3, r8, r3, lsl #4
+ ldrb r4, [r2, #2236] @ zero_extendqisi2
+ strb r4, [r3, #2104]
mov r0, r4
bl NandcWaitFlashReady
mov r0, r4
bl NandcFlashCs
mov r2, #0
- mov r0, r4
ldr r1, [sp, #8]
+ mov r0, r4
bl FlashEraseCmd
mov r0, r4
bl NandcWaitFlashReady
mov r0, r4
ldr r1, [sp, #8]
bl FlashReadStatus
- mov r2, #0
- ldr r3, [sp, #8]
sbfx r0, r0, #0, #1
+ ldr r1, [sp, #8]
str r0, [r6, r5]
+ mov r2, #0
+ ldr r3, [r8, #40]
mov r0, r4
- ldr r1, [r8, #4]
add r1, r1, r3
bl FlashEraseCmd
mov r0, r4
@@ -1823,249 +2008,244 @@
strne r3, [r6, r5]
ldr r3, [r6, r5]
cmn r3, #1
- bne .L309
- ldr r0, .L316+4
+ bne .L314
ldr r1, [sp, #8]
+ mov r0, r10
bl printk
-.L309:
+.L314:
mov r0, r4
bl NandcFlashDeCs
-.L307:
+.L312:
add r7, r7, #1
add r5, r5, #36
- b .L305
-.L315:
- mov r0, #0
- add sp, sp, #20
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L317:
+ b .L310
+.L321:
.align 2
-.L316:
+.L320:
.word .LANCHOR0
.word .LC1
.fnend
.size FlashEraseSLc2KBlocks, .-FlashEraseSLc2KBlocks
.align 2
.global FlashEraseBlocks
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashEraseBlocks, %function
FlashEraseBlocks:
.fnstart
- @ args = 0, pretend = 0, frame = 16
+ @ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r8, r2
- ldr r4, .L354
- .pad #28
- sub sp, sp, #28
- ldrb r5, [r4] @ zero_extendqisi2
+ ldr r4, .L355
+ .pad #20
+ sub sp, sp, #20
+ ldrb r5, [r4, #36] @ zero_extendqisi2
cmp r5, #0
moveq r9, r0
moveq r10, r1
- moveq fp, r4
- beq .L319
+ beq .L324
mov r1, r2
bl FlashEraseSLc2KBlocks
- b .L320
-.L328:
- mov r3, #36
- mov r1, #0
- mul r6, r3, r5
- add r2, sp, #16
- add r3, r9, r6
- str r3, [sp, #12]
- rsb r3, r5, r8
- ldr r0, [sp, #12]
- uxtb r3, r3
- str r3, [sp]
- add r3, sp, #20
- bl LogAddr2PhyAddr
- ldrb r3, [r4, #2230] @ zero_extendqisi2
- mov r7, r0
- ldr r0, [sp, #20]
- cmp r0, r3
- mvncs r3, #0
- strcs r3, [r9, r6]
- bcc .L351
.L322:
- add r5, r5, #1
-.L319:
- cmp r5, r8
- bcc .L328
- b .L352
-.L351:
- ldrb r3, [fp, #2240] @ zero_extendqisi2
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L333:
+ mov r3, #36
+ add r2, sp, #8
+ mul r6, r3, r5
+ sub r3, r8, r5
+ uxtb r3, r3
+ mov r1, #0
+ str r3, [sp]
+ add r3, sp, #12
+ add fp, r9, r6
+ mov r0, fp
+ bl LogAddr2PhyAddr
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ mov r7, r0
+ ldr r0, [sp, #12]
+ cmp r3, r0
+ mvnls r3, #0
+ strls r3, [r9, r6]
+ bls .L327
+ ldrb r3, [r4, #2244] @ zero_extendqisi2
cmp r3, #0
- add r3, r4, r0, asl #4
- ldr r3, [r3, #2108]
+ add r3, r4, r0, lsl #4
moveq r7, #0
+ ldr r3, [r3, #2112]
cmp r3, #0
- beq .L324
+ beq .L329
uxtb r0, r0
bl FlashWaitCmdDone
-.L324:
- ldr r2, [sp, #20]
+.L329:
+ ldr r2, [sp, #12]
cmp r7, #0
- ldr r0, [sp, #12]
- addne ip, r6, #36
- addne ip, r9, ip
- mov r3, r2, asl #4
+ addne r6, r6, #36
+ mov r0, #0
+ addne r6, r9, r6
+ lsl r3, r2, #4
add r2, r4, r2
add r1, r4, r3
add r3, r4, r3
- ldrb r6, [r2, #2232] @ zero_extendqisi2
+ str r0, [r1, #2116]
+ ldr r0, [sp, #8]
+ strne r6, [r1, #2116]
+ ldrb r6, [r2, #2236] @ zero_extendqisi2
str r0, [r1, #2108]
- mov r0, #0
- str r0, [r1, #2112]
- ldr r0, [sp, #16]
- strne ip, [r1, #2112]
- strb r6, [r3, #2100]
- str r0, [r1, #2104]
+ str fp, [r1, #2112]
mov r0, r6
+ strb r6, [r3, #2104]
bl NandcFlashCs
cmp r10, #1
mov r0, r6
- bne .L326
- ldrb r3, [fp, #144] @ zero_extendqisi2
+ bne .L331
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L326
+ beq .L331
bl flash_enter_slc_mode
- b .L327
-.L326:
- bl flash_exit_slc_mode
-.L327:
- ldr r3, [sp, #20]
+.L332:
+ ldr r3, [sp, #12]
mov r0, r6
- ldr r1, [sp, #16]
+ ldr r1, [sp, #8]
add r5, r5, r7
- add r3, r4, r3, asl #2
- ldr r2, [r3, #1172]
+ add r3, r4, r3, lsl #2
+ ldr r2, [r3, #1180]
adds r2, r2, #0
movne r2, #1
bl FlashWaitReadyEN
- mov r0, r6
mov r2, r7
- ldr r1, [sp, #16]
+ ldr r1, [sp, #8]
+ mov r0, r6
bl FlashEraseCmd
mov r0, r6
bl NandcFlashDeCs
- b .L322
-.L352:
- ldr r6, .L354
+.L327:
+ add r5, r5, #1
+.L324:
+ cmp r5, r8
+ bcc .L333
+ ldr r6, .L355+4
mov r5, #0
- ldr r7, .L354+4
-.L329:
- ldrb r2, [r4, #2230] @ zero_extendqisi2
- ldr r3, .L354
- cmp r5, r2
- bcs .L353
+.L334:
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ cmp r5, r3
+ bcc .L336
+ ldr r3, [r4, #2248]
+ cmp r3, #0
+ bne .L337
+.L338:
+ mov r0, #0
+ b .L322
+.L331:
+ bl flash_exit_slc_mode
+ b .L332
+.L336:
uxtb r0, r5
bl FlashWaitCmdDone
cmp r10, #1
- bne .L330
- ldrb r3, [r6, #144] @ zero_extendqisi2
+ bne .L335
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L330
- ldrb r0, [r7, r5, asl #4] @ zero_extendqisi2
+ beq .L335
+ ldrb r0, [r6, r5, lsl #4] @ zero_extendqisi2
bl flash_exit_slc_mode
-.L330:
+.L335:
add r5, r5, #1
- b .L329
-.L353:
- ldr r2, [r3, #2244]
- cmp r2, #0
- bne .L332
-.L334:
- mov r0, #0
- b .L320
-.L332:
- ldrb r3, [r3, #2068] @ zero_extendqisi2
+ b .L334
+.L337:
+ ldrb r3, [r4, #2072] @ zero_extendqisi2
cmp r3, #69
- bne .L334
- mov r3, #0
- mov r2, #36
- mov r1, r3
-.L333:
+ moveq r3, #0
+ moveq r2, #36
+ moveq r1, r3
+ bne .L338
+.L339:
cmp r3, r8
- beq .L334
+ beq .L338
mul r0, r2, r3
add r3, r3, #1
str r1, [r9, r0]
- b .L333
-.L320:
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L355:
+ b .L339
+.L356:
.align 2
-.L354:
+.L355:
.word .LANCHOR0
- .word .LANCHOR0+2100
+ .word .LANCHOR0+2104
.fnend
.size FlashEraseBlocks, .-FlashEraseBlocks
.align 2
.global FlashReadDpCmd
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadDpCmd, %function
FlashReadDpCmd:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
- mov r8, r0
- ldr r0, .L362
- mov r7, r1
+ mov r7, r0
+ ldr r0, .L363
+ mov r8, r1
uxtb r10, r2
- mov r9, r2, lsr #8
- add r3, r0, r8, asl #3
- mov r5, r2, lsr #16
- ldrb r1, [r0, #64] @ zero_extendqisi2
- uxtb lr, r7
- ldr r4, [r3, #12]
- mov ip, r7, lsr #8
- ldrb r3, [r3, #16] @ zero_extendqisi2
- cmp r1, #1
- ldr r2, [r0, #44]
- mov r1, r7, lsr #16
- mov r3, r3, asl #8
+ lsr r9, r2, #8
+ lsr r6, r2, #16
+ uxtb lr, r8
+ ldr r2, [r0, #48]
+ lsr ip, r8, #8
+ add r1, r0, r7, lsl #3
+ ldr r3, [r0, r7, lsl #3]
+ ldrb r4, [r1, #4] @ zero_extendqisi2
+ ldrb r1, [r0, #68] @ zero_extendqisi2
ldrb r2, [r2, #7] @ zero_extendqisi2
- bne .L357
+ cmp r1, #1
+ lsl r4, r4, #8
+ lsr r1, r8, #16
+ bne .L358
cmp r2, #1
- addeq r2, r4, r3
- add r4, r4, r3
- moveq r6, #38
- streq r6, [r2, #2056]
- mov r6, #0
- ldrb r3, [r0, #57] @ zero_extendqisi2
- ldrb r2, [r0, #56] @ zero_extendqisi2
- mov r0, r8
+ addeq r2, r3, r4
+ moveq r5, #38
+ add r4, r3, r4
+ streq r5, [r2, #2056]
+ ldrb r3, [r0, #61] @ zero_extendqisi2
+ mov r5, #0
+ ldrb r2, [r0, #60] @ zero_extendqisi2
+ mov r0, r7
str r2, [r4, #2056]
- str r6, [r4, #2052]
- str r6, [r4, #2052]
+ str r5, [r4, #2052]
+ str r5, [r4, #2052]
str lr, [r4, #2052]
str ip, [r4, #2052]
str r1, [r4, #2052]
str r3, [r4, #2056]
bl NandcWaitFlashReady
- str r6, [r4, #2056]
mov r3, #48
- str r6, [r4, #2052]
- str r6, [r4, #2052]
+ str r5, [r4, #2056]
+ str r5, [r4, #2052]
+ str r5, [r4, #2052]
str r10, [r4, #2052]
str r9, [r4, #2052]
- str r5, [r4, #2052]
+ str r6, [r4, #2052]
str r3, [r4, #2056]
- b .L359
-.L357:
+.L360:
+ mov r1, r8
+ mov r0, r7
+ pop {r4, r5, r6, r7, r8, r9, r10, lr}
+ b FlashSetRandomizer
+.L358:
cmp r2, #1
- addeq r2, r4, r3
- add r3, r4, r3
- moveq r6, #38
- streq r6, [r2, #2056]
- ldrb r2, [r0, #56] @ zero_extendqisi2
+ addeq r2, r3, r4
+ moveq r5, #38
+ streq r5, [r2, #2056]
+ add r3, r3, r4
+ ldrb r2, [r0, #60] @ zero_extendqisi2
str r2, [r3, #2056]
- ldrb r2, [r0, #57] @ zero_extendqisi2
+ ldrb r2, [r0, #61] @ zero_extendqisi2
str lr, [r3, #2052]
str ip, [r3, #2052]
str r1, [r3, #2052]
@@ -2073,132 +2253,140 @@
mov r2, #48
str r10, [r3, #2052]
str r9, [r3, #2052]
- str r5, [r3, #2052]
+ str r6, [r3, #2052]
str r2, [r3, #2056]
-.L359:
- mov r0, r8
- mov r1, r7
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- b FlashSetRandomizer
-.L363:
+ b .L360
+.L364:
.align 2
-.L362:
+.L363:
.word .LANCHOR0
.fnend
.size FlashReadDpCmd, .-FlashReadDpCmd
.align 2
.global ftl_flash_de_init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_flash_de_init, %function
ftl_flash_de_init:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
+ push {r4, lr}
+ .save {r4, lr}
mov r0, #0
- ldr r4, .L375
+ ldr r4, .L376
bl NandcWaitFlashReady
bl FlashSetReadRetryDefault
- ldr r0, [r4, #2248]
+ ldr r0, [r4, #2252]
cmp r0, #0
- beq .L365
+ beq .L366
mov r0, #0
bl flash_enter_slc_mode
- b .L366
-.L365:
- bl flash_exit_slc_mode
-.L366:
- ldrb r3, [r4, #2252] @ zero_extendqisi2
- ldr r5, .L375
+.L367:
+ ldrb r3, [r4, #2256] @ zero_extendqisi2
cmp r3, #0
- beq .L367
- ldrb r3, [r5, #2229] @ zero_extendqisi2
+ beq .L368
+ ldrb r3, [r4, #2233] @ zero_extendqisi2
tst r3, #1
- beq .L367
+ beq .L368
mov r0, #1
bl FlashSetInterfaceMode
mov r0, #1
bl NandcSetMode
mov r3, #0
- strb r3, [r5, #2252]
-.L367:
- ldr r3, [r4, #12]
+ strb r3, [r4, #2256]
+.L368:
+ ldr r3, [r4]
mov r0, #0
str r0, [r3, #336]
- ldmfd sp!, {r3, r4, r5, pc}
-.L376:
+ pop {r4, pc}
+.L366:
+ bl flash_exit_slc_mode
+ b .L367
+.L377:
.align 2
-.L375:
+.L376:
.word .LANCHOR0
.fnend
.size ftl_flash_de_init, .-ftl_flash_de_init
.align 2
.global NandcRandmzSel
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcRandmzSel, %function
NandcRandmzSel:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L378
- add r0, r3, r0, asl #3
- ldr r3, [r0, #12]
+ ldr r3, .L379
+ ldr r3, [r3, r0, lsl #3]
str r1, [r3, #336]
bx lr
-.L379:
+.L380:
.align 2
-.L378:
+.L379:
.word .LANCHOR0
.fnend
.size NandcRandmzSel, .-NandcRandmzSel
.global __aeabi_idiv
.align 2
.global NandcTimeCfg
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcTimeCfg, %function
NandcTimeCfg:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, lr}
+ push {r4, lr}
.save {r4, lr}
mov r4, r0
mov r0, #0
bl rknand_get_clk_rate
- ldr r1, .L391
+ ldr r1, .L392
bl __aeabi_idiv
- ldr r3, .L391+4
- ldr r3, [r3, #80]
+ ldr r3, .L392+4
cmp r0, #250
movwgt r2, #8354
- bgt .L389
- cmp r0, #220
+ ldr r3, [r3, #88]
bgt .L390
+ cmp r0, #220
+ ble .L384
+.L391:
+ movw r2, #8322
+ b .L390
+.L384:
cmp r0, #185
movwgt r2, #4226
- bgt .L389
+ bgt .L390
cmp r0, #160
movwgt r2, #4194
- bgt .L389
+ bgt .L390
cmp r4, #35
movwls r2, #4193
- bls .L389
+ bls .L390
cmp r4, #99
movwls r2, #4225
- bls .L389
+ bhi .L391
.L390:
- movw r2, #8322
-.L389:
str r2, [r3, #4]
- ldmfd sp!, {r4, pc}
-.L392:
+ pop {r4, pc}
+.L393:
.align 2
-.L391:
+.L392:
.word 1000000
.word .LANCHOR0
.fnend
.size NandcTimeCfg, .-NandcTimeCfg
.align 2
.global FlashTimingCfg
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashTimingCfg, %function
FlashTimingCfg:
.fnstart
@@ -2209,249 +2397,266 @@
sub r3, r3, #33
bic r3, r3, #32
cmp r3, #1
- bls .L394
+ bls .L395
movw r3, #8322
cmp r0, r3
- bne .L395
-.L394:
- ldr r3, .L396
- ldr r3, [r3, #80]
- str r0, [r3, #4]
+ bne .L396
.L395:
- ldr r3, .L396+4
- ldrb r0, [r3, #493] @ zero_extendqisi2
- b NandcTimeCfg
-.L397:
- .align 2
+ ldr r3, .L397
+ ldr r3, [r3, #88]
+ str r0, [r3, #4]
.L396:
+ ldr r3, .L397+4
+ ldrb r0, [r3, #489] @ zero_extendqisi2
+ b NandcTimeCfg
+.L398:
+ .align 2
+.L397:
.word .LANCHOR0
.word .LANCHOR1
.fnend
.size FlashTimingCfg, .-FlashTimingCfg
.align 2
.global NandcInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcInit, %function
NandcInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r1, #0
- ldr r3, .L401
+ ldr r3, .L402
mov r2, #1
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r1, #0
mov r5, #0
- str r1, [r3, #16]
mov r4, r3
- str r0, [r3, #12]
- str r2, [r3, #24]
+ str r2, [r3, #12]
mov r2, #2
- str r0, [r3, #20]
- str r2, [r3, #32]
+ str r2, [r3, #20]
mov r2, #3
- str r0, [r3, #28]
- str r0, [r3, #36]
- str r0, [r3, #80]
- str r2, [r3, #40]
+ stm r3, {r0, r1}
+ str r0, [r3, #8]
+ str r0, [r3, #16]
+ str r0, [r3, #24]
+ str r0, [r3, #88]
+ str r2, [r3, #28]
ldr r2, [r0]
and r2, r2, #253952
ubfx ip, r2, #13, #1
bfi r2, r1, #13, #1
ldr r1, [r0, #352]
orr r2, r2, #256
- str ip, [r3, #2256]
+ str ip, [r3, #2260]
movw ip, #2049
ubfx r1, r1, #16, #4
- str r1, [r3, #2260]
+ str r1, [r3, #2264]
ldr r1, [r0, #352]
cmp r1, ip
- str r1, [r3, #2264]
+ str r1, [r3, #2268]
moveq r3, #8
- streq r3, [r4, #2260]
+ streq r3, [r4, #2264]
str r2, [r0]
mov r0, #40
- ldr r3, [r4, #80]
+ ldr r3, [r4, #88]
str r5, [r3, #336]
bl NandcTimeCfg
- ldr r3, [r4, #80]
+ ldr r3, [r4, #88]
movw r2, #8322
mov r0, #36864
str r2, [r3, #344]
- ldr r2, .L401+4
+ ldr r2, .L402+4
str r2, [r3, #304]
bl ftl_malloc
- str r5, [r4, #2296]
- str r5, [r4, #2304]
- str r0, [r4, #2268]
str r0, [r4, #2272]
- add r0, r0, #32768
str r0, [r4, #2276]
- ldmfd sp!, {r3, r4, r5, pc}
-.L402:
+ add r0, r0, #32768
+ str r0, [r4, #2280]
+ str r5, [r4, #2300]
+ str r5, [r4, #2308]
+ pop {r4, r5, r6, pc}
+.L403:
.align 2
-.L401:
+.L402:
.word .LANCHOR0
.word 1579009
.fnend
.size NandcInit, .-NandcInit
.align 2
.global NandcGetTimeCfg
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcGetTimeCfg, %function
NandcGetTimeCfg:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L405
+ ldr ip, .L406
str lr, [sp, #-4]!
.save {lr}
- ldr lr, [ip, #80]
+ ldr lr, [ip, #88]
ldr lr, [lr, #4]
str lr, [r0]
- ldr r0, [ip, #80]
+ ldr r0, [ip, #88]
ldr r0, [r0]
str r0, [r1]
- ldr r1, [ip, #80]
+ ldr r1, [ip, #88]
ldr r1, [r1, #304]
str r1, [r2]
- ldr r1, [ip, #80]
+ ldr r1, [ip, #88]
ldr r2, [r1, #308]
ldr r1, [r1, #344]
uxtb r2, r2
- orr r2, r2, r1, asl #16
+ orr r2, r2, r1, lsl #16
str r2, [r3]
ldr pc, [sp], #4
-.L406:
+.L407:
.align 2
-.L405:
+.L406:
.word .LANCHOR0
.fnend
.size NandcGetTimeCfg, .-NandcGetTimeCfg
.align 2
.global NandcBchSel
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcBchSel, %function
NandcBchSel:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L415
- mov r1, #1
- ldr r2, [r3, #80]
- str r0, [r3, #2308]
- mov r3, #0
- str r1, [r2, #8]
- mov r1, #16
- cmp r0, r1
- bfi r3, r1, #8, #8
- bfc r3, #18, #1
- bne .L408
-.L411:
+ ldr r3, .L416
+ mov ip, #1
+ mov r1, #0
+ ldr r2, [r3, #88]
+ str r0, [r3, #2312]
+ mov r3, r1
+ str ip, [r2, #8]
+ mov ip, #16
+ cmp r0, ip
+ bfi r3, ip, #8, #8
+ bfi r3, r1, #18, #1
+ bne .L409
+.L412:
bfc r3, #4, #1
- b .L409
-.L408:
- cmp r0, #24
- orreq r3, r3, #16
- beq .L409
- cmp r0, #40
- orr r3, r3, #262144
- orr r3, r3, #16
- beq .L411
-.L409:
+.L410:
orr r3, r3, #1
str r3, [r2, #12]
bx lr
-.L416:
+.L409:
+ cmp r0, #24
+ orreq r3, r3, #16
+ beq .L410
+ cmp r0, #40
+ orr r3, r3, #262144
+ orr r3, r3, #16
+ bne .L410
+ b .L412
+.L417:
.align 2
-.L415:
+.L416:
.word .LANCHOR0
.fnend
.size NandcBchSel, .-NandcBchSel
.align 2
.global FlashBchSel
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashBchSel, %function
FlashBchSel:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L418
- strb r0, [r3, #2312]
+ ldr r3, .L419
+ strb r0, [r3, #2316]
b NandcBchSel
-.L419:
+.L420:
.align 2
-.L418:
+.L419:
.word .LANCHOR0
.fnend
.size FlashBchSel, .-FlashBchSel
.align 2
.global ftl_flash_resume
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_flash_resume, %function
ftl_flash_resume:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L429
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r3, .L430
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r5, #0
- ldr r2, [r3, #80]
+ ldr r6, .L430+4
mov r4, r3
- ldr r1, [r3, #84]
- ldr r6, .L429+4
- str r1, [r2]
- ldr r1, [r3, #88]
- ldr r2, [r3, #80]
- str r1, [r2, #4]
+ ldr r2, [r3, #88]
ldr r1, [r3, #92]
- str r1, [r2, #8]
+ str r1, [r2]
ldr r1, [r3, #96]
- str r1, [r2, #12]
+ ldr r2, [r3, #88]
+ str r1, [r2, #4]
ldr r1, [r3, #100]
- str r1, [r2, #304]
+ str r1, [r2, #8]
ldr r1, [r3, #104]
- str r1, [r2, #308]
+ str r1, [r2, #12]
ldr r1, [r3, #108]
- str r1, [r2, #336]
+ str r1, [r2, #304]
ldr r1, [r3, #112]
+ str r1, [r2, #308]
+ ldr r1, [r3, #116]
+ str r1, [r2, #336]
+ ldr r1, [r3, #120]
str r1, [r2, #344]
-.L422:
- ldrb r3, [r6, r5, asl #3] @ zero_extendqisi2
+.L423:
+ ldrb r3, [r6, r5, lsl #3] @ zero_extendqisi2
sub r3, r3, #1
uxtb r3, r3
cmp r3, #253
- bhi .L421
+ bhi .L422
uxtb r0, r5
bl FlashReset
-.L421:
+.L422:
add r5, r5, #1
cmp r5, #4
- bne .L422
- ldrb r3, [r4, #2252] @ zero_extendqisi2
- ldr r5, .L429
+ bne .L423
+ ldrb r3, [r4, #2256] @ zero_extendqisi2
cmp r3, #0
- beq .L423
+ beq .L424
mov r0, #1
bl NandcSetMode
- ldrb r0, [r5, #2229] @ zero_extendqisi2
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
bl FlashSetInterfaceMode
- ldrb r0, [r5, #2229] @ zero_extendqisi2
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
bl NandcSetMode
- ldrb r0, [r5, #101] @ zero_extendqisi2
+ ldrb r0, [r4, #109] @ zero_extendqisi2
bl NandcSetDdrPara
-.L423:
- ldr r3, [r4, #44]
- ldmfd sp!, {r4, r5, r6, lr}
+.L424:
+ ldr r3, [r4, #48]
+ pop {r4, r5, r6, lr}
ldrb r0, [r3, #20] @ zero_extendqisi2
b FlashBchSel
-.L430:
+.L431:
.align 2
-.L429:
+.L430:
.word .LANCHOR0
- .word .LANCHOR0+2068
+ .word .LANCHOR0+2072
.fnend
.size ftl_flash_resume, .-ftl_flash_resume
.align 2
.global ftl_nandc_get_irq_status
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_nandc_get_irq_status, %function
ftl_nandc_get_irq_status:
.fnstart
@@ -2464,6 +2669,9 @@
.size ftl_nandc_get_irq_status, .-ftl_nandc_get_irq_status
.align 2
.global rk_nandc_flash_ready
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_nandc_flash_ready, %function
rk_nandc_flash_ready:
.fnstart
@@ -2481,6 +2689,9 @@
.size rk_nandc_flash_ready, .-rk_nandc_flash_ready
.align 2
.global NandcIqrWaitFlashReady
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcIqrWaitFlashReady, %function
NandcIqrWaitFlashReady:
.fnstart
@@ -2492,6 +2703,9 @@
.size NandcIqrWaitFlashReady, .-NandcIqrWaitFlashReady
.align 2
.global rk_nandc_flash_xfer_completed
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_nandc_flash_xfer_completed, %function
rk_nandc_flash_xfer_completed:
.fnstart
@@ -2509,6 +2723,9 @@
.size rk_nandc_flash_xfer_completed, .-rk_nandc_flash_xfer_completed
.align 2
.global NandcSendDumpDataStart
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSendDumpDataStart, %function
NandcSendDumpDataStart:
.fnstart
@@ -2518,10 +2735,10 @@
ldr r2, [r0, #16]
.pad #8
sub sp, sp, #8
- ldr r3, .L437
+ ldr r3, .L438
str r2, [sp, #4]
ldr r2, [sp, #4]
- bic r2, r2, #4
+ bfc r2, #2, #1
str r2, [sp, #4]
ldr r2, [sp, #4]
str r2, [r0, #16]
@@ -2531,14 +2748,17 @@
add sp, sp, #8
@ sp needed
bx lr
-.L438:
+.L439:
.align 2
-.L437:
+.L438:
.word 538969130
.fnend
.size NandcSendDumpDataStart, .-NandcSendDumpDataStart
.align 2
.global NandcSendDumpDataDone
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcSendDumpDataDone, %function
NandcSendDumpDataDone:
.fnstart
@@ -2547,12 +2767,12 @@
@ link register save eliminated.
.pad #8
sub sp, sp, #8
-.L440:
+.L441:
ldr r3, [r0, #8]
str r3, [sp, #4]
ldr r3, [sp, #4]
tst r3, #1048576
- beq .L440
+ beq .L441
add sp, sp, #8
@ sp needed
bx lr
@@ -2560,155 +2780,152 @@
.size NandcSendDumpDataDone, .-NandcSendDumpDataDone
.align 2
.global NandcXferStart
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcXferStart, %function
NandcXferStart:
.fnstart
- @ args = 8, pretend = 0, frame = 24
+ @ args = 8, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov lr, #16
- ldr r5, .L462
- mov r4, #0
- .pad #28
- sub sp, sp, #28
- add r0, r5, r0, asl #3
- ldr r8, [sp, #64]
- ldr r6, [r0, #12]
- ldrb r0, [r0, #16] @ zero_extendqisi2
- ldr ip, [sp, #68]
+ mov ip, #16
+ ldr r4, .L463
+ mov r5, #0
+ .pad #20
+ sub sp, sp, #20
+ ldr r8, [sp, #56]
+ ldr r6, [r4, r0, lsl #3]
+ add r0, r4, r0, lsl #3
ldr r7, [r6, #12]
- bfi r7, lr, #8, #8
- bfi r7, r4, #3, #1
- bfi r4, r1, #1, #1
- orr r4, r4, #8
+ ldrb r0, [r0, #4] @ zero_extendqisi2
+ bfi r7, ip, #8, #8
+ bfi r7, r5, #3, #1
+ bfi r5, r1, #1, #1
bfi r7, r0, #5, #3
+ orr r5, r5, #8
mov r0, #1
- bfi r4, r0, #5, #2
- orr r4, r4, #536870912
- mov r3, r3, lsr r0
- orr r4, r4, #1024
- bfi r4, r3, #4, #1
- ldr r3, [r5, #2260]
+ bfi r5, r0, #5, #2
+ lsr r3, r3, r0
+ orr r5, r5, #536870912
+ orr r5, r5, #1024
+ bfi r5, r3, #4, #1
+ ldr r3, [r4, #2264]
cmp r3, #3
- bls .L445
+ bls .L446
ldr r3, [r6, #16]
- str r3, [sp, #20]
- ldr r3, [sp, #20]
- bic r3, r3, #4
- str r3, [sp, #20]
- adds r3, ip, #0
- movne r3, #1
- cmp ip, #0
- cmpeq r8, #0
- str r3, [sp, #8]
- beq .L446
+ str r3, [sp, #12]
+ ldr r3, [sp, #12]
+ bfc r3, #2, #1
+ str r3, [sp, #12]
+ ldr r3, [sp, #60]
+ cmp r8, #0
+ cmpeq r3, #0
+ beq .L447
cmp r1, #0
- bne .L447
-.L455:
+ bne .L448
+.L456:
add r2, r2, #1
cmp r8, #0
- mov r2, r2, asr #1
+ asr r2, r2, #1
movne r0, r8
- bfi r4, r2, #22, #6
- ldreq r0, [r5, #2272]
- b .L449
+ bfi r5, r2, #22, #6
+ ldreq r0, [r4, #2276]
+.L450:
+ ldr r3, [r4, #2280]
+ ubfx r10, r5, #22, #5
+ mov r9, r1
+ mov r2, r1
+ lsl r1, r10, #10
+ str r0, [r4, #2284]
+ str r3, [r4, #2288]
+ bl rknand_dma_map_single
+ mov r2, r9
+ str r0, [r4, #2292]
+ lsl r1, r10, #7
+ ldr r0, [r4, #2288]
+ bl rknand_dma_map_single
+ mov r3, #1
+ str r0, [r4, #2296]
+ str r3, [r4, #2300]
+ mov r2, #16
+ ldr r3, [r4, #2292]
+ tst r8, #3
+ clz r1, r9
+ lsr r1, r1, #5
+ str r3, [r6, #20]
+ ldr r3, [r4, #2296]
+ str r3, [r6, #24]
+ mov r3, #0
+ str r3, [sp, #12]
+ ldr r3, [sp, #12]
+ bfi r3, r2, #9, #5
+ moveq r2, #2
+ str r3, [sp, #12]
+ ldr r3, [sp, #12]
+ orr r3, r3, #448
+ str r3, [sp, #12]
+ ldreq r3, [sp, #12]
+ bfieq r3, r2, #3, #3
+ streq r3, [sp, #12]
+ ldr r3, [sp, #12]
+ orr r3, r3, #4
+ str r3, [sp, #12]
+ ldr r3, [sp, #12]
+ bfi r3, r1, #1, #1
+ str r3, [sp, #12]
+ ldr r3, [sp, #12]
+ orr r3, r3, #1
+ str r3, [sp, #12]
.L447:
- ldr r3, [r5, #2308]
- mov r9, r5
+ ldr r3, [sp, #12]
+ str r3, [r6, #16]
+.L446:
+ str r7, [r6, #12]
+ str r5, [r6, #8]
+ orr r5, r5, #4
+ str r5, [r6, #8]
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L448:
+ ldr r3, [r4, #2312]
+ lsr r10, r2, #1
+ ldr ip, [sp, #60]
cmp r3, #25
movcc r3, #64
movcs r3, #128
str r3, [sp, #4]
- mov r3, r2, lsr #1
- str r3, [sp, #12]
mov r3, #0
mov r0, r3
-.L451:
- ldr lr, [sp, #12]
- cmp r0, lr
- bcs .L455
- ldr lr, [sp, #8]
- mov r10, r3, lsr #2
+.L452:
+ cmp r0, r10
+ bcs .L456
+ ldr lr, [sp, #60]
add r0, r0, #1
cmp lr, #0
- ldrneh fp, [ip, #2]
- mvneq fp, #0
- ldrneh lr, [ip], #4
- ldreq lr, [r9, #2276]
- orrne lr, lr, fp, asl #16
- ldrne fp, [r9, #2276]
- streq fp, [lr, r10, asl #2]
- strne lr, [fp, r10, asl #2]
+ bic lr, r3, #3
+ ldrne fp, [ip], #4 @ unaligned
+ mvneq r9, #0
+ ldrne r9, [r4, #2280]
+ ldreq fp, [r4, #2280]
+ strne fp, [r9, lr]
+ streq r9, [fp, lr]
ldr lr, [sp, #4]
add r3, r3, lr
- b .L451
-.L449:
- ldr r3, [r5, #2276]
- ubfx r10, r4, #22, #5
- mov r9, r1
- str r0, [r5, #2280]
- mov r2, r9
- mov r1, r10, asl #10
- str r3, [r5, #2284]
- bl rknand_dma_map_single
- mov r2, r9
- mov r1, r10, asl #7
- clz r9, r9
- mov r9, r9, lsr #5
- str r0, [r5, #2288]
- ldr r0, [r5, #2284]
- bl rknand_dma_map_single
- mov r3, #1
- str r3, [r5, #2296]
- tst r8, #3
- ldr r3, [r5, #2288]
- str r0, [r5, #2292]
- str r3, [r6, #20]
- ldr r3, [r5, #2292]
- str r3, [r6, #24]
- mov r3, #0
- str r3, [sp, #20]
- ldr r3, [sp, #20]
- bic r3, r3, #15872
- orr r3, r3, #8192
- str r3, [sp, #20]
- ldr r3, [sp, #20]
- orr r3, r3, #448
- str r3, [sp, #20]
- ldreq r3, [sp, #20]
- biceq r3, r3, #56
- orreq r3, r3, #16
- streq r3, [sp, #20]
- ldr r3, [sp, #20]
- orr r3, r3, #4
- str r3, [sp, #20]
- ldr r3, [sp, #20]
- bic r3, r3, #2
- orr r9, r3, r9, asl #1
- str r9, [sp, #20]
- ldr r3, [sp, #20]
- orr r3, r3, #1
- str r3, [sp, #20]
-.L446:
- ldr r3, [sp, #20]
- str r3, [r6, #16]
-.L445:
- str r7, [r6, #12]
- str r4, [r6, #8]
- orr r4, r4, #4
- str r4, [r6, #8]
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L463:
+ b .L452
+.L464:
.align 2
-.L462:
+.L463:
.word .LANCHOR0
.fnend
.size NandcXferStart, .-NandcXferStart
.align 2
.global Ftl_log2
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_log2, %function
Ftl_log2:
.fnstart
@@ -2717,20 +2934,24 @@
@ link register save eliminated.
mov r1, #0
mov r2, #1
-.L465:
+.L466:
cmp r2, r0
uxth r3, r1
add r1, r1, #1
- movls r2, r2, asl #1
- bls .L465
-.L467:
+ bls .L467
sub r0, r3, #1
uxth r0, r0
bx lr
+.L467:
+ lsl r2, r2, #1
+ b .L466
.fnend
.size Ftl_log2, .-Ftl_log2
.align 2
.global FtlPrintInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlPrintInfo, %function
FtlPrintInfo:
.fnstart
@@ -2742,507 +2963,534 @@
.size FtlPrintInfo, .-FtlPrintInfo
.align 2
.global FtlSysBlkNumInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlSysBlkNumInit, %function
FtlSysBlkNumInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L471
- cmp r0, #23
- movw r1, #2330
- add r2, r3, #2320
- movls r0, #24
+ ldr r3, .L470
+ movw r2, #2324
+ movw r1, #2334
+ cmp r0, #24
+ movcc r0, #24
+ ldrh r2, [r3, r2]
ldrh r1, [r3, r1]
- ldrh r2, [r2]
- str r0, [r3, #2316]
- mul r2, r2, r0
- rsb r0, r0, r1
- movw r1, #2328
+ str r0, [r3, #2320]
+ mul r2, r0, r2
+ sub r0, r1, r0
+ movw r1, #2332
strh r0, [r3, r1] @ movhi
mov r0, #0
- ldr r1, [r3, #2336]
- str r2, [r3, #2324]
- rsb r2, r2, r1
- str r2, [r3, #2332]
+ ldr r1, [r3, #2340]
+ str r2, [r3, #2328]
+ sub r2, r1, r2
+ str r2, [r3, #2336]
bx lr
-.L472:
- .align 2
.L471:
+ .align 2
+.L470:
.word .LANCHOR0
.fnend
.size FtlSysBlkNumInit, .-FtlSysBlkNumInit
.align 2
.global FtlConstantsInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlConstantsInit, %function
FtlConstantsInit:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2340
- ldr r4, .L502
- movw r1, #2344
- ldrh r6, [r0, #8]
+ movw r3, #2344
+ ldr r4, .L500
+ movw r1, #2348
mov r5, r0
- ldrh r2, [r0, #10]
.pad #20
sub sp, sp, #20
+ ldrh r6, [r0, #8]
+ ldrh r2, [r0, #10]
ldrh lr, [r0, #14]
strh r6, [r4, r3] @ movhi
- movw r3, #2342
+ movw r3, #2346
strh r2, [r4, r3] @ movhi
ldrh r3, [r0, #12]
- ldr r0, .L502+4
+ ldr r0, .L500+4
strh r3, [r4, r1] @ movhi
- movw r1, #2330
+ movw r1, #2334
strh lr, [r4, r1] @ movhi
mov r1, #0
-.L474:
+.L473:
strb r1, [r1, r0]
add r1, r1, #1
cmp r1, #32
- bne .L474
+ bne .L473
ldrh r0, [r5, #14]
ldrh r1, [r5, #20]
cmp r1, r0, lsr #8
- bcs .L475
+ bcs .L474
uxtb r10, r3
- ldr r9, .L502+4
- mov r1, r10, asl #1
+ ldr r9, .L500+4
+ lsl r1, r10, #1
uxtb r1, r1
- str r1, [sp, #4]
+ str r1, [sp]
sub r1, r2, #1
mul r1, r3, r1
- str r1, [sp]
+ str r1, [sp, #8]
mov r1, #0
-.L476:
+.L475:
cmp r1, r3
- bcs .L478
- ldr ip, [sp]
- uxtb r0, r1
- rsb r7, r3, r1
- add ip, r1, ip
+ bcs .L477
+ ldr ip, [sp, #8]
+ sub r7, r1, r3
add r7, r9, r7
- add ip, r9, ip
- str ip, [sp, #8]
- mov ip, #0
+ uxtb r0, r1
str r7, [sp, #12]
+ add ip, r1, ip
+ add ip, r9, ip
+ str ip, [sp, #4]
+ mov ip, #0
mov r8, ip
-.L479:
- cmp r8, r2
- add ip, ip, r3
- bcs .L501
+ b .L478
+.L476:
ldr r7, [sp, #12]
- add fp, r0, r10
+ add fp, r10, r0
add r8, r8, #1
strb r0, [r7, ip]
- ldr r7, [sp, #8]
- strb fp, [r7, ip]
ldr r7, [sp, #4]
- add r0, r0, r7
+ strb fp, [r7, ip]
+ ldr r7, [sp]
+ add r0, r7, r0
uxtb r0, r0
- b .L479
-.L501:
- add r1, r1, #1
- b .L476
.L478:
- movw r1, #2342
- mov r2, r2, asl #1
+ cmp r8, r2
+ add ip, ip, r3
+ bcc .L476
+ add r1, r1, #1
+ b .L475
+.L477:
+ lsl r2, r2, #1
+ movw r1, #2346
+ lsr lr, lr, #1
strh r2, [r4, r1] @ movhi
- movw r2, #2330
- mov lr, lr, lsr #1
+ movw r2, #2334
strh lr, [r4, r2] @ movhi
-.L475:
- cmp r6, #1
- movw r2, #2380
+.L474:
+ ldr fp, .L500+8
+ movw r2, #2382
+ ldrb r9, [r4, #36] @ zero_extendqisi2
mov r1, #5
strh r1, [r4, r2] @ movhi
- movw r1, #2382
- mov r0, #0
- strh r0, [r4, r1] @ movhi
- ldreq r1, .L502
- ldrb r9, [r4] @ zero_extendqisi2
- ldr r8, .L502+8
- streqh r6, [r1, r2] @ movhi
- movw r1, #2342
- ldrh r7, [r4, r1]
+ cmp r6, #1
+ mov r1, #0
+ strheq r6, [r4, r2] @ movhi
+ strh r1, [fp] @ movhi
cmp r9, #0
- mov r2, #4352
- strh r2, [r8] @ movhi
- movne r2, #384
- strneh r2, [r8] @ movhi
- smulbb r7, r7, r3
- ldr r2, .L502
- ldrh r10, [r5, #16]
- add r1, r2, #2320
- str r2, [sp, #8]
- uxth r7, r7
- strh r7, [r1] @ movhi
- movw r1, #2330
- ldrh r6, [r4, r1]
- movw r1, #2386
- smulbb r0, r7, r10
- smulbb r3, r6, r3
- strh r3, [r4, r1] @ movhi
- movw r3, #2388
+ mov r1, #4352
+ movw r2, #2386
+ strh r1, [r4, r2] @ movhi
+ movne r1, #384
+ strhne r1, [r4, r2] @ movhi
+ movw r2, #2346
+ ldrh r7, [r4, r2]
+ movw r2, #2324
+ ldrh r8, [r5, #16]
ldrh r1, [r5, #18]
- strh r10, [r4, r3] @ movhi
- movw r3, #2390
- strh r1, [r4, r3] @ movhi
- movw r3, #2392
- strh r0, [r4, r3] @ movhi
- movw r0, #2394
- ldrh r3, [r5, #20]
+ smulbb r7, r7, r3
str r1, [sp, #4]
- strh r3, [r4, r0] @ movhi
+ uxth r7, r7
+ strh r7, [r4, r2] @ movhi
+ movw r2, #2334
+ ldrh r6, [r4, r2]
+ movw r2, #2388
+ smulbb r3, r3, r6
+ strh r3, [r4, r2] @ movhi
+ smulbb r2, r7, r8
+ movw r3, #2390
+ strh r8, [r4, r3] @ movhi
+ movw r3, #2392
+ strh r1, [r4, r3] @ movhi
+ movw r3, #2394
+ strh r2, [r4, r3] @ movhi
+ movw r2, #2396
+ ldrh r3, [r5, #20]
mov r0, r3
+ strh r3, [r4, r2] @ movhi
str r3, [sp]
bl Ftl_log2
- movw ip, #2398
- cmp r6, #1024
ldr r3, [sp]
- mov fp, r0
- movw r0, #2396
- ldr r2, [sp, #8]
- strh fp, [r4, r0] @ movhi
- mov r0, r3, asl #9
+ movw r2, #2398
+ strh r0, [r4, r2] @ movhi
+ mov r10, r0
+ ldr r0, .L500+12
+ cmp r6, #1024
ldr r1, [sp, #4]
- uxth r0, r0
- strh r0, [r4, ip] @ movhi
- add ip, r2, #2400
- mov r0, r0, lsr #8
- strh r0, [ip] @ movhi
+ lsl r2, r3, #9
+ uxth r2, r2
+ mul r1, r3, r1
+ strh r2, [r0] @ movhi
+ lsr r2, r2, #8
movw r0, #2402
- ldrh ip, [r5, #26]
- mul r1, r1, r3
- ldr r5, .L502
- strh ip, [r4, r0] @ movhi
- movwhi ip, #2382
- mul r0, r6, r7
- str r0, [r4, #2336]
- uxtbhi r0, r6
- strhih r0, [r2, ip] @ movhi
- movw r2, #2382
- ldrh r2, [r4, r2]
- ldrh r0, [r8]
- rsb r2, r2, r6
- mov r6, r6, asl #6
- mul r2, r2, r7
- mov r0, r0, asl #3
+ strh r2, [r4, r0] @ movhi
+ movw r2, #2404
+ ldrh r0, [r5, #26]
+ strh r0, [r4, r2] @ movhi
+ mul r2, r6, r7
+ str r2, [r4, #2340]
+ uxtbhi r2, r6
+ strhhi r2, [fp] @ movhi
+ ldrh r2, [fp]
+ sub r2, r6, r2
+ lsl r6, r6, #6
+ mul r2, r7, r2
mul r2, r3, r2
- mul r10, r10, r2
- mov r10, r10, asr #11
- str r10, [r4, #2404]
+ mul r8, r8, r2
+ movw r2, #2386
+ ldrh r0, [r4, r2]
+ asr r8, r8, #11
+ lsl r0, r0, #3
+ str r8, [r4, #2408]
bl __aeabi_idiv
- movw r3, #2408
- mov r1, r7
- ldr r10, .L502
uxth r0, r0
+ movw r3, #2412
+ mov r1, r7
cmp r0, #4
- strhih r0, [r5, r3] @ movhi
movls r2, #4
- strlsh r2, [r5, r3] @ movhi
+ strhhi r0, [r4, r3] @ movhi
+ strhls r2, [r4, r3] @ movhi
cmp r9, #0
- movw r2, #2410
- movne r3, #640
- strneh r3, [r8] @ movhi
- ldrh r3, [r8]
- mov r3, r3, asr fp
- add fp, fp, #9
- mov r0, r6, asr fp
+ movne r2, #640
+ movwne r3, #2386
+ strhne r2, [r4, r3] @ movhi
+ movw r3, #2386
+ ldrh r3, [r4, r3]
+ movw r2, #2414
+ asr r3, r3, r10
+ add r10, r10, #9
+ asr r6, r6, r10
add r3, r3, #2
strh r3, [r4, r2] @ movhi
+ ldr r3, .L500+16
+ strh r6, [r3] @ movhi
+ uxth r6, r6
+ mul r3, r6, r7
+ add r6, r6, #8
+ str r3, [r4, #2420]
movw r3, #2412
- strh r0, [r4, r3] @ movhi
- uxth r0, r0
- add r6, r0, #8
- mul r3, r7, r0
- str r3, [r4, #2416]
- movw r3, #2408
ldrh r0, [r4, r3]
bl __aeabi_uidiv
- cmp r7, #1
uxtah r0, r6, r0
- ldr r6, .L502
+ cmp r7, #1
+ add r3, r4, #2320
addeq r0, r0, #4
- str r0, [r10, #2316]
- ldr r3, [r4, #2316]
- uxth r0, r3
+ str r0, [r4, #2320]
+ ldrh r0, [r3]
bl FtlSysBlkNumInit
- ldr r3, [r4, #2316]
- ldr r2, [r4, #2332]
+ ldr r5, [r4, #2336]
+ movw r2, #2390
+ ldr r3, [r4, #2320]
mov r0, #2048
- str r3, [r4, #2420]
- movw r3, #2388
- ldrh r3, [r4, r3]
- mov r2, r2, asl #2
- mul r3, r3, r2
- movw r2, #2396
+ str r3, [r4, #2424]
+ lsl r3, r5, #2
ldrh r5, [r4, r2]
- add r5, r5, #9
- mov r5, r3, lsr r5
- movw r3, #2424
+ mul r5, r5, r3
+ movw r3, #2398
+ ldrh r3, [r4, r3]
+ add r3, r3, #9
+ lsr r5, r5, r3
+ movw r3, #2428
add r5, r5, #2
uxth r5, r5
strh r5, [r4, r3] @ movhi
- movw r3, #2394
- ldrh r7, [r4, r3]
- mov r1, r7
+ movw r3, #2396
+ ldrh r6, [r4, r3]
+ mov r1, r6
bl __aeabi_idiv
- movw r1, #2408
+ movw r1, #2412
+ movw r3, #2430
ldrh r2, [r4, r1]
- movw r3, #2426
- ldrb ip, [r4, #144] @ zero_extendqisi2
- cmp ip, #0
strh r0, [r4, r3] @ movhi
mov r3, #0
- str r3, [r4, #2428]
+ str r3, [r4, #2432]
+ ldrb ip, [r4, #152] @ zero_extendqisi2
add r3, r2, #3
strh r3, [r4, r1] @ movhi
+ ldr r3, [r4, #2420]
+ cmp ip, #0
addne r2, r2, #4
- ldr r3, [r4, #2416]
- strneh r2, [r6, r1] @ movhi
add r0, r3, #3
+ strhne r2, [r4, r1] @ movhi
+ str r0, [r4, #2420]
addne r3, r3, #5
- str r0, [r4, #2416]
- bne .L500
+ bne .L499
cmp r0, #7
- bhi .L489
+ bhi .L488
mov r3, #8
-.L500:
- str r3, [r6, #2416]
-.L489:
- ldr r2, .L502+12
+.L499:
+ str r3, [r4, #2420]
+.L488:
+ movw r2, #2436
mov r3, #0
- mov r0, #0
- strh r3, [r2] @ movhi
- movw r3, #2328
+ strh r3, [r4, r2] @ movhi
+ movw r3, #2332
ldrh r1, [r4, r3]
- mov r3, r1, lsr #3
- add r3, r3, r1, asl #1
+ mov r0, #0
+ lsr r3, r1, #3
+ add r3, r3, r1, lsl #1
add r3, r3, #52
- add r5, r3, r5, asl #2
- cmp r5, r7, asl #9
+ add r5, r3, r5, lsl #2
+ cmp r5, r6, lsl #9
movcc r3, #1
- strcch r3, [r2] @ movhi
+ strhcc r3, [r4, r2] @ movhi
add sp, sp, #20
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L503:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L501:
.align 2
-.L502:
+.L500:
.word .LANCHOR0
- .word .LANCHOR0+2348
+ .word .LANCHOR0+2350
.word .LANCHOR0+2384
- .word .LANCHOR0+2432
+ .word .LANCHOR0+2400
+ .word .LANCHOR0+2416
.fnend
.size FtlConstantsInit, .-FtlConstantsInit
.align 2
.global IsBlkInVendorPart
+ .syntax unified
+ .arm
+ .fpu softvfp
.type IsBlkInVendorPart, %function
IsBlkInVendorPart:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L511
- movw r3, #2434
+ ldr r2, .L509
+ movw r3, #2438
ldrh r3, [r2, r3]
cmp r3, #0
- beq .L510
- movw r1, #2408
- ldr r3, [r2, #2436]
+ beq .L508
+ movw r1, #2412
+ ldr r3, [r2, #2440]
ldrh r2, [r2, r1]
- add r2, r3, r2, asl #1
-.L506:
+ add r2, r3, r2, lsl #1
+.L504:
cmp r3, r2
- beq .L510
+ bne .L505
+.L508:
+ mov r0, #0
+ bx lr
+.L505:
ldrh r1, [r3], #2
- cmp r1, r0
- bne .L506
+ cmp r0, r1
+ bne .L504
mov r0, #1
bx lr
.L510:
- mov r0, #0
- bx lr
-.L512:
.align 2
-.L511:
+.L509:
.word .LANCHOR0
.fnend
.size IsBlkInVendorPart, .-IsBlkInVendorPart
.align 2
.global FtlCacheMetchLpa
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlCacheMetchLpa, %function
FtlCacheMetchLpa:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L520
- ldr r3, [r2, #2440]
+ ldr r2, .L521
+ ldr r3, [r2, #2444]
cmp r3, #0
- beq .L516
- stmfd sp!, {r4, r5, lr}
+ beq .L514
+ push {r4, r5, lr}
.save {r4, r5, lr}
mov r5, #36
- ldr r4, [r2, #2444]
+ ldr r4, [r2, #2448]
mov r2, #0
-.L515:
+.L513:
mla ip, r5, r2, r4
ldr lr, [ip, #16]
- cmp lr, r0
- movcc ip, #0
- movcs ip, #1
cmp lr, r1
movhi ip, #0
+ movls ip, #1
+ cmp lr, r0
+ movcc ip, #0
cmp ip, #0
- bne .L517
- add r2, r2, #1
- cmp r2, r3
bne .L515
+ add r2, r2, #1
+ cmp r3, r2
+ bne .L513
mov r0, ip
- ldmfd sp!, {r4, r5, pc}
-.L516:
+ pop {r4, r5, pc}
+.L514:
mov r0, r3
bx lr
-.L517:
+.L515:
mov r0, #1
- ldmfd sp!, {r4, r5, pc}
-.L521:
+ pop {r4, r5, pc}
+.L522:
.align 2
-.L520:
+.L521:
.word .LANCHOR0
.fnend
.size FtlCacheMetchLpa, .-FtlCacheMetchLpa
.align 2
.global FtlGetCap
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGetCap, %function
FtlGetCap:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L523
- ldr r0, [r3, #2428]
+ ldr r3, .L524
+ ldr r0, [r3, #2432]
bx lr
-.L524:
+.L525:
.align 2
-.L523:
+.L524:
.word .LANCHOR0
.fnend
.size FtlGetCap, .-FtlGetCap
.align 2
.global FtlGetCapacity
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGetCapacity, %function
FtlGetCapacity:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L526
- ldr r0, [r3, #2428]
+ ldr r3, .L527
+ ldr r0, [r3, #2432]
bx lr
-.L527:
+.L528:
.align 2
-.L526:
+.L527:
.word .LANCHOR0
.fnend
.size FtlGetCapacity, .-FtlGetCapacity
.align 2
.global ftl_get_density
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_get_density, %function
ftl_get_density:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L529
- ldr r0, [r3, #2428]
+ ldr r3, .L530
+ ldr r0, [r3, #2432]
bx lr
-.L530:
+.L531:
.align 2
-.L529:
+.L530:
.word .LANCHOR0
.fnend
.size ftl_get_density, .-ftl_get_density
.align 2
.global FtlGetLpn
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGetLpn, %function
FtlGetLpn:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L532
- ldr r0, [r3, #2448]
+ ldr r3, .L533
+ ldr r0, [r3, #2452]
bx lr
-.L533:
+.L534:
.align 2
-.L532:
+.L533:
.word .LANCHOR0
.fnend
.size FtlGetLpn, .-FtlGetLpn
.align 2
.global FtlBbmMapBadBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbmMapBadBlock, %function
FtlBbmMapBadBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, lr}
- .save {r4, r5, r6, lr}
- .pad #8
- movw r3, #2386
- ldr r5, .L536
- mov r6, r0
- ldrh r4, [r5, r3]
- mov r1, r4
+ push {r0, r1, r2, r4, r5, r6, r7, lr}
+ .save {r4, r5, r6, r7, lr}
+ .pad #12
+ movw r3, #2388
+ ldr r4, .L537
+ mov r5, r0
+ ldrh r7, [r4, r3]
+ mov r1, r7
bl __aeabi_uidiv
- uxth r2, r0
- smulbb r3, r2, r4
- add r1, r5, r2, asl #2
- mov r4, #1
- ldr ip, [r1, #2480]
- rsb r3, r3, r6
- uxth r3, r3
- and r1, r3, #31
- mov lr, r3, lsr #5
- ldr r0, [ip, lr, asl #2]
- orr r1, r0, r4, asl r1
- ldr r0, .L536+4
- str r1, [ip, lr, asl #2]
- str r1, [sp]
- mov r1, r6
+ uxth r6, r0
+ mov r1, r7
+ mov r0, r5
+ bl __aeabi_uidivmod
+ add r2, r4, r6, lsl #2
+ uxth r3, r1
+ ldr r2, [r2, #2484]
+ lsr r1, r3, #5
+ and ip, r3, #31
+ mov lr, #1
+ ldr r0, [r2, r1, lsl #2]
+ orr r0, r0, lr, lsl ip
+ str r0, [r2, r1, lsl #2]
+ mov r2, r6
+ str r0, [sp]
+ mov r1, r5
+ ldr r0, .L537+4
bl printk
- add r2, r5, #2448
+ add r3, r4, #2448
mov r0, #0
- ldrh r3, [r2, #10]
- add r3, r3, r4
- strh r3, [r2, #10] @ movhi
- add sp, sp, #8
+ ldrh r2, [r3, #14]
+ add r2, r2, #1
+ strh r2, [r3, #14] @ movhi
+ add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, pc}
-.L537:
+ pop {r4, r5, r6, r7, pc}
+.L538:
.align 2
-.L536:
+.L537:
.word .LANCHOR0
.word .LC2
.fnend
.size FtlBbmMapBadBlock, .-FtlBbmMapBadBlock
- .global __aeabi_uidivmod
.align 2
.global FtlBbmIsBadBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbmIsBadBlock, %function
FtlBbmIsBadBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- movw r3, #2386
- ldr r5, .L540
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ movw r3, #2388
+ ldr r5, .L541
mov r7, r0
ldrh r6, [r5, r3]
mov r1, r6
@@ -3251,23 +3499,26 @@
uxth r4, r1
mov r1, r6
bl __aeabi_uidiv
- mov r2, r4, lsr #5
- and r4, r4, #31
uxth r0, r0
- add r5, r5, r0, asl #2
- ldr r3, [r5, #2480]
- ldr r0, [r3, r2, asl #2]
- mov r0, r0, lsr r4
+ lsr r2, r4, #5
+ add r5, r5, r0, lsl #2
+ and r4, r4, #31
+ ldr r3, [r5, #2484]
+ ldr r0, [r3, r2, lsl #2]
+ lsr r0, r0, r4
and r0, r0, #1
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L541:
+ pop {r4, r5, r6, r7, r8, pc}
+.L542:
.align 2
-.L540:
+.L541:
.word .LANCHOR0
.fnend
.size FtlBbmIsBadBlock, .-FtlBbmIsBadBlock
.align 2
.global FtlBbtInfoPrint
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbtInfoPrint, %function
FtlBbtInfoPrint:
.fnstart
@@ -3279,34 +3530,37 @@
.size FtlBbtInfoPrint, .-FtlBbtInfoPrint
.align 2
.global FtlBbtCalcTotleCnt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbtCalcTotleCnt, %function
FtlBbtCalcTotleCnt:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r3, .L552
+ movw r2, #2388
+ movw r1, #2346
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- movw r3, #2386
- ldr r4, .L552
mov r5, #0
- ldrh r6, [r4, r3]
- movw r3, #2342
- ldrh r3, [r4, r3]
mov r4, r5
- mul r6, r3, r6
-.L544:
+ ldrh r2, [r3, r2]
+ ldrh r6, [r3, r1]
+ mul r6, r6, r2
+.L545:
uxth r0, r5
cmp r0, r6
- bge .L551
+ blt .L547
+ mov r0, r4
+ pop {r4, r5, r6, pc}
+.L547:
bl FtlBbmIsBadBlock
- add r5, r5, #1
cmp r0, #0
+ add r5, r5, #1
addne r4, r4, #1
uxthne r4, r4
- b .L544
-.L551:
- mov r0, r4
- ldmfd sp!, {r4, r5, r6, pc}
+ b .L545
.L553:
.align 2
.L552:
@@ -3315,29 +3569,34 @@
.size FtlBbtCalcTotleCnt, .-FtlBbtCalcTotleCnt
.align 2
.global V2P_block
+ .syntax unified
+ .arm
+ .fpu softvfp
.type V2P_block, %function
V2P_block:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- movw r3, #2344
- ldr r6, .L556
- mov r4, r1
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ movw r3, #2348
+ ldr r4, .L556
+ mov r5, r1
mov r7, r0
- ldrh r5, [r6, r3]
- mov r1, r5
- bl __aeabi_uidivmod
- mov r0, r7
- smlabb r4, r4, r5, r1
- mov r1, r5
+ ldrh r6, [r4, r3]
+ mov r1, r6
bl __aeabi_uidiv
- movw r3, #2386
- ldrh r3, [r6, r3]
- smlabb r0, r3, r0, r4
+ movw r3, #2388
+ smulbb r5, r6, r5
+ ldrh r4, [r4, r3]
+ mov r1, r6
+ smulbb r4, r4, r0
+ mov r0, r7
+ bl __aeabi_uidivmod
+ add r0, r5, r1
+ add r0, r4, r0
uxth r0, r0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
+ pop {r4, r5, r6, r7, r8, pc}
.L557:
.align 2
.L556:
@@ -3346,18 +3605,21 @@
.size V2P_block, .-V2P_block
.align 2
.global P2V_plane
+ .syntax unified
+ .arm
+ .fpu softvfp
.type P2V_plane, %function
P2V_plane:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
ldr r3, .L560
- movw r2, #2344
- stmfd sp!, {r4, r5, r6, lr}
+ movw r2, #2348
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r6, r0
ldrh r5, [r3, r2]
- movw r2, #2386
+ movw r2, #2388
ldrh r1, [r3, r2]
bl __aeabi_uidiv
mov r1, r5
@@ -3366,7 +3628,7 @@
bl __aeabi_uidivmod
add r1, r4, r1
uxth r0, r1
- ldmfd sp!, {r4, r5, r6, pc}
+ pop {r4, r5, r6, pc}
.L561:
.align 2
.L560:
@@ -3375,23 +3637,26 @@
.size P2V_plane, .-P2V_plane
.align 2
.global P2V_block_in_plane
+ .syntax unified
+ .arm
+ .fpu softvfp
.type P2V_block_in_plane, %function
P2V_block_in_plane:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, lr}
+ push {r4, lr}
.save {r4, lr}
- movw r3, #2386
+ movw r3, #2388
ldr r4, .L564
ldrh r1, [r4, r3]
bl __aeabi_uidivmod
- movw r3, #2344
+ movw r3, #2348
uxth r0, r1
ldrh r1, [r4, r3]
bl __aeabi_uidiv
uxth r0, r0
- ldmfd sp!, {r4, pc}
+ pop {r4, pc}
.L565:
.align 2
.L564:
@@ -3400,6 +3665,9 @@
.size P2V_block_in_plane, .-P2V_block_in_plane
.align 2
.global ftl_cmp_data_ver
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_cmp_data_ver, %function
ftl_cmp_data_ver:
.fnstart
@@ -3408,13 +3676,13 @@
@ link register save eliminated.
cmp r0, r1
bls .L567
- rsb r0, r1, r0
+ sub r0, r0, r1
cmp r0, #-2147483648
movhi r0, #0
movls r0, #1
bx lr
.L567:
- rsb r0, r0, r1
+ sub r0, r1, r0
cmp r0, #-2147483648
movls r0, #0
movhi r0, #1
@@ -3423,6 +3691,9 @@
.size ftl_cmp_data_ver, .-ftl_cmp_data_ver
.align 2
.global FtlFreeSysBlkQueueEmpty
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBlkQueueEmpty, %function
FtlFreeSysBlkQueueEmpty:
.fnstart
@@ -3432,16 +3703,19 @@
ldr r3, .L570
ldrh r0, [r3, #6]
clz r0, r0
- mov r0, r0, lsr #5
+ lsr r0, r0, #5
bx lr
.L571:
.align 2
.L570:
- .word .LANCHOR0+2512
+ .word .LANCHOR0+2516
.fnend
.size FtlFreeSysBlkQueueEmpty, .-FtlFreeSysBlkQueueEmpty
.align 2
.global FtlFreeSysBlkQueueFull
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBlkQueueFull, %function
FtlFreeSysBlkQueueFull:
.fnstart
@@ -3452,291 +3726,307 @@
ldrh r0, [r3, #6]
sub r0, r0, #1024
clz r0, r0
- mov r0, r0, lsr #5
+ lsr r0, r0, #5
bx lr
.L574:
.align 2
.L573:
- .word .LANCHOR0+2512
+ .word .LANCHOR0+2516
.fnend
.size FtlFreeSysBlkQueueFull, .-FtlFreeSysBlkQueueFull
.align 2
.global FtlFreeSysBlkQueueIn
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBlkQueueIn, %function
FtlFreeSysBlkQueueIn:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
sub r3, r0, #1
movw r2, #65533
- mov r7, r0
uxth r3, r3
cmp r3, r2
- ldmhifd sp!, {r3, r4, r5, r6, r7, pc}
- ldr r4, .L585
+ bxhi lr
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ ldr r4, .L588
ldrh r3, [r4, #6]
cmp r3, #1024
- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
+ popeq {r4, r5, r6, r7, r8, pc}
cmp r1, #0
+ mov r5, r0
beq .L577
- ldr r5, .L585+4
- ldr r3, [r5, #-3616]
+ ldr r6, .L588+4
+ ldr r3, [r6, #-3612]
cmp r3, #0
bne .L577
bl P2V_block_in_plane
- mov r1, #1
- mov r3, r7, asl #10
- mov r2, r1
- mov r6, r0
- ldr r0, [r5, #-3612]
+ mov r7, r0
+ ldr r0, [r6, #-3608]
+ lsl r3, r5, #10
+ mov r2, #1
+ mov r1, r2
str r3, [r0, #4]
bl FlashEraseBlocks
- ldr r1, [r5, #-3608]
- mov r3, r6, asl #1
- ldrh r2, [r1, r3]
- add r2, r2, #1
- strh r2, [r1, r3] @ movhi
- ldr r3, [r5, #-3604]
+ ldr r2, [r6, #-3604]
+ lsl r0, r7, #1
+ ldrh r3, [r2, r0]
add r3, r3, #1
- str r3, [r5, #-3604]
+ strh r3, [r2, r0] @ movhi
+ ldr r3, [r6, #-3600]
+ add r3, r3, #1
+ str r3, [r6, #-3600]
.L577:
ldrh r3, [r4, #6]
add r3, r3, #1
strh r3, [r4, #6] @ movhi
ldrh r3, [r4, #4]
- add r2, r4, r3, asl #1
+ add r2, r4, r3, lsl #1
add r3, r3, #1
ubfx r3, r3, #0, #10
+ strh r5, [r2, #8] @ movhi
strh r3, [r4, #4] @ movhi
- strh r7, [r2, #8] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L586:
+ pop {r4, r5, r6, r7, r8, pc}
+.L589:
.align 2
-.L585:
- .word .LANCHOR0+2512
+.L588:
+ .word .LANCHOR0+2516
.word .LANCHOR2
.fnend
.size FtlFreeSysBlkQueueIn, .-FtlFreeSysBlkQueueIn
.align 2
.global FtlFreeSysBLkSort
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBLkSort, %function
FtlFreeSysBLkSort:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L600
- ldrh ip, [r3, #28]
- ldr r3, .L600+4
+ ldr r3, .L603
ldrh r2, [r3, #6]
cmp r2, #0
bxeq lr
- stmfd sp!, {r4, lr}
- .save {r4, lr}
+ ldr r2, .L603+4
mov r0, #0
- ldrh r1, [r3, #2]
- and ip, ip, #31
- ldrh r2, [r3, #4]
+ push {r4, lr}
+ .save {r4, lr}
mov r4, r0
-.L589:
- uxth lr, r0
+ ldrh r1, [r3, #2]
+ ldrh lr, [r2, #28]
+ ldrh r2, [r3, #4]
+ and lr, lr, #31
+.L592:
+ uxth ip, r0
add r0, r0, #1
cmp lr, ip
- bge .L599
- add lr, r3, r1, asl #1
+ bgt .L593
+ cmp r4, #0
+ strhne r1, [r3, #2] @ movhi
+ strhne r2, [r3, #4] @ movhi
+ pop {r4, pc}
+.L593:
+ add ip, r3, r1, lsl #1
add r1, r1, #1
ubfx r1, r1, #0, #10
- ldrh r4, [lr, #8]
- add lr, r3, r2, asl #1
- strh r4, [lr, #8] @ movhi
+ ldrh r4, [ip, #8]
+ add ip, r3, r2, lsl #1
+ strh r4, [ip, #8] @ movhi
mov r4, #1
add r2, r2, r4
ubfx r2, r2, #0, #10
- b .L589
-.L599:
- cmp r4, #0
- strneh r1, [r3, #2] @ movhi
- strneh r2, [r3, #4] @ movhi
- ldmfd sp!, {r4, pc}
-.L601:
+ b .L592
+.L604:
.align 2
-.L600:
- .word .LANCHOR2-3600
- .word .LANCHOR0+2512
+.L603:
+ .word .LANCHOR0+2516
+ .word .LANCHOR2-3596
.fnend
.size FtlFreeSysBLkSort, .-FtlFreeSysBLkSort
.align 2
.global FtlFreeSysBlkQueueOut
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBlkQueueOut, %function
FtlFreeSysBlkQueueOut:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
- ldr r7, .L613
- add r4, r7, #2512
- mov r8, r4
-.L603:
+ ldr r4, .L616
+ ldr r8, .L616+4
+ mov r7, r4
+.L606:
ldrh r1, [r4, #6]
cmp r1, #0
- beq .L604
- ldr r5, .L613+4
+ beq .L607
+ ldr r5, .L616+8
sub r1, r1, #1
ldrh r3, [r4, #2]
strh r1, [r4, #6] @ movhi
- ldr r10, [r5, #-3616]
- add r2, r4, r3, asl #1
+ ldr r10, [r5, #-3612]
+ add r2, r4, r3, lsl #1
add r3, r3, #1
cmp r10, #0
ubfx r3, r3, #0, #10
ldrh r6, [r2, #8]
strh r3, [r4, #2] @ movhi
- bne .L605
+ bne .L608
mov r0, r6
bl P2V_block_in_plane
- mov r3, r6, asl #10
mov r9, r0
- ldr r0, [r5, #-3612]
+ ldr r0, [r5, #-3608]
+ lsl r3, r6, #10
str r3, [r0, #4]
- ldrb r3, [r7, #144] @ zero_extendqisi2
+ ldrb r3, [r8, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L606
- mov r1, r10
+ beq .L609
mov r2, #1
+ mov r1, r10
bl FlashEraseBlocks
-.L606:
- mov r1, #1
- ldr r0, [r5, #-3612]
- mov r2, r1
+.L609:
+ mov r2, #1
+ ldr r0, [r5, #-3608]
+ mov r1, r2
bl FlashEraseBlocks
- ldr r1, [r5, #-3608]
- mov r3, r9, asl #1
- ldrh r2, [r1, r3]
- add r2, r2, #1
- strh r2, [r1, r3] @ movhi
- ldr r3, [r5, #-3604]
+ ldr r2, [r5, #-3604]
+ lsl r0, r9, #1
+ ldrh r3, [r2, r0]
add r3, r3, #1
- str r3, [r5, #-3604]
- b .L605
-.L604:
- ldr r0, .L613+8
- bl printk
-.L607:
- b .L607
-.L605:
+ strh r3, [r2, r0] @ movhi
+ ldr r3, [r5, #-3600]
+ add r3, r3, #1
+ str r3, [r5, #-3600]
+.L608:
sub r3, r6, #1
movw r2, #65533
uxth r3, r3
cmp r3, r2
- bls .L608
+ bls .L611
+ ldrh r2, [r7, #6]
mov r1, r6
- ldrh r2, [r8, #6]
- ldr r0, .L613+12
+ ldr r0, .L616+12
bl printk
- b .L603
-.L608:
+ b .L606
+.L607:
+ ldr r0, .L616+16
+ bl printk
+.L610:
+ b .L610
+.L611:
mov r0, r6
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L614:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L617:
.align 2
-.L613:
+.L616:
+ .word .LANCHOR0+2516
.word .LANCHOR0
.word .LANCHOR2
- .word .LC3
.word .LC4
+ .word .LC3
.fnend
.size FtlFreeSysBlkQueueOut, .-FtlFreeSysBlkQueueOut
.align 2
.global test_node_in_list
+ .syntax unified
+ .arm
+ .fpu softvfp
.type test_node_in_list, %function
test_node_in_list:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L621
+ ldr r3, .L624
str lr, [sp, #-4]!
.save {lr}
movw lr, #65535
- ldr ip, [r3, #-3552]
ldr r2, [r0]
- ldr r3, .L621+4
- rsb r0, ip, r2
- mov r0, r0, asr #1
+ ldr ip, [r3, #-3548]
+ sub r3, r2, ip
+ asr r0, r3, #1
+ ldr r3, .L624+4
mul r3, r3, r0
mov r0, #6
uxth r3, r3
-.L617:
- cmp r1, r3
- beq .L618
+.L620:
+ cmp r3, r1
+ beq .L621
ldrh r3, [r2]
cmp r3, lr
- beq .L619
+ beq .L622
mla r2, r0, r3, ip
- b .L617
-.L618:
+ b .L620
+.L621:
mov r0, #1
ldr pc, [sp], #4
-.L619:
+.L622:
mov r0, #0
ldr pc, [sp], #4
-.L622:
+.L625:
.align 2
-.L621:
+.L624:
.word .LANCHOR2
.word -1431655765
.fnend
.size test_node_in_list, .-test_node_in_list
.align 2
.global insert_data_list
+ .syntax unified
+ .arm
+ .fpu softvfp
.type insert_data_list, %function
insert_data_list:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- movw r3, #2328
- ldr r5, .L640
- ldrh r3, [r5, r3]
+ movw r3, #2332
+ ldr r4, .L642
+ ldrh r3, [r4, r3]
cmp r3, r0
- bls .L625
- ldr r2, .L640+4
+ bls .L628
+ ldr r2, .L642+4
mov lr, #6
mul lr, lr, r0
mvn ip, #0
- ldr r6, [r2, #-3552]
- mov r10, r2
+ ldr r6, [r2, #-3548]
+ mov r5, r2
add r1, r6, lr
strh ip, [r1, #2] @ movhi
strh ip, [r6, lr] @ movhi
- ldr r3, [r2, #-3548]
+ ldr r3, [r2, #-3544]
cmp r3, #0
- beq .L639
- ldr r8, [r2, #-3544]
- mov r4, r0, asl #1
+ streq r1, [r2, #-3544]
+ beq .L628
+ ldr r8, [r2, #-3540]
+ lsl r10, r0, #1
ldrh r2, [r1, #4]
- ldrh r7, [r8, r4]
+ ldrh r7, [r8, r10]
cmp r2, #0
mulne ip, r2, r7
- ldr r7, [r10, #-3552]
- ldr r2, .L640+8
- rsb r9, r7, r3
- mov r9, r9, asr #1
+ ldr r7, [r5, #-3548]
+ sub r2, r3, r7
+ asr r9, r2, #1
+ ldr r2, .L642+8
mul r2, r2, r9
- movw r9, #2328
- ldrh r5, [r5, r9]
- ldr r9, [r10, #-3608]
- add r4, r9, r4
- str r4, [sp, #4]
+ movw r9, #2332
+ ldrh r4, [r4, r9]
+ ldr r9, [r5, #-3604]
+ str r4, [sp]
uxth r2, r2
+ add r4, r9, r10
+ str r4, [sp, #4]
mov r4, #0
- str r5, [sp]
-.L634:
- add r4, r4, #1
+.L637:
ldr r5, [sp]
+ add r4, r4, #1
uxth r4, r4
cmp r4, r5
movls r5, #0
@@ -3744,64 +4034,60 @@
cmp r0, r2
orreq r5, r5, #1
cmp r5, #0
- bne .L625
- mov r10, r2, asl #1
+ bne .L628
+ lsl r10, r2, #1
ldrh r5, [r3, #4]
ldrh fp, [r8, r10]
cmp r5, #0
mvneq r5, #0
mulne r5, r5, fp
- cmp r5, ip
- bne .L630
+ cmp ip, r5
+ bne .L633
ldr r5, [sp, #4]
ldrh r10, [r9, r10]
ldrh r5, [r5]
cmp r10, r5
- bcc .L632
- b .L631
-.L630:
- bhi .L631
-.L632:
+ bcc .L635
+.L634:
+ strh r2, [r6, lr] @ movhi
+ ldr ip, .L642+4
+ ldrh r2, [r3, #2]
+ strh r2, [r1, #2] @ movhi
+ ldr r2, [ip, #-3544]
+ cmp r3, r2
+ ldrhne lr, [r3, #2]
+ movne r2, #6
+ ldrne r1, [ip, #-3548]
+ strheq r0, [r3, #2] @ movhi
+ streq r1, [ip, #-3544]
+ mulne r2, r2, lr
+ strhne r0, [r1, r2] @ movhi
+ strhne r0, [r3, #2] @ movhi
+ b .L628
+.L633:
+ bcc .L634
+.L635:
ldrh r5, [r3]
movw r10, #65535
cmp r5, r10
- streqh r2, [r1, #2] @ movhi
- streqh r0, [r3] @ movhi
- ldreq r3, .L640+4
- streq r1, [r3, #-3540]
- beq .L625
-.L633:
- mov r3, #6
- mov r2, r5
- mla r3, r3, r5, r7
- b .L634
-.L631:
- strh r2, [r6, lr] @ movhi
- ldrh r2, [r3, #2]
+ bne .L636
strh r2, [r1, #2] @ movhi
- ldr r2, .L640+4
- ldr ip, [r2, #-3548]
- cmp r3, ip
- bne .L635
- strh r0, [r3, #2] @ movhi
-.L639:
- str r1, [r2, #-3548]
- b .L625
-.L635:
- ldrh ip, [r3, #2]
- ldr r1, [r2, #-3552]
- mov r2, #6
- mul r2, r2, ip
- strh r0, [r1, r2] @ movhi
- strh r0, [r3, #2] @ movhi
-.L625:
+ strh r0, [r3] @ movhi
+ ldr r3, .L642+4
+ str r1, [r3, #-3536]
+.L628:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L641:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L636:
+ mov r3, #6
+ mov r2, r5
+ mla r3, r3, r5, r7
+ b .L637
+.L643:
.align 2
-.L640:
+.L642:
.word .LANCHOR0
.word .LANCHOR2
.word -1431655765
@@ -3809,180 +4095,193 @@
.size insert_data_list, .-insert_data_list
.align 2
.global INSERT_DATA_LIST
+ .syntax unified
+ .arm
+ .fpu softvfp
.type INSERT_DATA_LIST, %function
INSERT_DATA_LIST:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
bl insert_data_list
- ldr r2, .L644
- ldrh r3, [r2]
+ ldr r2, .L646
+ ldrh r3, [r2, #-12]
add r3, r3, #1
- strh r3, [r2] @ movhi
- ldmfd sp!, {r3, pc}
-.L645:
+ strh r3, [r2, #-12] @ movhi
+ pop {r4, pc}
+.L647:
.align 2
-.L644:
- .word .LANCHOR2-3536
+.L646:
+ .word .LANCHOR2-3520
.fnend
.size INSERT_DATA_LIST, .-INSERT_DATA_LIST
.align 2
.global insert_free_list
+ .syntax unified
+ .arm
+ .fpu softvfp
.type insert_free_list, %function
insert_free_list:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
movw r4, #65535
cmp r0, r4
- beq .L647
- ldr r2, .L655
- mov lr, #6
- mul r6, lr, r0
+ beq .L649
+ ldr r2, .L656
+ mov r1, #6
+ mul r5, r1, r0
mvn r3, #0
- ldr r7, [r2, #-3552]
- mov r5, r2
- add ip, r7, r6
- strh r3, [ip, #2] @ movhi
- strh r3, [r7, r6] @ movhi
- ldr r3, [r2, #-3532]
+ ldr r6, [r2, #-3548]
+ mov ip, r2
+ add lr, r6, r5
+ strh r3, [lr, #2] @ movhi
+ strh r3, [r6, r5] @ movhi
+ ldr r3, [r2, #-3528]
cmp r3, #0
- beq .L654
- ldr r9, [r2, #-3608]
- mov r2, r0, asl #1
- ldr r8, [r5, #-3552]
- rsb r1, r8, r3
- ldrh r10, [r9, r2]
- ldr r2, .L655+4
- mov r1, r1, asr #1
- mul r1, r2, r1
- uxth r2, r1
-.L651:
- mov r1, r2, asl #1
- ldrh r1, [r9, r1]
- cmp r1, r10
- bcs .L649
+ streq lr, [r2, #-3528]
+ beq .L649
+ ldr r8, [r2, #-3604]
+ lsl r2, r0, #1
+ ldr r7, [ip, #-3548]
+ ldrh r9, [r8, r2]
+ sub r2, r3, r7
+ asr r10, r2, #1
+ ldr r2, .L656+4
+ mul r2, r2, r10
+ mov r10, r1
+ uxth r2, r2
+.L653:
+ lsl r1, r2, #1
+ ldrh r1, [r8, r1]
+ cmp r1, r9
+ bcs .L651
ldrh r1, [r3]
cmp r1, r4
- streqh r2, [ip, #2] @ movhi
- streqh r0, [r3] @ movhi
- beq .L647
-.L650:
- mla r3, lr, r1, r8
- mov r2, r1
- b .L651
-.L649:
- ldrh r1, [r3, #2]
- strh r1, [ip, #2] @ movhi
- strh r2, [r7, r6] @ movhi
- ldr r1, [r5, #-3532]
- ldr r2, .L655
- cmp r3, r1
bne .L652
- strh r0, [r3, #2] @ movhi
-.L654:
- str ip, [r2, #-3532]
- b .L647
-.L652:
- ldrh ip, [r3, #2]
- ldr r1, [r2, #-3552]
- mov r2, #6
- mul r2, r2, ip
- strh r0, [r1, r2] @ movhi
- strh r0, [r3, #2] @ movhi
-.L647:
+ strh r2, [lr, #2] @ movhi
+ strh r0, [r3] @ movhi
+.L649:
mov r0, #0
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L656:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L652:
+ mla r3, r10, r1, r7
+ mov r2, r1
+ b .L653
+.L651:
+ ldrh r1, [r3, #2]
+ strh r1, [lr, #2] @ movhi
+ strh r2, [r6, r5] @ movhi
+ ldr r2, [ip, #-3528]
+ cmp r3, r2
+ ldrhne lr, [r3, #2]
+ movne r2, #6
+ ldrne r1, [ip, #-3548]
+ strheq r0, [r3, #2] @ movhi
+ streq lr, [ip, #-3528]
+ mulne r2, r2, lr
+ strhne r0, [r1, r2] @ movhi
+ strhne r0, [r3, #2] @ movhi
+ b .L649
+.L657:
.align 2
-.L655:
+.L656:
.word .LANCHOR2
.word -1431655765
.fnend
.size insert_free_list, .-insert_free_list
.align 2
.global INSERT_FREE_LIST
+ .syntax unified
+ .arm
+ .fpu softvfp
.type INSERT_FREE_LIST, %function
INSERT_FREE_LIST:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
bl insert_free_list
- ldr r2, .L659
- ldrh r3, [r2, #-8]
+ ldr r2, .L660
+ ldrh r3, [r2, #-4]
add r3, r3, #1
- strh r3, [r2, #-8] @ movhi
- ldmfd sp!, {r3, pc}
-.L660:
+ strh r3, [r2, #-4] @ movhi
+ pop {r4, pc}
+.L661:
.align 2
-.L659:
+.L660:
.word .LANCHOR2-3520
.fnend
.size INSERT_FREE_LIST, .-INSERT_FREE_LIST
.align 2
.global List_remove_node
+ .syntax unified
+ .arm
+ .fpu softvfp
.type List_remove_node, %function
List_remove_node:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, lr}
+ push {r4, r5, lr}
.save {r4, r5, lr}
mov ip, #6
- ldr r4, .L667
- movw r5, #65535
+ ldr r4, .L668
mul r1, ip, r1
+ movw r5, #65535
ldr r3, [r0]
- ldr r2, [r4, #-3552]
+ ldr r2, [r4, #-3548]
add lr, r2, r1
cmp lr, r3
ldrh r3, [r2, r1]
- bne .L662
+ bne .L663
cmp r3, r5
mlane r3, ip, r3, r2
moveq r3, #0
streq r3, [r0]
strne r3, [r0]
mvnne r0, #0
- strneh r0, [r3, #2] @ movhi
- b .L664
-.L662:
- cmp r3, r5
- ldrh r0, [lr, #2]
- bne .L665
- cmp r0, r3
- mulne r0, ip, r0
- mvnne r3, #0
- strneh r3, [r2, r0] @ movhi
- b .L664
+ strhne r0, [r3, #2] @ movhi
.L665:
- mla r3, ip, r3, r2
- strh r0, [r3, #2] @ movhi
- ldrh r5, [lr, #2]
- ldrh r0, [r2, r1]
- ldr r3, [r4, #-3552]
- mul ip, ip, r5
- strh r0, [r3, ip] @ movhi
-.L664:
mvn r3, #0
mov r0, #0
strh r3, [r2, r1] @ movhi
strh r3, [lr, #2] @ movhi
- ldmfd sp!, {r4, r5, pc}
-.L668:
+ pop {r4, r5, pc}
+.L663:
+ cmp r3, r5
+ ldrh r0, [lr, #2]
+ bne .L666
+ cmp r0, r3
+ mulne r3, ip, r0
+ mvnne r0, #0
+ strhne r0, [r2, r3] @ movhi
+ b .L665
+.L666:
+ mla r3, ip, r3, r2
+ strh r0, [r3, #2] @ movhi
+ ldrh r3, [lr, #2]
+ ldrh r5, [r2, r1]
+ ldr r0, [r4, #-3548]
+ mul r3, ip, r3
+ strh r5, [r0, r3] @ movhi
+ b .L665
+.L669:
.align 2
-.L667:
+.L668:
.word .LANCHOR2
.fnend
.size List_remove_node, .-List_remove_node
.align 2
.global List_pop_index_node
+ .syntax unified
+ .arm
+ .fpu softvfp
.type List_pop_index_node, %function
List_pop_index_node:
.fnstart
@@ -3990,1133 +4289,1182 @@
@ frame_needed = 0, uses_anonymous_args = 0
ldr r3, [r0]
cmp r3, #0
- beq .L675
- ldr r2, .L678
- movw ip, #65535
- stmfd sp!, {r4, lr}
+ beq .L676
+ ldr r2, .L681
+ push {r4, lr}
.save {r4, lr}
- mov lr, #6
- ldr r4, [r2, #-3552]
-.L671:
- cmp r1, #0
- bne .L672
-.L674:
- rsb r4, r4, r3
- ldr r3, .L678+4
- mov r4, r4, asr #1
- mul r4, r3, r4
- uxth r4, r4
- mov r1, r4
- bl List_remove_node
- mov r0, r4
- ldmfd sp!, {r4, pc}
+ movw lr, #65535
+ mov r4, #6
+ ldr r2, [r2, #-3548]
.L672:
- ldrh r2, [r3]
- cmp r2, ip
- beq .L674
- sub r1, r1, #1
- mla r3, lr, r2, r4
- uxth r1, r1
- b .L671
+ cmp r1, #0
+ bne .L673
.L675:
+ ldr r4, .L681+4
+ sub r3, r3, r2
+ asr r3, r3, #1
+ mul r4, r4, r3
+ uxth r1, r4
+ bl List_remove_node
+ uxth r0, r4
+ pop {r4, pc}
+.L673:
+ ldrh ip, [r3]
+ cmp ip, lr
+ beq .L675
+ sub r1, r1, #1
+ mla r3, r4, ip, r2
+ uxth r1, r1
+ b .L672
+.L676:
movw r0, #65535
bx lr
-.L679:
+.L682:
.align 2
-.L678:
+.L681:
.word .LANCHOR2
.word -1431655765
.fnend
.size List_pop_index_node, .-List_pop_index_node
.align 2
.global List_get_gc_head_node
+ .syntax unified
+ .arm
+ .fpu softvfp
.type List_get_gc_head_node, %function
List_get_gc_head_node:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L687
- ldr r3, [r2, #-3548]
+ ldr r2, .L689
+ ldr r3, [r2, #-3544]
cmp r3, #0
- ldrne r1, [r2, #-3552]
+ ldrne r1, [r2, #-3548]
movne ip, #6
movwne r2, #65535
- beq .L685
-.L682:
- cmp r0, #0
- beq .L683
- ldrh r3, [r3]
- cmp r3, r2
- subne r0, r0, #1
- mlane r3, ip, r3, r1
- uxthne r0, r0
- bne .L682
-.L685:
+ bne .L685
+.L688:
movw r0, #65535
bx lr
-.L683:
- rsb r3, r1, r3
- ldr r0, .L687+4
- mov r3, r3, asr #1
- mul r0, r0, r3
- uxth r0, r0
- bx lr
-.L688:
- .align 2
.L687:
+ sub r0, r0, #1
+ mla r3, ip, r3, r1
+ uxth r0, r0
+.L685:
+ cmp r0, #0
+ beq .L686
+ ldrh r3, [r3]
+ cmp r3, r2
+ bne .L687
+ b .L688
+.L686:
+ ldr r0, .L689+4
+ sub r3, r3, r1
+ asr r3, r3, #1
+ mul r3, r0, r3
+ uxth r0, r3
+ bx lr
+.L690:
+ .align 2
+.L689:
.word .LANCHOR2
.word -1431655765
.fnend
.size List_get_gc_head_node, .-List_get_gc_head_node
.align 2
.global List_update_data_list
+ .syntax unified
+ .arm
+ .fpu softvfp
.type List_update_data_list, %function
List_update_data_list:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- ldr r3, .L697
- sub r2, r3, #3520
- ldrh r2, [r2, #-4]
+ ldr r3, .L699
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ sub r5, r3, #3520
+ ldrh r2, [r5]
cmp r2, r0
- beq .L690
+ beq .L692
sub r2, r3, #3472
- ldrh r2, [r2, #-4]
+ ldrh r2, [r2]
cmp r2, r0
- beq .L690
+ beq .L692
sub r2, r3, #3424
- ldrh r2, [r2, #-4]
+ ldrh r2, [r2]
cmp r2, r0
- beq .L690
+ beq .L692
mov lr, #6
- ldr r1, [r3, #-3552]
+ ldr r1, [r3, #-3548]
mul lr, lr, r0
- ldr r2, [r3, #-3548]
+ ldr r2, [r3, #-3544]
add ip, r1, lr
cmp ip, r2
- beq .L690
- ldr r4, [r3, #-3544]
- mov r3, r0, asl #1
- ldrh r2, [r4, r3]
- ldrh r3, [ip, #4]
- ldrh ip, [ip, #2]
- cmp r3, #0
- mulne r2, r3, r2
+ beq .L692
+ ldr r4, [r3, #-3540]
+ lsl r3, r0, #1
+ ldrh r2, [ip, #4]
+ ldrh r3, [r4, r3]
+ cmp r2, #0
mvneq r2, #0
- movw r3, #65535
- cmp ip, r3
- bne .L692
- ldrh r3, [r1, lr]
+ mulne r2, r2, r3
+ ldrh r3, [ip, #2]
+ movw ip, #65535
cmp r3, ip
- beq .L690
-.L692:
- mov r3, #6
- mul ip, r3, ip
- ldr r3, .L697+4
+ bne .L694
+ ldrh ip, [r1, lr]
+ cmp ip, r3
+ beq .L692
+.L694:
+ mov ip, #6
+ mul ip, ip, r3
+ ldr r3, .L699+4
+ asr lr, ip, #1
add r1, r1, ip
- mov lr, ip, asr #1
mul r3, r3, lr
- mov r3, r3, asl #1
+ lsl r3, r3, #1
ldrh lr, [r4, r3]
ldrh r3, [r1, #4]
cmp r3, #0
mulne r3, r3, lr
mvneq r3, #0
cmp r2, r3
- bcs .L690
- ldr r5, .L697+8
+ bcs .L692
mov r4, r0
- mov r1, r4
- sub r0, r5, #12
+ mov r1, r0
+ ldr r0, .L699+8
bl List_remove_node
- ldrh r3, [r5]
+ ldrh r3, [r5, #-12]
mov r0, r4
sub r3, r3, #1
- strh r3, [r5] @ movhi
+ strh r3, [r5, #-12] @ movhi
bl INSERT_DATA_LIST
-.L690:
+.L692:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L698:
+ pop {r4, r5, r6, pc}
+.L700:
.align 2
-.L697:
+.L699:
.word .LANCHOR2
.word -1431655765
- .word .LANCHOR2-3536
+ .word .LANCHOR2-3544
.fnend
.size List_update_data_list, .-List_update_data_list
.align 2
.global ftl_map_blk_alloc_new_blk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_map_blk_alloc_new_blk, %function
ftl_map_blk_alloc_new_blk:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mov r3, #0
ldrh r1, [r0, #10]
ldr r2, [r0, #12]
-.L700:
+.L702:
uxth r5, r3
cmp r5, r1
- bcs .L703
+ bcs .L705
mov r7, r2
add r3, r3, #1
ldrh r6, [r7]
add r2, r2, #2
cmp r6, #0
- bne .L700
+ bne .L702
mov r4, r0
bl FtlFreeSysBlkQueueOut
- movw r2, #65533
sub r3, r0, #1
+ movw r2, #65533
+ uxth r3, r3
mov r1, r0
strh r0, [r7] @ movhi
- uxth r3, r3
cmp r3, r2
- bls .L701
- ldr r3, .L707
- ldr r0, .L707+4
+ bls .L703
+ ldr r3, .L709
+ ldr r0, .L709+4
ldrh r2, [r3, #6]
bl printk
-.L702:
- b .L702
-.L701:
+.L704:
+ b .L704
+.L703:
ldr r3, [r4, #28]
strh r6, [r4, #2] @ movhi
+ strh r5, [r4] @ movhi
add r3, r3, #1
str r3, [r4, #28]
ldrh r3, [r4, #8]
- strh r5, [r4] @ movhi
add r3, r3, #1
strh r3, [r4, #8] @ movhi
-.L703:
+.L705:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L708:
+ pop {r4, r5, r6, r7, r8, pc}
+.L710:
.align 2
-.L707:
- .word .LANCHOR0+2512
+.L709:
+ .word .LANCHOR0+2516
.word .LC5
.fnend
.size ftl_map_blk_alloc_new_blk, .-ftl_map_blk_alloc_new_blk
.align 2
.global select_l2p_ram_region
+ .syntax unified
+ .arm
+ .fpu softvfp
.type select_l2p_ram_region, %function
select_l2p_ram_region:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L725
- movw r3, #2426
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r2, .L722
+ movw r3, #2430
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r1, #0
- ldrh r2, [r2, r3]
mov ip, #12
- ldr r3, .L725+4
movw lr, #65535
- ldr r3, [r3, #-3380]
-.L710:
+ ldrh r2, [r2, r3]
+ ldr r3, .L722+4
+ ldr r3, [r3, #-3376]
+.L712:
uxth r0, r1
cmp r0, r2
- bcs .L722
- add r1, r1, #1
- mla r4, ip, r1, r3
- ldrh r4, [r4, #-12]
- cmp r4, lr
- bne .L710
- ldmfd sp!, {r4, r5, r6, pc}
-.L722:
+ bcc .L714
mov r0, r2
mov r1, #0
mov ip, #-2147483648
mov r5, #12
-.L713:
+.L715:
uxth r4, r1
cmp r4, r2
- bcs .L723
+ bcc .L717
+ cmp r0, r2
+ popcc {r4, r5, r6, pc}
+ ldr r1, .L722+8
+ mov r0, r2
+ mvn ip, #0
+ ldrh r5, [r1, #-12]
+ mov r1, #0
+.L718:
+ uxth lr, r1
+ cmp lr, r2
+ bcc .L720
+ pop {r4, r5, r6, pc}
+.L714:
+ add r1, r1, #1
+ mla r4, ip, r1, r3
+ ldrh r4, [r4, #-12]
+ cmp r4, lr
+ bne .L712
+ pop {r4, r5, r6, pc}
+.L717:
mla lr, r5, r1, r3
add r1, r1, #1
ldr lr, [lr, #4]
- cmp lr, ip
- mvn r6, lr
- mov r6, r6, lsr #31
- movcs r6, #0
+ cmp ip, lr
+ movls r6, #0
+ movhi r6, #1
+ cmp lr, #0
+ movlt r6, #0
cmp r6, #0
movne ip, lr
movne r0, r4
- b .L713
-.L723:
- cmp r0, r2
- ldmccfd sp!, {r4, r5, r6, pc}
- ldr r1, .L725+8
- mov r0, r2
- mvn ip, #0
- ldrh r5, [r1]
- mov r1, #0
-.L716:
- uxth lr, r1
- cmp lr, r2
- bcs .L724
+ b .L715
+.L720:
ldr r4, [r3, #4]
- cmp r4, ip
- bcs .L717
+ cmp ip, r4
+ bls .L719
ldrh r6, [r3]
cmp r6, r5
movne ip, r4
movne r0, lr
-.L717:
+.L719:
add r1, r1, #1
add r3, r3, #12
- b .L716
-.L724:
- ldmfd sp!, {r4, r5, r6, pc}
-.L726:
+ b .L718
+.L723:
.align 2
-.L725:
+.L722:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR2-3376
+ .word .LANCHOR2-3360
.fnend
.size select_l2p_ram_region, .-select_l2p_ram_region
.align 2
.global FtlUpdateVaildLpn
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlUpdateVaildLpn, %function
FtlUpdateVaildLpn:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L735
+ ldr r3, .L733
sub r1, r3, #3360
- ldrh r2, [r1, #-14]
+ ldrh r2, [r1, #-10]
cmp r2, #4
cmpls r0, #0
- addeq r2, r2, #1
- streqh r2, [r1, #-14] @ movhi
- bxeq lr
- ldr r0, .L735+4
+ bne .L725
+ add r2, r2, #1
+ strh r2, [r1, #-10] @ movhi
+ bx lr
+.L725:
+ ldr r0, .L733+4
mov r2, #0
str lr, [sp, #-4]!
.save {lr}
- movw ip, #65535
- strh r2, [r1, #-14] @ movhi
- movw r1, #2328
- ldrh r0, [r0, r1]
- str r2, [r3, #-3372]
- ldr r2, [r3, #-3544]
- add r0, r2, r0, asl #1
-.L729:
- cmp r2, r0
- beq .L734
- ldrh r1, [r2], #2
- cmp r1, ip
- ldrne lr, [r3, #-3372]
- addne r1, r1, lr
- strne r1, [r3, #-3372]
- b .L729
-.L734:
+ movw lr, #65535
+ strh r2, [r1, #-10] @ movhi
+ movw r1, #2332
+ str r2, [r3, #-3368]
+ ldrh r1, [r0, r1]
+ ldr r2, [r3, #-3540]
+ add r1, r2, r1, lsl #1
+.L726:
+ cmp r2, r1
+ bne .L728
ldr pc, [sp], #4
-.L736:
+.L728:
+ ldrh ip, [r2], #2
+ cmp ip, lr
+ ldrne r0, [r3, #-3368]
+ addne r0, r0, ip
+ strne r0, [r3, #-3368]
+ b .L726
+.L734:
.align 2
-.L735:
+.L733:
.word .LANCHOR2
.word .LANCHOR0
.fnend
.size FtlUpdateVaildLpn, .-FtlUpdateVaildLpn
.align 2
.global ftl_set_blk_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_set_blk_mode, %function
ftl_set_blk_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L741
- mov r3, r0, lsr #5
cmp r1, #0
- and r0, r0, #31
- uxth r3, r3
+ mov r3, r0
+ beq .L736
+ b ftl_set_blk_mode.part.9
+.L736:
+ ldr r2, .L737
+ lsr r0, r0, #5
+ and r3, r3, #31
mov ip, #1
- ldr r1, [r2, #-3368]
- ldr r2, [r1, r3, asl #2]
- orrne r0, r2, ip, asl r0
- biceq r0, r2, ip, asl r0
- str r0, [r1, r3, asl #2]
+ ldr r1, [r2, #32]
+ ldr r2, [r1, r0, lsl #2]
+ bic r3, r2, ip, lsl r3
+ str r3, [r1, r0, lsl #2]
bx lr
-.L742:
+.L738:
.align 2
-.L741:
- .word .LANCHOR2
+.L737:
+ .word .LANCHOR0
.fnend
.size ftl_set_blk_mode, .-ftl_set_blk_mode
.align 2
.global ftl_get_blk_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_get_blk_mode, %function
ftl_get_blk_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L744
- mov r2, r0, lsr #5
+ ldr r3, .L740
+ lsr r2, r0, #5
and r0, r0, #31
- ldr r3, [r3, #-3368]
- ldr r3, [r3, r2, asl #2]
- mov r0, r3, lsr r0
+ ldr r3, [r3, #32]
+ ldr r3, [r3, r2, lsl #2]
+ lsr r0, r3, r0
and r0, r0, #1
bx lr
-.L745:
+.L741:
.align 2
-.L744:
- .word .LANCHOR2
+.L740:
+ .word .LANCHOR0
.fnend
.size ftl_get_blk_mode, .-ftl_get_blk_mode
.align 2
.global ftl_sb_update_avl_pages
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_sb_update_avl_pages, %function
ftl_sb_update_avl_pages:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
mov r3, #0
+ movw ip, #2324
strh r3, [r0, #4] @ movhi
- ldr r3, .L756
- stmfd sp!, {r4, r5, lr}
+ ldr r3, .L750
+ push {r4, r5, lr}
.save {r4, r5, lr}
- movw r4, #65535
- ldrh lr, [r3]
- add r3, r2, #7
- add r3, r0, r3, asl #1
-.L747:
- cmp r2, lr
- bcs .L754
- ldrh ip, [r3, #2]!
- add r2, r2, #1
- cmp ip, r4
- uxth r2, r2
- ldrneh ip, [r0, #4]
- addne ip, ip, #1
- strneh ip, [r0, #4] @ movhi
- b .L747
-.L754:
- ldr r2, .L756+4
- movw r3, #2388
- add ip, r0, #14
movw r5, #65535
- ldrh r4, [r2, r3]
- mov r2, #0
-.L750:
- uxth r3, r2
- cmp r3, lr
- bcs .L755
- ldrh r3, [ip, #2]!
+ ldrh lr, [r3, ip]
+ add ip, r0, r2, lsl #1
+ add ip, ip, #14
+.L743:
+ cmp r2, lr
+ bcc .L745
+ movw r2, #2390
+ add ip, r0, #16
+ ldrh r3, [r3, r2]
+ movw r4, #65535
+ sub r3, r3, #1
+ sub r1, r3, r1
+ mov r3, #0
+ uxth r1, r1
+.L746:
+ uxth r2, r3
+ cmp lr, r2
+ bhi .L748
+ pop {r4, r5, pc}
+.L745:
+ ldrh r4, [ip, #2]!
add r2, r2, #1
- cmp r3, r5
- ldrneh r3, [r0, #4]
- addne r3, r4, r3
- subne r3, r3, #1
- rsbne r3, r1, r3
- strneh r3, [r0, #4] @ movhi
- b .L750
-.L755:
- ldmfd sp!, {r4, r5, pc}
-.L757:
+ uxth r2, r2
+ cmp r4, r5
+ ldrhne r4, [r0, #4]
+ addne r4, r4, #1
+ strhne r4, [r0, #4] @ movhi
+ b .L743
+.L748:
+ ldrh r2, [ip], #2
+ add r3, r3, #1
+ cmp r2, r4
+ ldrhne r2, [r0, #4]
+ addne r2, r1, r2
+ strhne r2, [r0, #4] @ movhi
+ b .L746
+.L751:
.align 2
-.L756:
- .word .LANCHOR0+2320
+.L750:
.word .LANCHOR0
.fnend
.size ftl_sb_update_avl_pages, .-ftl_sb_update_avl_pages
.align 2
.global make_superblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type make_superblock, %function
make_superblock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, lr}
- add r6, r0, #16
- ldr r7, .L772
+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ movw r3, #2324
+ ldr r6, .L765
mov r4, r0
+ add r7, r0, #16
mvn r9, #0
+ ldr r10, .L765+4
mov r5, #0
+ ldrh r8, [r6, r3]
strh r5, [r0, #4] @ movhi
- ldrh r8, [r7], #28
strb r5, [r0, #7]
-.L759:
+.L753:
uxth r3, r5
- cmp r3, r8
- bcs .L771
- ldrb r0, [r7, r5] @ zero_extendqisi2
- add r6, r6, #2
- ldrh r1, [r4]
- add r5, r5, #1
- bl V2P_block
- strh r9, [r6, #-2] @ movhi
- mov r10, r0
- bl FtlBbmIsBadBlock
- cmp r0, #0
- streqh r10, [r6, #-2] @ movhi
- ldreqb r3, [r4, #7] @ zero_extendqisi2
- addeq r3, r3, #1
- streqb r3, [r4, #7]
- b .L759
-.L771:
- ldr r3, .L772+4
- movw r2, #2388
- ldrb r1, [r4, #7] @ zero_extendqisi2
- ldrh r2, [r3, r2]
- smulbb r2, r1, r2
- strh r2, [r4, #4] @ movhi
- mov r2, #0
- strb r2, [r4, #9]
- ldr r2, [r3, #2244]
- cmp r2, #0
- beq .L762
- ldr r1, .L772+8
- ldrh r2, [r4]
- ldr r1, [r1, #-3608]
- mov r2, r2, asl #1
- ldrh r2, [r1, r2]
- cmp r2, #79
- movls r2, #1
- strlsb r2, [r4, #9]
-.L762:
- ldrb r3, [r3] @ zero_extendqisi2
+ cmp r8, r3
+ bhi .L755
+ movw r2, #2390
+ ldrb r3, [r4, #7] @ zero_extendqisi2
+ ldrh r2, [r6, r2]
+ smulbb r3, r3, r2
+ strh r3, [r4, #4] @ movhi
+ mov r3, #0
+ strb r3, [r4, #9]
+ ldr r3, [r6, #2248]
+ cmp r3, #0
+ beq .L756
+ ldrh r3, [r4]
+ ldr r2, .L765+8
+ ldr r2, [r2, #-3604]
+ lsl r3, r3, #1
+ ldrh r3, [r2, r3]
+ cmp r3, #79
+ movls r3, #1
+ strbls r3, [r4, #9]
+.L756:
+ ldrb r3, [r6, #36] @ zero_extendqisi2
mov r0, #0
cmp r3, #0
movne r3, #1
- strneb r3, [r4, #9]
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L773:
+ strbne r3, [r4, #9]
+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L755:
+ ldrb r0, [r10, r5] @ zero_extendqisi2
+ add r7, r7, #2
+ ldrh r1, [r4]
+ add r5, r5, #1
+ bl V2P_block
+ strh r9, [r7, #-2] @ movhi
+ mov fp, r0
+ bl FtlBbmIsBadBlock
+ cmp r0, #0
+ strheq fp, [r7, #-2] @ movhi
+ ldrbeq r3, [r4, #7] @ zero_extendqisi2
+ addeq r3, r3, #1
+ strbeq r3, [r4, #7]
+ b .L753
+.L766:
.align 2
-.L772:
- .word .LANCHOR0+2320
+.L765:
.word .LANCHOR0
+ .word .LANCHOR0+2350
.word .LANCHOR2
.fnend
.size make_superblock, .-make_superblock
.align 2
.global update_multiplier_value
+ .syntax unified
+ .arm
+ .fpu softvfp
.type update_multiplier_value, %function
update_multiplier_value:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
+ ldr r3, .L774
+ movw r2, #2324
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r5, #0
- ldr r3, .L784
+ ldr r9, .L774+4
mov r6, r0
- ldr r9, .L784+4
mov r4, r5
- add r2, r3, #2320
- ldrh r7, [r2]
- movw r2, #2388
+ ldrh r7, [r3, r2]
+ movw r2, #2390
ldrh r8, [r3, r2]
-.L775:
+.L768:
uxth r3, r5
- cmp r3, r7
- bcs .L783
- ldrb r0, [r9, r5] @ zero_extendqisi2
- mov r1, r6
- bl V2P_block
- add r5, r5, #1
- bl FtlBbmIsBadBlock
- cmp r0, #0
- addeq r4, r4, r8
- uxtheq r4, r4
- b .L775
-.L783:
+ cmp r7, r3
+ bhi .L770
cmp r4, #0
- beq .L778
+ moveq r0, r4
+ beq .L771
mov r1, r4
mov r0, #32768
bl __aeabi_idiv
- uxth r4, r0
-.L778:
- ldr r3, .L784+8
+.L771:
+ ldr r3, .L774+8
mov r2, #6
- mov r0, #0
- ldr r3, [r3, #-3552]
+ ldr r3, [r3, #-3548]
mla r6, r2, r6, r3
- strh r4, [r6, #4] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L785:
+ strh r0, [r6, #4] @ movhi
+ mov r0, #0
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L770:
+ mov r1, r6
+ ldrb r0, [r9, r5] @ zero_extendqisi2
+ bl V2P_block
+ bl FtlBbmIsBadBlock
+ cmp r0, #0
+ add r5, r5, #1
+ addeq r4, r4, r8
+ uxtheq r4, r4
+ b .L768
+.L775:
.align 2
-.L784:
+.L774:
.word .LANCHOR0
- .word .LANCHOR0+2348
+ .word .LANCHOR0+2350
.word .LANCHOR2
.fnend
.size update_multiplier_value, .-update_multiplier_value
.align 2
.global GetFreeBlockMinEraseCount
+ .syntax unified
+ .arm
+ .fpu softvfp
.type GetFreeBlockMinEraseCount, %function
GetFreeBlockMinEraseCount:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L789
- ldr r0, [r2, #-3532]
+ ldr r2, .L779
+ ldr r0, [r2, #-3528]
cmp r0, #0
bxeq lr
- ldr r3, [r2, #-3552]
- rsb r0, r3, r0
- ldr r3, .L789+4
- mov r0, r0, asr #1
+ ldr r3, [r2, #-3548]
+ sub r0, r0, r3
+ ldr r3, .L779+4
+ asr r0, r0, #1
mul r0, r3, r0
- ldr r3, [r2, #-3608]
+ ldr r3, [r2, #-3604]
uxth r0, r0
- mov r0, r0, asl #1
+ lsl r0, r0, #1
ldrh r0, [r3, r0]
bx lr
-.L790:
+.L780:
.align 2
-.L789:
+.L779:
.word .LANCHOR2
.word -1431655765
.fnend
.size GetFreeBlockMinEraseCount, .-GetFreeBlockMinEraseCount
.align 2
.global GetFreeBlockMaxEraseCount
+ .syntax unified
+ .arm
+ .fpu softvfp
.type GetFreeBlockMaxEraseCount, %function
GetFreeBlockMaxEraseCount:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r1, .L801
- ldr r3, [r1, #-3532]
+ ldr r1, .L793
+ ldr r3, [r1, #-3528]
cmp r3, #0
- beq .L797
+ beq .L787
sub r2, r1, #3520
- stmfd sp!, {r4, r5, lr}
+ push {r4, r5, lr}
.save {r4, r5, lr}
+ ldrh r2, [r2, #-4]
mov r4, #6
- ldrh r2, [r2, #-8]
movw r5, #65535
- ldr ip, [r1, #-3552]
- rsb r2, r2, r2, asl #3
- rsb r3, ip, r3
- mov r2, r2, asr #3
- mov r3, r3, asr #1
+ ldr ip, [r1, #-3548]
+ rsb r2, r2, r2, lsl #3
+ sub r3, r3, ip
+ asr r2, r2, #3
+ asr r3, r3, #1
cmp r0, r2
uxthgt r0, r2
- ldr r2, .L801+4
+ ldr r2, .L793+4
mul r3, r2, r3
mov r2, #0
uxth r3, r3
-.L794:
+.L784:
uxth lr, r2
- cmp lr, r0
- bcs .L796
+ cmp r0, lr
+ bls .L786
mul lr, r4, r3
add r2, r2, #1
ldrh lr, [ip, lr]
cmp lr, r5
- bne .L798
-.L796:
- ldr r2, [r1, #-3608]
- mov r3, r3, asl #1
+ bne .L788
+.L786:
+ ldr r2, [r1, #-3604]
+ lsl r3, r3, #1
ldrh r0, [r2, r3]
- ldmfd sp!, {r4, r5, pc}
-.L798:
+ pop {r4, r5, pc}
+.L788:
mov r3, lr
- b .L794
-.L797:
+ b .L784
+.L787:
mov r0, r3
bx lr
-.L802:
+.L794:
.align 2
-.L801:
+.L793:
.word .LANCHOR2
.word -1431655765
.fnend
.size GetFreeBlockMaxEraseCount, .-GetFreeBlockMaxEraseCount
.align 2
.global FtlPrintInfo2buf
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlPrintInfo2buf, %function
FtlPrintInfo2buf:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, lr}
- mov r7, r0
- ldr r8, .L814
- add r4, r7, #12
- ldr r1, .L814+4
- .pad #32
- sub sp, sp, #32
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov r8, r0
+ ldr r9, .L808
+ add r5, r8, #12
+ .pad #36
+ sub sp, sp, #36
+ ldr r1, .L808+4
bl strcpy
- mov r0, r4
- ldr r1, .L814+8
- ldr r2, [r8, #116]
+ ldr r2, [r9, #124]
+ mov r0, r5
+ ldr r1, .L808+8
bl sprintf
- ldr r1, .L814+12
- ldr r2, [r8, #2404]
- add r4, r4, r0
- mov r0, r4
+ add r5, r5, r0
+ ldr r2, [r9, #2408]
+ mov r0, r5
+ ldr r1, .L808+12
bl sprintf
- ldr r3, .L814+16
- ldr r3, [r3, #504]
+ ldr r3, .L808+16
+ add r5, r5, r0
+ ldr r3, [r3, #500]
cmp r3, #1
- add r4, r4, r0
- bne .L809
- add r0, sp, #16
- add r1, sp, #20
- add r2, sp, #24
+ subne r0, r5, r8
+ bne .L795
add r3, sp, #28
+ add r2, sp, #24
+ add r1, sp, #20
+ add r0, sp, #16
bl NandcGetTimeCfg
- mov r0, r4
- ldr r1, .L814+20
- ldr r6, .L814+24
- sub r10, r6, #3520
- ldr r3, [sp, #24]
- ldr r2, [sp, #16]
- str r3, [sp]
ldr r3, [sp, #28]
+ mov r0, r5
+ ldr r2, [sp, #16]
+ ldr r1, .L808+20
str r3, [sp, #4]
+ ldr r3, [sp, #24]
+ ldr r7, .L808+24
+ str r3, [sp]
ldr r3, [sp, #20]
+ sub r10, r7, #3520
bl sprintf
- ldr r1, .L814+28
- add r4, r4, r0
- add r5, r4, #10
- mov r0, r4
- sub r4, r6, #3600
+ add r6, r5, r0
+ ldr r1, .L808+28
+ mov r0, r6
+ add r6, r6, #10
bl strcpy
- mov r0, r5
- ldr r1, .L814+32
- ldr r2, [r8, #2448]
+ ldr r2, [r9, #2452]
+ mov r0, r6
+ ldr r1, .L808+32
+ sub r4, r7, #3584
bl sprintf
- ldr r1, .L814+36
- ldr r2, [r6, #-3372]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3368]
+ ldr r1, .L808+36
+ mov r0, r6
bl sprintf
- ldr r1, .L814+40
- ldr r2, [r6, #-3364]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3364]
+ ldr r1, .L808+40
+ mov r0, r6
bl sprintf
- ldr r1, .L814+44
- ldr r2, [r6, #-3360]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3360]
+ ldr r1, .L808+44
+ mov r0, r6
bl sprintf
- ldr r1, .L814+48
- ldr r2, [r6, #-3356]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3356]
+ ldr r1, .L808+48
+ mov r0, r6
bl sprintf
- ldr r1, .L814+52
- ldr r2, [r6, #-3352]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3352]
+ ldr r1, .L808+52
+ mov r0, r6
bl sprintf
- ldr r1, .L814+56
- ldr r2, [r6, #-3348]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3348]
+ ldr r1, .L808+56
+ mov r0, r6
bl sprintf
- ldr r1, .L814+60
- ldr r2, [r6, #-3344]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3344]
+ ldr r1, .L808+60
+ mov r0, r6
bl sprintf
- ldr r2, [r6, #-3340]
- ldr r1, .L814+64
- mov r2, r2, lsr #11
- add r5, r5, r0
- mov r0, r5
+ ldr r2, [r7, #-3340]
+ add r6, r6, r0
+ ldr r1, .L808+64
+ mov r0, r6
+ sub r5, r7, #3280
+ lsr r2, r2, #11
bl sprintf
- ldr r2, [r6, #-3336]
- ldr r1, .L814+68
- mov r2, r2, lsr #11
- add r5, r5, r0
- mov r0, r5
+ ldr r2, [r7, #-3336]
+ add r6, r6, r0
+ ldr r1, .L808+68
+ mov r0, r6
+ lsr r2, r2, #11
bl sprintf
- ldr r1, .L814+72
- ldr r2, [r6, #-3332]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3332]
+ ldr r1, .L808+72
+ mov r0, r6
bl sprintf
- ldr r1, .L814+76
- ldr r2, [r6, #-3328]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3328]
+ ldr r1, .L808+76
+ mov r0, r6
bl sprintf
- add r5, r5, r0
+ add r6, r6, r0
bl FtlBbtCalcTotleCnt
- ldr r2, .L814+80
- ldr r1, .L814+84
- ldrh r2, [r2, #6]
+ ldr r2, .L808+80
mov r3, r0
- mov r0, r5
+ ldr r1, .L808+84
+ mov r0, r6
+ ldrh r2, [r2, #6]
bl sprintf
- ldr r1, .L814+88
- ldrh r2, [r10, #-8]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+92
- ldr r2, [r6, #-3324]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+96
- ldr r2, [r6, #-3320]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+100
- ldr r2, [r6, #-3316]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+104
- ldr r2, [r6, #-3604]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+108
- ldr r2, [r6, #-3312]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+112
- ldr r2, [r6, #-3308]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldrh r2, [r4, #30]
- ldr r1, .L814+116
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldrh r2, [r4, #28]
- ldr r1, .L814+120
- sub r4, r6, #3296
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+124
- ldr r2, [r8, #2428]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+128
- ldr r2, [r8, #2420]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+132
- ldr r2, [r8, #2316]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- add r3, r8, #2512
- ldr r1, .L814+136
- ldrh r2, [r3, #6]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- movw r3, #2328
- ldrh r2, [r8, r3]
- ldr r1, .L814+140
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldrh r2, [r4, #-8]
- ldr r1, .L814+144
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+148
- ldr r2, [r8, #2332]
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldrh r2, [r4, #-4]
- ldr r1, .L814+152
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- movw r3, #2452
- ldrh r2, [r8, r3]
- ldr r1, .L814+156
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldrh r2, [r4, #-226]
- ldr r1, .L814+160
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+164
- ldrb r2, [r6, #-3518] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
- bl sprintf
- ldr r1, .L814+168
+ add r6, r6, r0
ldrh r2, [r10, #-4]
- add r5, r5, r0
- mov r0, r5
+ ldr r1, .L808+88
+ mov r0, r6
bl sprintf
- ldr r1, .L814+172
- ldrb r2, [r6, #-3516] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3324]
+ ldr r1, .L808+92
+ mov r0, r6
bl sprintf
- ldrh r2, [r4, #-224]
- ldr r1, .L814+176
- sub r4, r6, #3472
- sub r9, r4, #4
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3320]
+ ldr r1, .L808+96
+ mov r0, r6
bl sprintf
- ldrh r3, [r10, #-4]
- ldr r2, [r6, #-3544]
- ldr r1, .L814+180
- mov r3, r3, asl #1
- ldrh r2, [r2, r3]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3316]
+ ldr r1, .L808+100
+ mov r0, r6
bl sprintf
- ldrh r2, [r4, #-2]
- ldr r1, .L814+184
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3600]
+ ldr r1, .L808+104
+ mov r0, r6
bl sprintf
- ldr r1, .L814+188
- ldrb r2, [r6, #-3470] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldr r2, [r7, #-3312]
+ ldr r1, .L808+108
+ mov r0, r6
bl sprintf
+ add r6, r6, r0
+ ldr r2, [r7, #-3308]
+ ldr r1, .L808+112
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r4, #18]
+ ldr r1, .L808+116
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r4, #16]
+ ldr r1, .L808+120
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldr r2, [r9, #2432]
+ ldr r1, .L808+124
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldr r2, [r9, #2424]
+ ldr r1, .L808+128
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldr r2, [r9, #2320]
+ ldr r1, .L808+132
+ mov r0, r6
+ bl sprintf
+ ldr r3, .L808+136
+ add r6, r6, r0
+ ldr r1, .L808+140
+ mov r0, r6
+ sub r4, r7, #3296
+ ldrh r2, [r3, #6]
+ bl sprintf
+ movw r3, #2332
+ add r6, r6, r0
+ ldrh r2, [r9, r3]
+ mov r0, r6
+ ldr r1, .L808+144
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r4, #-8]
+ ldr r1, .L808+148
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldr r2, [r9, #2336]
+ ldr r1, .L808+152
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
ldrh r2, [r4, #-4]
- ldr r1, .L814+192
- add r5, r5, r0
- mov r0, r5
+ ldr r1, .L808+156
+ mov r0, r6
bl sprintf
- ldr r1, .L814+196
- ldrb r2, [r6, #-3468] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ movw r3, #2456
+ add r6, r6, r0
+ ldrh r2, [r9, r3]
+ mov r0, r6
+ ldr r1, .L808+160
+ sub r4, r7, #3472
bl sprintf
- ldrh r2, [r9, #4]
- ldr r1, .L814+200
- sub r9, r6, #3424
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r10, #2]
+ ldr r1, .L808+164
+ mov r0, r6
bl sprintf
- ldrh r3, [r4, #-4]
- ldr r2, [r6, #-3544]
- ldr r1, .L814+204
- mov r3, r3, asl #1
+ add r6, r6, r0
+ ldrb r2, [r7, #-3514] @ zero_extendqisi2
+ ldr r1, .L808+168
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r10]
+ ldr r1, .L808+172
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrb r2, [r7, #-3512] @ zero_extendqisi2
+ ldr r1, .L808+176
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r10, #4]
+ ldr r1, .L808+180
+ mov r0, r6
+ bl sprintf
+ ldrh r3, [r10]
+ add r6, r6, r0
+ ldr r2, [r7, #-3540]
+ mov r0, r6
+ ldr r1, .L808+184
+ lsl r3, r3, #1
ldrh r2, [r2, r3]
- add r5, r5, r0
- mov r0, r5
bl sprintf
- ldrh r2, [r4, #46]
- ldr r1, .L814+208
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r4, #2]
+ ldr r1, .L808+188
+ mov r0, r6
bl sprintf
- ldr r1, .L814+212
- ldrb r2, [r6, #-3422] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrb r2, [r7, #-3466] @ zero_extendqisi2
+ ldr r1, .L808+192
+ mov r0, r6
bl sprintf
- ldrh r2, [r9, #-4]
- ldr r1, .L814+216
- sub r9, r6, #3280
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r4]
+ ldr r1, .L808+196
+ mov r0, r6
bl sprintf
- ldr r1, .L814+220
- ldrb r2, [r6, #-3420] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrb r2, [r7, #-3464] @ zero_extendqisi2
+ ldr r1, .L808+200
+ mov r0, r6
bl sprintf
- ldrh r2, [r4, #48]
- ldr r1, .L814+224
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r4, #4]
+ ldr r1, .L808+204
+ mov r0, r6
bl sprintf
- ldrh r2, [r4, #190]
- ldr r1, .L814+228
- add r5, r5, r0
- mov r0, r5
+ ldrh r3, [r4]
+ add r6, r6, r0
+ ldr r2, [r7, #-3540]
+ mov r0, r6
+ ldr r1, .L808+208
+ sub r4, r7, #3424
+ lsl r3, r3, #1
+ ldrh r2, [r2, r3]
bl sprintf
- ldr r1, .L814+232
- ldrb r2, [r6, #-3278] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r4, #2]
+ ldr r1, .L808+212
+ mov r0, r6
bl sprintf
- ldr r1, .L814+236
- ldrh r2, [r9, #-4]
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrb r2, [r7, #-3418] @ zero_extendqisi2
+ ldr r1, .L808+216
+ mov r0, r6
bl sprintf
- ldr r1, .L814+240
- ldrb r2, [r6, #-3276] @ zero_extendqisi2
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrh r2, [r4]
+ ldr r1, .L808+220
+ mov r0, r6
bl sprintf
- ldrh r2, [r4, #192]
- ldr r1, .L814+244
- add r5, r5, r0
- mov r0, r5
+ add r6, r6, r0
+ ldrb r2, [r7, #-3416] @ zero_extendqisi2
+ ldr r1, .L808+224
+ mov r0, r6
bl sprintf
- ldr r1, [r6, #-3148]
- ldr r3, [r8, #2244]
- ldr r2, [r6, #-3236]
- orr r2, r3, r2, asl #8
- ldr r3, [r6, #-3152]
- str r1, [sp]
- add r5, r5, r0
- ldr r1, [r6, #-3156]
- mov r0, r5
- str r1, [sp, #4]
- ldr r1, .L814+248
+ add r6, r6, r0
+ ldrh r2, [r4, #4]
+ ldr r1, .L808+228
+ mov r0, r6
bl sprintf
- ldr r1, .L814+252
- ldr r2, [r6, #-3160]
- add r4, r5, r0
- sub r5, r6, #2704
+ add r6, r6, r0
+ ldrh r2, [r5, #-2]
+ ldr r1, .L808+232
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrb r2, [r7, #-3278] @ zero_extendqisi2
+ ldr r1, .L808+236
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrh r2, [r5, #-4]
+ ldr r1, .L808+240
+ mov r0, r6
+ bl sprintf
+ add r6, r6, r0
+ ldrb r2, [r7, #-3276] @ zero_extendqisi2
+ ldr r1, .L808+244
+ mov r0, r6
+ bl sprintf
+ sub r4, r5, #4
+ add r6, r6, r0
+ ldrh r2, [r4, #4]
+ mov r0, r6
+ ldr r1, .L808+248
+ bl sprintf
+ ldr r3, [r7, #-3160]
+ add r6, r6, r0
+ ldr r2, [r9, #2248]
+ mov r0, r6
+ ldr r1, [r7, #-2724]
+ str r3, [sp, #4]
+ ldr r3, [r7, #-3152]
+ orr r2, r2, r1, lsl #8
+ ldr r1, .L808+252
+ str r3, [sp]
+ ldr r3, [r7, #-3156]
+ bl sprintf
+ add r4, r6, r0
+ ldr r2, [r7, #-3164]
+ ldr r1, .L808+256
mov r0, r4
bl sprintf
- ldr r1, .L814+256
- ldr r2, [r6, #-3136]
add r4, r4, r0
+ ldr r2, [r7, #-3140]
+ ldr r1, .L808+260
mov r0, r4
bl sprintf
- sub r3, r6, #2720
- ldr r1, .L814+260
+ sub r3, r7, #2720
+ add r4, r4, r0
ldrh r2, [r3]
+ mov r0, r4
+ ldr r1, .L808+264
+ sub r6, r7, #2704
+ bl sprintf
add r4, r4, r0
+ ldrh r2, [r6, #-14]
+ ldr r1, .L808+268
mov r0, r4
bl sprintf
- ldr r1, .L814+264
- ldrh r2, [r5, #-14]
add r4, r4, r0
+ ldr r2, [r7, #-2716]
+ ldr r1, .L808+272
mov r0, r4
bl sprintf
- ldr r1, .L814+268
- ldr r2, [r6, #-2716]
add r4, r4, r0
- mov r0, r4
- bl sprintf
- ldr r1, .L814+272
- ldrh r2, [r5, #-8]
- add r4, r4, r0
+ ldrh r2, [r6, #-8]
+ ldr r1, .L808+276
mov r0, r4
bl sprintf
add r4, r4, r0
bl GetFreeBlockMinEraseCount
- ldr r1, .L814+276
+ ldr r1, .L808+280
mov r2, r0
mov r0, r4
bl sprintf
add r4, r4, r0
- ldrh r0, [r10, #-8]
+ ldrh r0, [r10, #-4]
bl GetFreeBlockMaxEraseCount
- ldr r1, .L814+280
+ ldr r1, .L808+284
mov r2, r0
mov r0, r4
bl sprintf
- ldrh r3, [r9, #-4]
+ ldrh r3, [r5, #-4]
movw r2, #65535
- cmp r3, r2
add r4, r4, r0
- beq .L806
- ldr r2, [r6, #-3544]
- mov r3, r3, asl #1
+ cmp r3, r2
+ beq .L798
+ ldr r2, [r7, #-3540]
+ lsl r3, r3, #1
mov r0, r4
- ldr r1, .L814+284
+ ldr r1, .L808+288
ldrh r2, [r2, r3]
bl sprintf
add r4, r4, r0
-.L806:
+.L798:
mov r0, #0
- mov r5, #0
+ ldr r9, .L808+292
bl List_get_gc_head_node
- movw r10, #65535
- mov r9, #6
uxth r3, r0
-.L808:
- cmp r3, r10
- beq .L807
- ldr r2, [r6, #-3544]
- mov r1, r3, asl #1
- mul r8, r9, r3
+ mov r5, #0
+ movw fp, #65535
+ mov r10, #6
+.L800:
+ cmp r3, fp
+ beq .L799
+ ldr r2, [r7, #-3604]
+ lsl r1, r3, #1
+ mul r6, r10, r3
mov r0, r4
ldrh r2, [r2, r1]
- str r2, [sp]
- ldr r2, [r6, #-3552]
- add r2, r2, r8
+ str r2, [sp, #8]
+ ldr r2, [r7, #-3548]
+ add r2, r2, r6
ldrh r2, [r2, #4]
str r2, [sp, #4]
- ldr r2, [r6, #-3608]
+ ldr r2, [r7, #-3540]
ldrh r2, [r2, r1]
- ldr r1, .L814+288
- str r2, [sp, #8]
+ mov r1, r9
+ str r2, [sp]
mov r2, r5
bl sprintf
add r5, r5, #1
- ldr r3, [r6, #-3552]
+ ldr r3, [r7, #-3548]
cmp r5, #16
- ldrh r3, [r3, r8]
add r4, r4, r0
- bne .L808
-.L807:
- ldr r2, [r6, #-3552]
+ ldrh r3, [r3, r6]
+ bne .L800
+.L799:
+ ldr r2, [r7, #-3548]
mov r5, #0
- ldr r3, [r6, #-3532]
- movw r10, #65535
- mov r9, #6
- rsb r3, r2, r3
- ldr r2, .L814+292
- mov r3, r3, asr #1
+ ldr r3, [r7, #-3528]
+ movw r9, #65535
+ ldr fp, .L808+296
+ mov r10, #6
+ sub r3, r3, r2
+ ldr r2, .L808+300
+ asr r3, r3, #1
mul r3, r2, r3
uxth r3, r3
-.L810:
- cmp r3, r10
- beq .L809
- mul r8, r9, r3
- ldr r2, [r6, #-3552]
- ldr r1, [r6, #-3608]
+.L802:
+ cmp r3, r9
+ beq .L801
+ ldr r1, [r7, #-3604]
+ lsl r2, r3, #1
+ mul r6, r10, r3
mov r0, r4
- add r2, r2, r8
+ ldrh r2, [r1, r2]
+ mov r1, fp
+ str r2, [sp, #4]
+ ldr r2, [r7, #-3548]
+ add r2, r2, r6
ldrh r2, [r2, #4]
str r2, [sp]
- mov r2, r3, asl #1
- ldrh r2, [r1, r2]
- ldr r1, .L814+296
- str r2, [sp, #4]
mov r2, r5
- bl sprintf
add r5, r5, #1
- ldr r3, [r6, #-3552]
+ bl sprintf
cmp r5, #4
- ldrh r3, [r3, r8]
add r4, r4, r0
- bne .L810
-.L809:
- rsb r0, r7, r4
- add sp, sp, #32
+ ldrne r3, [r7, #-3548]
+ ldrhne r3, [r3, r6]
+ bne .L802
+.L801:
+ sub r0, r4, r8
+.L795:
+ add sp, sp, #36
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L815:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L809:
.align 2
-.L814:
+.L808:
.word .LANCHOR0
.word .LC6
.word .LC7
@@ -5137,7 +5485,7 @@
.word .LC20
.word .LC21
.word .LC22
- .word .LANCHOR0+2452
+ .word .LANCHOR0+2456
.word .LC23
.word .LC24
.word .LC25
@@ -5151,6 +5499,7 @@
.word .LC33
.word .LC34
.word .LC35
+ .word .LANCHOR0+2516
.word .LC36
.word .LC37
.word .LC38
@@ -5190,237 +5539,243 @@
.word .LC72
.word .LC73
.word .LC74
- .word -1431655765
.word .LC75
+ .word -1431655765
.fnend
.size FtlPrintInfo2buf, .-FtlPrintInfo2buf
.align 2
.global ftl_proc_ftl_read
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_proc_ftl_read, %function
ftl_proc_ftl_read:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r5, r0
- ldr r1, .L818
- ldr r2, .L818+4
+ ldr r2, .L812
+ ldr r1, .L812+4
bl sprintf
add r4, r5, r0
mov r0, r4
bl FtlPrintInfo2buf
add r0, r4, r0
- rsb r0, r5, r0
- ldmfd sp!, {r3, r4, r5, pc}
-.L819:
+ sub r0, r0, r5
+ pop {r4, r5, r6, pc}
+.L813:
.align 2
-.L818:
+.L812:
.word .LC76
.word .LC77
.fnend
.size ftl_proc_ftl_read, .-ftl_proc_ftl_read
.align 2
.global GetSwlReplaceBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type GetSwlReplaceBlock, %function
GetSwlReplaceBlock:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #28
sub sp, sp, #28
- ldr r4, .L850
+ ldr r4, .L842
ldr r2, [r4, #-3316]
ldr r3, [r4, #-3308]
cmp r2, r3
- bcs .L821
- ldr r2, .L850+4
- movw r1, #2328
- ldr r0, [r4, #-3608]
+ bcs .L815
+ ldr r0, .L842+4
+ movw r2, #2332
mov r3, #0
str r3, [r4, #-3324]
- ldrh r1, [r2, r1]
- sub r0, r0, #2
- mov r5, r2
-.L822:
+ ldrh r1, [r0, r2]
+ mov r6, r0
+ ldr r2, [r4, #-3604]
+ sub r2, r2, #2
+.L816:
cmp r3, r1
- bcs .L849
- ldrh r2, [r0, #2]!
- add r3, r3, #1
- ldr ip, [r4, #-3324]
- add r2, r2, ip
- str r2, [r4, #-3324]
- b .L822
-.L849:
- ldr r6, [r4, #-3324]
- mov r0, r6
+ bcc .L817
+ ldr r5, [r4, #-3324]
+ mov r0, r5
bl __aeabi_uidiv
- movw r3, #2380
- ldrh r1, [r5, r3]
str r0, [r4, #-3316]
+ movw r3, #2382
ldr r0, [r4, #-3320]
- rsb r0, r0, r6
+ ldrh r1, [r6, r3]
+ sub r0, r5, r0
bl __aeabi_uidiv
str r0, [r4, #-3324]
- b .L824
-.L821:
- ldr r3, [r4, #-3312]
- cmp r2, r3
- bls .L824
- ldr ip, .L850+8
- add r3, r3, #1
- str r3, [r4, #-3312]
- mov r3, #0
-.L826:
- ldrh r2, [ip]
- cmp r3, r2
- bcs .L824
- ldr r0, [r4, #-3608]
- mov r1, r3, asl #1
- add r3, r3, #1
- ldrh r2, [r0, r1]
- add r2, r2, #1
- strh r2, [r0, r1] @ movhi
- b .L826
-.L824:
- ldr r6, [r4, #-3308]
+.L818:
+ ldr r5, [r4, #-3308]
ldr r8, [r4, #-3316]
- add r3, r6, #256
+ add r3, r5, #256
cmp r3, r8
- bls .L829
- ldr r2, .L850
- add r3, r6, #768
- ldr r2, [r2, #-3312]
+ bls .L823
+ ldr r2, [r4, #-3312]
+ add r3, r5, #768
cmp r3, r2
- bls .L829
- ldr r3, .L850+4
- cmp r6, #40
- ldr r2, [r3, #2244]
+ bls .L823
+ ldr r3, .L842+4
+ cmp r5, #40
+ ldr r2, [r3, #2248]
movls r3, #0
movhi r3, #1
cmp r2, #0
orreq r3, r3, #1
cmp r3, #0
- beq .L829
-.L831:
- movw r0, #65535
- b .L830
-.L829:
- ldr r5, .L850
- sub r3, r5, #3520
- ldrh r0, [r3, #-8]
- add r0, r0, r0, asl #1
- ubfx r0, r0, #2, #16
- bl GetFreeBlockMaxEraseCount
- add r1, r6, #64
- cmp r0, r1
- mov r9, r0
- movcs r1, #0
- movcc r1, #1
- cmp r6, #40
- movls r1, #0
- cmp r1, #0
- bne .L831
- ldr r3, [r5, #-3548]
- cmp r3, #0
- beq .L831
- ldr r0, .L850+4
- movw r2, #2328
- ldr ip, .L850+12
- movw r7, #65535
- ldr r10, [r5, #-3608]
- mov lr, #6
- ldrh r2, [r0, r2]
- ldr r0, [r5, #-3552]
- mov r5, r7
- str r2, [sp, #20]
-.L832:
- ldrh r2, [r3]
- movw fp, #65535
- cmp r2, fp
- beq .L834
- add r1, r1, #1
- ldr fp, [sp, #20]
- uxth r1, r1
- cmp r1, fp
- bhi .L831
- ldrh fp, [r3, #4]
- cmp fp, #0
- beq .L833
- rsb r3, r0, r3
- mov r3, r3, asr #1
- mul r3, ip, r3
- uxth r3, r3
- mov fp, r3, asl #1
- ldrh fp, [r10, fp]
- cmp fp, r6
- bls .L838
- cmp fp, r7
- movcc r7, fp
- movcc r5, r3
-.L833:
- mla r3, lr, r2, r0
- b .L832
-.L838:
- mov r5, r3
-.L834:
- movw r3, #65535
- cmp r5, r3
- beq .L831
- mov r3, r5, asl #1
- ldrh fp, [r10, r3]
- cmp fp, r6
- bls .L836
- str r3, [sp, #20]
- bl GetFreeBlockMinEraseCount
- ldr r3, [sp, #20]
- cmp r0, r6
- strhi r7, [r4, #-3308]
-.L836:
- cmp fp, r8
- bcs .L831
- add r2, fp, #128
- cmp r9, r2
- ble .L831
- add r2, fp, #256
- cmp r2, r8
- bcc .L837
- ldr r2, [r4, #-3312]
- add fp, fp, #768
- cmp fp, r2
- bcs .L831
-.L837:
- ldr r2, [r4, #-3544]
- mov r1, r5
- ldr r0, .L850+16
- ldrh r2, [r2, r3]
- str r2, [sp]
- mov r2, r8
- ldrh r3, [r10, r3]
- stmib sp, {r3, r9}
- ldr r3, [r4, #-3312]
- bl printk
- mov r0, r5
- mov r3, #1
- str r3, [r4, #-2708]
-.L830:
+ beq .L823
+.L825:
+ movw r6, #65535
+.L824:
+ mov r0, r6
add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L851:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L817:
+ ldrh r0, [r2, #2]!
+ add r3, r3, #1
+ ldr ip, [r4, #-3324]
+ add r0, r0, ip
+ str r0, [r4, #-3324]
+ b .L816
+.L815:
+ ldr r3, [r4, #-3312]
+ cmp r2, r3
+ bls .L818
+ ldr ip, .L842+8
+ add r3, r3, #1
+ str r3, [r4, #-3312]
+ mov r3, #0
+.L820:
+ ldrh r2, [ip]
+ cmp r3, r2
+ bcs .L818
+ ldr r0, [r4, #-3604]
+ lsl r1, r3, #1
+ add r3, r3, #1
+ ldrh r2, [r0, r1]
+ add r2, r2, #1
+ strh r2, [r0, r1] @ movhi
+ b .L820
+.L823:
+ ldr r3, .L842+12
+ ldrh r0, [r3, #-4]
+ add r0, r0, r0, lsl #1
+ ubfx r0, r0, #2, #16
+ bl GetFreeBlockMaxEraseCount
+ add r1, r5, #64
+ mov r10, r0
+ cmp r0, r1
+ movcs r1, #0
+ movcc r1, #1
+ cmp r5, #40
+ movls r1, #0
+ cmp r1, #0
+ bne .L825
+ ldr r3, [r4, #-3544]
+ cmp r3, #0
+ beq .L825
+ ldr r0, .L842+4
+ movw r2, #2332
+ ldr ip, [r4, #-3548]
+ movw r7, #65535
+ ldr r9, [r4, #-3604]
+ mov fp, #6
+ ldrh r2, [r0, r2]
+ ldr lr, .L842+16
+ str r2, [sp, #20]
+ mov r2, r7
+.L826:
+ ldrh r0, [r3]
+ movw r6, #65535
+ cmp r0, r6
+ bne .L829
+ mov r6, r2
+.L828:
+ movw r3, #65535
+ cmp r6, r3
+ beq .L825
+ lsl fp, r6, #1
+ ldrh r1, [r9, fp]
+ cmp r5, r1
+ bcs .L830
+ bl GetFreeBlockMinEraseCount
+ cmp r5, r0
+ strcc r7, [r4, #-3308]
+.L830:
+ cmp r8, r1
+ bls .L825
+ add r3, r1, #128
+ cmp r10, r3
+ ble .L825
+ add r3, r1, #256
+ cmp r8, r3
+ bhi .L831
+ ldr r3, [r4, #-3312]
+ add r1, r1, #768
+ cmp r1, r3
+ bcs .L825
+.L831:
+ str r10, [sp, #8]
+ mov r2, r8
+ ldrh r3, [r9, fp]
+ mov r1, r6
+ ldr r0, .L842+20
+ str r3, [sp, #4]
+ ldr r3, [r4, #-3540]
+ ldrh r3, [r3, fp]
+ str r3, [sp]
+ ldr r3, [r4, #-3312]
+ bl printk
+ mov r3, #1
+ str r3, [r4, #-2708]
+ b .L824
+.L829:
+ add r1, r1, #1
+ ldr r6, [sp, #20]
+ uxth r1, r1
+ cmp r1, r6
+ bhi .L825
+ ldrh r6, [r3, #4]
+ cmp r6, #0
+ beq .L827
+ sub r3, r3, ip
+ asr r3, r3, #1
+ mul r3, lr, r3
+ uxth r6, r3
+ lsl r3, r6, #1
+ ldrh r3, [r9, r3]
+ cmp r5, r3
+ bcs .L828
+ cmp r7, r3
+ movhi r7, r3
+ movhi r2, r6
+.L827:
+ mla r3, fp, r0, ip
+ b .L826
+.L843:
.align 2
-.L850:
+.L842:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR0+2328
+ .word .LANCHOR0+2332
+ .word .LANCHOR2-3520
.word -1431655765
.word .LC78
.fnend
.size GetSwlReplaceBlock, .-GetSwlReplaceBlock
.align 2
.global free_data_superblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type free_data_superblock, %function
free_data_superblock:
.fnstart
@@ -5428,467 +5783,494 @@
@ frame_needed = 0, uses_anonymous_args = 0
movw r2, #65535
cmp r0, r2
- stmfd sp!, {r3, lr}
- .save {r3, lr}
- beq .L853
- ldr r2, .L855
- mov r3, r0, asl #1
+ beq .L847
+ ldr r2, .L850
+ lsl r3, r0, #1
+ push {r4, lr}
+ .save {r4, lr}
mov r1, #0
- ldr r2, [r2, #-3544]
+ ldr r2, [r2, #-3540]
strh r1, [r2, r3] @ movhi
bl INSERT_FREE_LIST
-.L853:
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L856:
+ pop {r4, pc}
+.L847:
+ mov r0, #0
+ bx lr
+.L851:
.align 2
-.L855:
+.L850:
.word .LANCHOR2
.fnend
.size free_data_superblock, .-free_data_superblock
.align 2
.global FtlGcBufInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcBufInit, %function
FtlGcBufInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L865
+ ldr ip, .L858
mov r3, #0
- ldr r1, .L865+4
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ ldr r2, .L858+4
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
- add r7, ip, #78
- mov r5, #12
- mov r6, #1
- mov r8, #36
- str r3, [r1, #-2704]
-.L858:
- ldrh r2, [ip]
- add r4, r3, #1
- uxth r3, r3
- cmp r3, r2
- bcs .L863
- mul r0, r5, r3
- ldr lr, [r1, #-2700]
- add r2, lr, r0
- str r6, [r2, #8]
- ldrh r2, [r7]
- mul r2, r2, r3
- add r9, r2, #3
- cmp r2, #0
- movlt r2, r9
- ldr r9, [r1, #-2696]
- bic r2, r2, #3
- add r2, r9, r2
- str r2, [lr, r0]
- ldr r2, .L865+8
- ldr r9, [r1, #-2700]
- ldrh r2, [r2]
- add lr, r9, r0
- mul r2, r2, r3
- add r10, r2, #3
- cmp r2, #0
- movlt r2, r10
- ldr r10, [r1, #-2692]
- bic r2, r2, #3
- add r2, r10, r2
- str r2, [lr, #4]
- ldr r2, [r1, #-2688]
- mla r3, r8, r3, r2
- ldr r2, [r9, r0]
- str r2, [r3, #8]
- ldr r2, [lr, #4]
- str r2, [r3, #12]
- mov r3, r4
- b .L858
-.L863:
- ldr r0, .L865+4
+ mov r4, #12
+ mov r5, #1
+ add r6, ip, #76
+ mov r7, #36
+ str r3, [r2, #-2704]
+.L853:
+ ldrh r1, [ip]
+ uxth r0, r3
+ add lr, r3, #1
+ cmp r0, r1
+ bcc .L854
+ ldr r4, .L858+8
mov ip, #12
- ldr r4, .L865+12
mov lr, #0
-.L860:
- ldr r3, [r1, #-2684]
- cmp r2, r3
- bcs .L864
- mul r5, ip, r2
- ldr r7, [r0, #-2700]
- add r3, r7, r5
+.L855:
+ ldr r3, [r2, #-2684]
+ cmp r1, r3
+ bcc .L856
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L854:
+ uxth r3, r3
+ ldr r8, [r2, #-2700]
+ mul r0, r4, r3
+ add r1, r8, r0
+ str r5, [r1, #8]
+ ldrh r1, [r6]
+ mul r1, r3, r1
+ add r9, r1, #3
+ cmp r1, #0
+ movlt r1, r9
+ ldr r9, [r2, #-2696]
+ bic r1, r1, #3
+ add r1, r9, r1
+ str r1, [r8, r0]
+ ldr r1, .L858+12
+ ldr r9, [r2, #-2700]
+ ldrh r1, [r1]
+ add r8, r9, r0
+ mul r1, r3, r1
+ add r10, r1, #3
+ cmp r1, #0
+ movlt r1, r10
+ ldr r10, [r2, #-2692]
+ bic r1, r1, #3
+ add r1, r10, r1
+ str r1, [r8, #4]
+ ldr r1, [r2, #-2688]
+ mla r3, r7, r3, r1
+ ldr r1, [r9, r0]
+ str r1, [r3, #8]
+ ldr r1, [r8, #4]
+ str r1, [r3, #12]
+ mov r3, lr
+ b .L853
+.L856:
+ mul r5, ip, r1
+ ldr r6, [r2, #-2700]
+ add r3, r6, r5
str lr, [r3, #8]
ldrh r3, [r4]
- mul r3, r3, r2
- add r6, r3, #3
+ mul r3, r1, r3
+ add r0, r3, #3
cmp r3, #0
- movlt r3, r6
- ldr r6, [r0, #-2696]
+ movlt r3, r0
+ ldr r0, [r2, #-2696]
bic r3, r3, #3
- add r3, r6, r3
- str r3, [r7, r5]
- ldr r3, .L865+8
- ldr r6, [r0, #-2700]
+ add r3, r0, r3
+ str r3, [r6, r5]
+ ldr r3, .L858+12
+ ldr r0, [r2, #-2700]
ldrh r3, [r3]
- add r5, r6, r5
- mul r3, r3, r2
- add r2, r2, #1
- uxth r2, r2
- add r6, r3, #3
+ add r0, r0, r5
+ mul r3, r1, r3
+ add r1, r1, #1
+ uxth r1, r1
+ add r5, r3, #3
cmp r3, #0
- movlt r3, r6
- ldr r6, [r0, #-2692]
+ movlt r3, r5
+ ldr r5, [r2, #-2692]
bic r3, r3, #3
- add r3, r6, r3
- str r3, [r5, #4]
- b .L860
-.L864:
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L866:
+ add r3, r5, r3
+ str r3, [r0, #4]
+ b .L855
+.L859:
.align 2
-.L865:
- .word .LANCHOR0+2320
+.L858:
+ .word .LANCHOR0+2324
.word .LANCHOR2
.word .LANCHOR0+2400
- .word .LANCHOR0+2398
+ .word .LANCHOR0+2402
.fnend
.size FtlGcBufInit, .-FtlGcBufInit
.align 2
.global FtlGcBufFree
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcBufFree, %function
FtlGcBufFree:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L875
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ ldr r3, .L868
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
mov lr, #0
- ldr r6, [r3, #-2684]
mov r5, #36
+ mov r7, #12
+ mov r8, lr
+ ldr r6, [r3, #-2684]
ldr r4, [r3, #-2700]
- mov r7, lr
- mov r8, #12
-.L868:
- uxth ip, lr
- cmp ip, r1
- ldmcsfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
- mla ip, r5, ip, r0
+.L861:
+ uxth r3, lr
+ cmp r1, r3
+ popls {r4, r5, r6, r7, r8, r9, r10, pc}
+ mla ip, r5, r3, r0
mov r2, #0
-.L869:
+.L862:
uxth r3, r2
- cmp r3, r6
- bcs .L870
- mul r3, r8, r3
+ cmp r6, r3
+ bls .L863
+ mul r3, r7, r3
add r2, r2, #1
- add r9, r4, r3
ldr r10, [r4, r3]
+ add r9, r4, r3
ldr r3, [ip, #8]
cmp r10, r3
- bne .L869
- str r7, [r9, #8]
-.L870:
+ bne .L862
+ str r8, [r9, #8]
+.L863:
add lr, lr, #1
- b .L868
-.L876:
+ b .L861
+.L869:
.align 2
-.L875:
+.L868:
.word .LANCHOR2
.fnend
.size FtlGcBufFree, .-FtlGcBufFree
.align 2
.global FtlGcBufAlloc
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcBufAlloc, %function
FtlGcBufAlloc:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L886
+ ldr r3, .L878
mov ip, #0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
+ push {r4, r5, r6, r7, r8, r9, lr}
.save {r4, r5, r6, r7, r8, r9, lr}
mov r6, #12
- ldr r4, [r3, #-2684]
mov r7, #1
- ldr r5, [r3, #-2700]
mov r8, #36
-.L878:
+ ldr r4, [r3, #-2684]
+ ldr r5, [r3, #-2700]
+.L871:
uxth r2, ip
- cmp r2, r1
- bcs .L885
+ cmp r1, r2
+ bhi .L875
+ pop {r4, r5, r6, r7, r8, r9, pc}
+.L875:
mov lr, #0
-.L879:
+.L872:
uxth r3, lr
- cmp r3, r4
- bcs .L880
+ cmp r4, r3
+ bls .L873
mla r3, r6, r3, r5
add lr, lr, #1
ldr r9, [r3, #8]
cmp r9, #0
- bne .L879
+ bne .L872
mla r2, r8, r2, r0
ldr lr, [r3]
str r7, [r3, #8]
str lr, [r2, #8]
ldr r3, [r3, #4]
str r3, [r2, #12]
-.L880:
+.L873:
add ip, ip, #1
- b .L878
-.L885:
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L887:
+ b .L871
+.L879:
.align 2
-.L886:
+.L878:
.word .LANCHOR2
.fnend
.size FtlGcBufAlloc, .-FtlGcBufAlloc
.align 2
.global IsBlkInGcList
+ .syntax unified
+ .arm
+ .fpu softvfp
.type IsBlkInGcList, %function
IsBlkInGcList:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L894
+ ldr r2, .L885
+ ldr r3, [r2, #-2680]
sub r2, r2, #2672
- ldr r3, [r2, #-8]
ldrh r2, [r2, #-4]
- add r2, r3, r2, asl #1
-.L889:
+ add r2, r3, r2, lsl #1
+.L881:
cmp r3, r2
- beq .L893
- ldrh r1, [r3], #2
- cmp r1, r0
- bne .L889
- mov r0, #1
- bx lr
-.L893:
+ bne .L883
mov r0, #0
bx lr
-.L895:
+.L883:
+ ldrh r1, [r3], #2
+ cmp r1, r0
+ bne .L881
+ mov r0, #1
+ bx lr
+.L886:
.align 2
-.L894:
+.L885:
.word .LANCHOR2
.fnend
.size IsBlkInGcList, .-IsBlkInGcList
.align 2
.global FtlGcUpdatePage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcUpdatePage, %function
FtlGcUpdatePage:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mov r4, r0
ubfx r0, r0, #10, #16
mov r5, r1
mov r6, r2
bl P2V_block_in_plane
- ldr r2, .L904
- mov lr, #0
- sub r3, r2, #2672
- ldr r8, [r2, #-2680]
- ldrh r1, [r3, #-4]
- sub r7, r8, #2
-.L897:
- uxth ip, lr
- cmp ip, r1
- bcs .L901
- ldrh r9, [r7, #2]!
- add lr, lr, #1
- cmp r9, r0
- bne .L897
-.L901:
- cmp ip, r1
- moveq ip, ip, asl #1
- streqh r0, [r8, ip] @ movhi
- ldreqh ip, [r3, #-4]
- addeq ip, ip, #1
- streqh ip, [r3, #-4] @ movhi
-.L899:
- ldr r3, .L904+4
- mov ip, #12
+ ldr r2, .L892
+ mov r3, #0
+ sub ip, r2, #2672
+ ldr lr, [r2, #-2680]
+ ldrh r7, [ip, #-4]
+ sub r1, lr, #2
+.L888:
+ uxth r8, r3
+ cmp r8, r7
+ bcc .L890
+ moveq r3, r8
+ lsleq r3, r3, #1
+ strheq r0, [lr, r3] @ movhi
+ ldrheq r3, [ip, #-4]
+ addeq r3, r3, #1
+ strheq r3, [ip, #-4] @ movhi
+ b .L889
+.L890:
+ ldrh r8, [r1, #2]!
+ add r3, r3, #1
+ cmp r8, r0
+ bne .L888
+.L889:
+ ldr r0, .L892+4
+ mov r3, #12
ldr r2, [r2, #-2672]
- ldrh r1, [r3, #-12]
- mul ip, ip, r1
- add r1, r2, ip
+ ldrh r1, [r0, #-12]
+ mul r3, r3, r1
+ add r1, r2, r3
stmib r1, {r5, r6}
- str r4, [r2, ip]
- ldrh r2, [r3, #-12]
- add r2, r2, #1
- strh r2, [r3, #-12] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L905:
+ str r4, [r2, r3]
+ ldrh r3, [r0, #-12]
+ add r3, r3, #1
+ strh r3, [r0, #-12] @ movhi
+ pop {r4, r5, r6, r7, r8, pc}
+.L893:
.align 2
-.L904:
+.L892:
.word .LANCHOR2
.word .LANCHOR2-2656
.fnend
.size FtlGcUpdatePage, .-FtlGcUpdatePage
.align 2
.global FtlGcRefreshOpenBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcRefreshOpenBlock, %function
FtlGcRefreshOpenBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r5, r0
- ldr r4, .L914
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r4, .L902
ldrh r3, [r4, #-10]
cmp r3, r0
- beq .L908
+ beq .L896
ldrh r3, [r4, #-8]
cmp r3, r0
- beq .L908
+ beq .L896
ldrh r3, [r4, #-6]
cmp r3, r0
- beq .L908
+ beq .L896
ldrh r3, [r4, #-4]
cmp r3, r0
- beq .L908
- ldr r0, .L914+4
- mov r1, r5
+ beq .L896
+ mov r5, r0
+ mov r1, r0
+ ldr r0, .L902+4
bl printk
ldrh r2, [r4, #-10]
movw r3, #65535
cmp r2, r3
- streqh r5, [r4, #-10] @ movhi
- beq .L908
+ strheq r5, [r4, #-10] @ movhi
+ beq .L896
ldrh r2, [r4, #-8]
cmp r2, r3
- streqh r5, [r4, #-8] @ movhi
- beq .L908
+ strheq r5, [r4, #-8] @ movhi
+ beq .L896
ldrh r2, [r4, #-6]
cmp r2, r3
- streqh r5, [r4, #-6] @ movhi
- beq .L908
+ strheq r5, [r4, #-6] @ movhi
+ beq .L896
ldrh r2, [r4, #-4]
cmp r2, r3
- streqh r5, [r4, #-4] @ movhi
-.L908:
+ strheq r5, [r4, #-4] @ movhi
+.L896:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L915:
+ pop {r4, r5, r6, pc}
+.L903:
.align 2
-.L914:
+.L902:
.word .LANCHOR2-2656
.word .LC79
.fnend
.size FtlGcRefreshOpenBlock, .-FtlGcRefreshOpenBlock
.align 2
.global FtlGcRefreshBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcRefreshBlock, %function
FtlGcRefreshBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r5, r0
- ldr r4, .L927
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r4, .L915
ldrh r3, [r4, #-10]
cmp r3, r0
- beq .L924
+ beq .L912
ldrh r3, [r4, #-8]
cmp r3, r0
- beq .L924
+ beq .L912
ldrh r3, [r4, #-6]
cmp r3, r0
- beq .L924
+ beq .L912
ldrh r3, [r4, #-4]
cmp r3, r0
- beq .L924
- ldr r0, .L927+4
- mov r1, r5
+ beq .L912
+ mov r5, r0
+ mov r1, r0
+ ldr r0, .L915+4
bl printk
ldrh r2, [r4, #-10]
movw r3, #65535
cmp r2, r3
- streqh r5, [r4, #-10] @ movhi
- beq .L924
+ strheq r5, [r4, #-10] @ movhi
+ beq .L912
ldrh r2, [r4, #-8]
cmp r2, r3
- streqh r5, [r4, #-8] @ movhi
- beq .L924
+ strheq r5, [r4, #-8] @ movhi
+ beq .L912
ldrh r2, [r4, #-6]
cmp r2, r3
- streqh r5, [r4, #-6] @ movhi
- beq .L924
+ strheq r5, [r4, #-6] @ movhi
+ beq .L912
ldrh r2, [r4, #-4]
cmp r2, r3
- bne .L925
+ bne .L913
strh r5, [r4, #-4] @ movhi
-.L924:
+.L912:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L925:
+ pop {r4, r5, r6, pc}
+.L913:
mvn r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L928:
+ pop {r4, r5, r6, pc}
+.L916:
.align 2
-.L927:
+.L915:
.word .LANCHOR2-2656
.word .LC79
.fnend
.size FtlGcRefreshBlock, .-FtlGcRefreshBlock
.align 2
.global FtlGcMarkBadPhyBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcMarkBadPhyBlk, %function
FtlGcMarkBadPhyBlk:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mov r5, r0
+ ldr r6, .L926
bl P2V_block_in_plane
- ldr r6, .L939
- mov r2, r5
sub r7, r6, #2656
- ldrh r1, [r7, #-2]
mov r4, r0
- ldr r0, .L939+4
+ mov r2, r5
+ ldrh r1, [r7, #-2]
+ ldr r0, .L926+4
bl printk
mov r0, r4
bl FtlGcRefreshBlock
- ldr r3, .L939+8
- ldr r3, [r3, #2244]
+ ldr r3, .L926+8
+ ldr r3, [r3, #2248]
cmp r3, #0
mov r3, r7
- beq .L930
- ldr r1, [r6, #-3608]
- mov r4, r4, asl #1
+ beq .L918
+ ldr r1, [r6, #-3604]
+ lsl r4, r4, #1
ldrh r2, [r1, r4]
cmp r2, #39
subhi r2, r2, #40
- strhih r2, [r1, r4] @ movhi
-.L930:
+ strhhi r2, [r1, r4] @ movhi
+.L918:
ldrh r2, [r3, #-2]
mov r1, #0
-.L931:
+.L919:
uxth r0, r1
- cmp r0, r2
- bcs .L938
- add r1, r1, #1
- add r0, r3, r1, asl #1
- ldrh r0, [r0, #-2]
- cmp r0, r5
- bne .L931
- b .L932
-.L938:
+ cmp r2, r0
+ bhi .L921
cmp r2, #15
addls r1, r2, #1
- movls r2, r2, asl #1
- strlsh r1, [r3, #-2] @ movhi
- strlsh r5, [r3, r2] @ movhi
-.L932:
+ lslls r2, r2, #1
+ strhls r1, [r3, #-2] @ movhi
+ strhls r5, [r3, r2] @ movhi
+ b .L920
+.L921:
+ add r1, r1, #1
+ add r0, r3, r1, lsl #1
+ ldrh r0, [r0, #-2]
+ cmp r0, r5
+ bne .L919
+.L920:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L940:
+ pop {r4, r5, r6, r7, r8, pc}
+.L927:
.align 2
-.L939:
+.L926:
.word .LANCHOR2
.word .LC80
.word .LANCHOR0
@@ -5896,28 +6278,31 @@
.size FtlGcMarkBadPhyBlk, .-FtlGcMarkBadPhyBlk
.align 2
.global FtlGcReFreshBadBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcReFreshBadBlk, %function
FtlGcReFreshBadBlk:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L949
+ ldr r3, .L938
ldrh r2, [r3, #-2]
cmp r2, #0
- beq .L948
+ beq .L935
ldrh r0, [r3, #-10]
movw r1, #65535
cmp r0, r1
- bne .L948
- stmfd sp!, {r4, lr}
+ bne .L935
+ push {r4, lr}
.save {r4, lr}
add r4, r3, #48
ldrh r1, [r4, #-14]
cmp r1, r2
movcs r2, #0
- strcsh r2, [r4, #-14] @ movhi
+ strhcs r2, [r4, #-14] @ movhi
ldrh r2, [r4, #-14]
- mov r2, r2, asl #1
+ lsl r2, r2, #1
ldrh r0, [r3, r2]
bl P2V_block_in_plane
bl FtlGcRefreshBlock
@@ -5925,18 +6310,21 @@
mov r0, #0
add r3, r3, #1
strh r3, [r4, #-14] @ movhi
- ldmfd sp!, {r4, pc}
-.L948:
+ pop {r4, pc}
+.L935:
mov r0, #0
bx lr
-.L950:
+.L939:
.align 2
-.L949:
+.L938:
.word .LANCHOR2-2656
.fnend
.size FtlGcReFreshBadBlk, .-FtlGcReFreshBadBlk
.align 2
.global ftl_memset
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_memset, %function
ftl_memset:
.fnstart
@@ -5948,459 +6336,470 @@
.size ftl_memset, .-ftl_memset
.align 2
.global BuildFlashLsbPageTable
+ .syntax unified
+ .arm
+ .fpu softvfp
.type BuildFlashLsbPageTable, %function
BuildFlashLsbPageTable:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
cmp r0, #0
- stmfd sp!, {r4, lr}
- .save {r4, lr}
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r4, r1
- bne .L953
- ldr r3, .L996
-.L954:
- mov r2, r0, asl #1
+ bne .L942
+ ldr r3, .L998
+.L943:
+ lsl r2, r0, #1
strh r0, [r2, r3] @ movhi
add r0, r0, #1
cmp r0, #512
- bne .L954
-.L958:
+ bne .L943
+.L949:
+ ldr r5, .L998+4
mov r1, #255
- ldr r0, .L996+4
mov r2, #2048
uxth r4, r4
+ sub r0, r5, #12
+ sub r5, r5, #12
bl ftl_memset
+ ldr r1, .L998
mov r3, #0
- ldr r1, .L996
- ldr r0, .L996+4
- b .L955
-.L953:
+.L944:
+ uxth r2, r3
+ cmp r4, r2
+ bhi .L977
+ pop {r4, r5, r6, pc}
+.L942:
cmp r0, #1
- bne .L956
- ldr ip, .L996
+ bne .L945
+ ldr r1, .L998
mov r3, #0
-.L957:
+.L948:
+ cmp r3, #3
uxth r2, r3
- mov lr, r3, asl #1
- cmp r2, #3
- movls r0, #0
- movhi r0, #1
- bics r1, r0, r3
+ bls .L946
+ tst r2, #1
+ movne r0, #3
+ moveq r0, #2
+ rsb r2, r0, r2, lsl #1
+ uxth r2, r2
+.L946:
+ lsl r0, r3, #1
add r3, r3, #1
- movne r1, #2
- moveq r1, #3
- cmp r0, #0
- rsb r1, r1, r2, asl #1
- movne r2, r1
- cmp r3, #512
- strh r2, [lr, ip] @ movhi
- bne .L957
- b .L958
-.L956:
- cmp r0, #2
- bne .L959
- ldr r1, .L996
- mov r3, #0
-.L960:
- uxth r2, r3
- mov r0, r3, asl #1
- cmp r2, #1
- add r3, r3, #1
- mov ip, r2, asl #1
- subhi r2, ip, #1
cmp r3, #512
strh r2, [r0, r1] @ movhi
- bne .L960
- b .L958
-.L959:
+ bne .L948
+ b .L949
+.L945:
+ cmp r0, #2
+ bne .L950
+ ldr r1, .L998
+ mov r2, #0
+.L952:
+ uxth r3, r2
+ cmp r2, #1
+ lsl r0, r2, #1
+ add r2, r2, #1
+ lslhi r3, r3, #1
+ subhi r3, r3, #1
+ uxthhi r3, r3
+ cmp r2, #512
+ strh r3, [r0, r1] @ movhi
+ bne .L952
+ b .L949
+.L950:
cmp r0, #3
- bne .L961
- ldr ip, .L996
+ bne .L953
+ ldr r1, .L998
mov r3, #0
-.L962:
+.L956:
+ cmp r3, #5
uxth r2, r3
- mov lr, r3, asl #1
- cmp r2, #5
- movls r0, #0
- movhi r0, #1
- bics r1, r0, r3
+ bls .L954
+ tst r2, #1
+ movne r0, #5
+ moveq r0, #4
+ rsb r2, r0, r2, lsl #1
+ uxth r2, r2
+.L954:
+ lsl r0, r3, #1
add r3, r3, #1
- movne r1, #4
- moveq r1, #5
- cmp r0, #0
- rsb r1, r1, r2, asl #1
- movne r2, r1
cmp r3, #512
- strh r2, [lr, ip] @ movhi
- bne .L962
- b .L958
-.L961:
+ strh r2, [r0, r1] @ movhi
+ bne .L956
+ b .L949
+.L953:
cmp r0, #4
mov r3, #0
- bne .L963
- ldr r2, .L996+8
- strh r3, [r2, #148] @ movhi
+ bne .L957
+ ldr r2, .L998+8
+ strh r3, [r2, #156] @ movhi
mov r3, #1
- strh r0, [r2, #156] @ movhi
- strh r3, [r2, #150] @ movhi
- mov r3, #2
- strh r3, [r2, #152] @ movhi
- mov r3, #3
- strh r3, [r2, #154] @ movhi
- mov r3, #5
strh r3, [r2, #158] @ movhi
- mov r3, #7
+ mov r3, #2
strh r3, [r2, #160] @ movhi
+ mov r3, #3
+ strh r3, [r2, #162] @ movhi
+ mov r3, #5
+ strh r3, [r2, #166] @ movhi
+ mov r3, #7
+ strh r3, [r2, #168] @ movhi
mov r3, #8
- strh r3, [r2, #162]! @ movhi
-.L964:
+ strh r0, [r2, #164] @ movhi
+ strh r3, [r2, #170]! @ movhi
+.L959:
tst r3, #1
movne r1, #7
moveq r1, #6
- rsb r1, r1, r3, asl #1
+ rsb r1, r1, r3, lsl #1
add r3, r3, #1
- strh r1, [r2, #2]! @ movhi
uxth r3, r3
+ strh r1, [r2, #2]! @ movhi
cmp r3, #512
- bne .L964
- b .L958
-.L963:
+ bne .L959
+ b .L949
+.L957:
cmp r0, #5
- bne .L965
- ldr r2, .L996
-.L966:
- mov r1, r3, asl #1
- strh r3, [r1, r2] @ movhi
+ bne .L960
+ ldr r2, .L998+8
+ add r1, r2, #156
+.L961:
+ lsl r0, r3, #1
+ strh r3, [r0, r1] @ movhi
add r3, r3, #1
cmp r3, #16
- bne .L966
- ldr r2, .L996+12
-.L967:
+ bne .L961
+ add r2, r2, #186
+.L962:
strh r3, [r2, #2]! @ movhi
add r3, r3, #2
uxth r3, r3
cmp r3, #1008
- bne .L967
- b .L958
-.L965:
+ bne .L962
+ b .L949
+.L960:
cmp r0, #6
- bne .L968
- ldr r1, .L996+16
-.L969:
- cmp r3, #5
- add r2, r3, r3, asl #1
- movls r0, #0
- movhi r0, #1
- bics ip, r0, r3
- movne ip, #10
- moveq ip, #12
- cmp r0, #0
- subne r2, r2, ip
- moveq r2, r3
- add r3, r3, #1
- strh r2, [r1, #2]! @ movhi
+ bne .L963
+ ldr r0, .L998
+ mov r1, r3
+.L966:
+ cmp r1, #5
+ uxth r2, r1
+ bls .L964
+ tst r2, #1
+ movne r2, #12
+ moveq r2, #10
+ sub r2, r3, r2
+ uxth r2, r2
+.L964:
+ lsl ip, r1, #1
+ add r1, r1, #1
+ cmp r1, #512
+ add r3, r3, #3
+ strh r2, [ip, r0] @ movhi
uxth r3, r3
- cmp r3, #512
- bne .L969
- b .L958
-.L968:
+ bne .L966
+ b .L949
+.L963:
cmp r0, #9
- bne .L970
- ldr r2, .L996+8
+ bne .L967
+ ldr r2, .L998+8
movw r1, #1021
- strh r3, [r2, #148] @ movhi
+ strh r3, [r2, #156] @ movhi
mov r3, #1
- strh r3, [r2, #150] @ movhi
- mov r3, #2
- strh r3, [r2, #152]! @ movhi
- mov r3, #3
+ strh r3, [r2, #158] @ movhi
+ mov r3, r2
+ mov r2, #2
+ strh r2, [r3, #160]! @ movhi
+ mov r2, #3
+.L968:
+ strh r2, [r3, #2]! @ movhi
+ add r2, r2, #2
+ uxth r2, r2
+ cmp r2, r1
+ bne .L968
+ b .L949
+.L967:
+ cmp r0, #10
+ bne .L969
+ ldr r2, .L998+8
+ add r1, r2, #156
+.L970:
+ lsl r0, r3, #1
+ strh r3, [r0, r1] @ movhi
+ add r3, r3, #1
+ cmp r3, #63
+ bne .L970
+ add r2, r2, #280
+ movw r1, #961
.L971:
strh r3, [r2, #2]! @ movhi
add r3, r3, #2
uxth r3, r3
cmp r3, r1
bne .L971
- b .L958
-.L970:
- cmp r0, #10
- bne .L972
- ldr r2, .L996
-.L973:
- mov r1, r3, asl #1
- strh r3, [r1, r2] @ movhi
- add r3, r3, #1
- cmp r3, #63
- bne .L973
- ldr r2, .L996+20
- movw r1, #961
-.L974:
- strh r3, [r2, #2]! @ movhi
- add r3, r3, #2
- uxth r3, r3
- cmp r3, r1
- bne .L974
- b .L958
-.L972:
+ b .L949
+.L969:
cmp r0, #11
- bne .L975
- ldr r2, .L996
+ bne .L972
+ ldr r2, .L998+8
mov r3, #0
-.L976:
- mov r1, r3, asl #1
- strh r3, [r1, r2] @ movhi
+ add r1, r2, #156
+.L973:
+ lsl r0, r3, #1
+ strh r3, [r0, r1] @ movhi
add r3, r3, #1
cmp r3, #8
- bne .L976
- ldr r1, .L996+24
-.L977:
- tst r3, #1
- movne r2, #7
- moveq r2, #6
- rsb r2, r2, r3, asl #1
- add r3, r3, #1
- strh r2, [r1, #2]! @ movhi
- uxth r3, r3
- cmp r3, #512
- bne .L977
- b .L958
+ bne .L973
+ add r2, r2, #170
.L975:
+ tst r3, #1
+ movne r1, #7
+ moveq r1, #6
+ rsb r1, r1, r3, lsl #1
+ add r3, r3, #1
+ uxth r3, r3
+ strh r1, [r2, #2]! @ movhi
+ cmp r3, #512
+ bne .L975
+ b .L949
+.L972:
cmp r0, #12
- bne .L958
- ldr r3, .L996+8
+ bne .L949
+ ldr r3, .L998+8
mov r2, #0
- strh r2, [r3, #148] @ movhi
+ strh r2, [r3, #156] @ movhi
mov r2, #1
- strh r2, [r3, #150] @ movhi
+ strh r2, [r3, #158] @ movhi
mov r2, #2
- strh r2, [r3, #152] @ movhi
+ strh r2, [r3, #160] @ movhi
mov r2, #3
- strh r2, [r3, #154]! @ movhi
+ strh r2, [r3, #162]! @ movhi
mov r2, #4
-.L978:
+.L976:
sub r1, r2, #1
add r1, r1, r2, lsr #1
add r2, r2, #1
- strh r1, [r3, #2]! @ movhi
uxth r2, r2
+ strh r1, [r3, #2]! @ movhi
cmp r2, #512
- bne .L978
- b .L958
-.L955:
- uxth r2, r3
- cmp r2, r4
- bcs .L995
- mov r2, r3, asl #1
+ bne .L976
+ b .L949
+.L977:
+ lsl r2, r3, #1
add r3, r3, #1
ldrh r2, [r2, r1]
- mov ip, r2, asl #1
- strh r2, [r0, ip] @ movhi
- b .L955
-.L995:
- ldmfd sp!, {r4, pc}
-.L997:
+ lsl r0, r2, #1
+ strh r2, [r5, r0] @ movhi
+ b .L944
+.L999:
.align 2
-.L996:
- .word .LANCHOR0+148
- .word .LANCHOR2-2620
+.L998:
+ .word .LANCHOR0+156
+ .word .LANCHOR2-2608
.word .LANCHOR0
- .word .LANCHOR0+178
- .word .LANCHOR0+146
- .word .LANCHOR0+272
- .word .LANCHOR0+162
.fnend
.size BuildFlashLsbPageTable, .-BuildFlashLsbPageTable
.align 2
.global FlashDieInfoInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashDieInfoInit, %function
FlashDieInfoInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L1015
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r6, #0
- ldr r3, .L1013
- ldr r5, .L1013+4
- ldr r9, .L1013+8
+ ldr r4, .L1015+4
+ ldr r10, .L1015+8
ldrh r0, [r3, #10]
- strb r6, [r5, #2230]
- mov r7, r5
- strb r6, [r9, #-572]
+ strb r6, [r4, #2234]
+ strb r6, [r10, #-572]
bl FlashBlockAlignInit
- mov r1, r6
mov r2, #8
- ldr r0, .L1013+12
- bl ftl_memset
mov r1, r6
+ ldr r0, .L1015+12
+ bl ftl_memset
mov r2, #32
- ldr r0, .L1013+16
- bl ftl_memset
- ldr r0, .L1013+20
mov r1, r6
- mov r2, #128
+ ldr r0, .L1015+16
bl ftl_memset
- ldr r4, [r5, #44]
- ldr fp, .L1013+24
- add r8, r4, #1
-.L1000:
- mov r0, r8
- add r1, fp, r6, asl #3
- ldrb r2, [r4] @ zero_extendqisi2
- bl FlashMemCmp8
- ldr r10, .L1013+24
- cmp r0, #0
- bne .L999
- ldrb r3, [r7, #2230] @ zero_extendqisi2
- add r2, r7, r3, asl #2
- str r0, [r2, #1172]
- add r2, r3, #1
- add r3, r7, r3
- strb r2, [r7, #2230]
- strb r6, [r3, #2232]
-.L999:
- add r6, r6, #1
- cmp r6, #4
- bne .L1000
- ldrb r3, [r5, #2230] @ zero_extendqisi2
- ldr r7, .L1013+4
- strb r3, [r9, #-572]
- ldrb r3, [r4, #8] @ zero_extendqisi2
- cmp r3, #2
- beq .L1001
-.L1005:
- ldrb r3, [r4, #13] @ zero_extendqisi2
- ldrb r2, [r5, #2230] @ zero_extendqisi2
- smulbb r2, r2, r3
- ldrh r3, [r4, #14]
- smulbb r3, r2, r3
- ldr r2, .L1013+28
- strh r3, [r2, #-2] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1001:
- ldr r9, [r7, #4]
- mov r6, #0
-.L1004:
- mov r0, r8
- add r1, r10, r6, asl #3
- ldrb r2, [r4] @ zero_extendqisi2
- bl FlashMemCmp8
- cmp r0, #0
- bne .L1002
- ldrb r1, [r4, #13] @ zero_extendqisi2
- ldrh r3, [r4, #14]
- ldrb r2, [r7, #2230] @ zero_extendqisi2
- mul r1, r9, r1
- and r3, r3, #65280
- add r0, r7, r2, asl #2
- mul r3, r3, r1
- str r3, [r0, #1172]
- ldrb r1, [r4, #23] @ zero_extendqisi2
- cmp r1, #0
- movne r3, r3, asl #1
- strne r3, [r0, #1172]
- add r3, r2, #1
- add r2, r5, r2
- strb r3, [r5, #2230]
- strb r6, [r2, #2232]
+ mov r2, #128
+ mov r1, r6
+ ldr r0, .L1015+20
+ bl ftl_memset
+ ldr r9, .L1015+24
+ ldr r5, [r4, #48]
+ mov r8, r9
+ add r7, r5, #1
.L1002:
+ ldrb r2, [r5] @ zero_extendqisi2
+ add r1, r9, r6, lsl #3
+ mov r0, r7
+ bl FlashMemCmp8
+ cmp r0, #0
+ bne .L1001
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ add r2, r4, r3, lsl #2
+ str r0, [r2, #1180]
+ add r2, r3, #1
+ add r3, r4, r3
+ strb r2, [r4, #2234]
+ strb r6, [r3, #2236]
+.L1001:
add r6, r6, #1
cmp r6, #4
+ bne .L1002
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ strb r3, [r10, #-572]
+ ldrb r3, [r5, #8] @ zero_extendqisi2
+ cmp r3, #2
+ beq .L1003
+.L1007:
+ ldrh r2, [r5, #14]
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ smulbb r3, r3, r2
+ ldrb r2, [r5, #13] @ zero_extendqisi2
+ smulbb r3, r3, r2
+ ldr r2, .L1015+28
+ strh r3, [r2, #-2] @ movhi
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1003:
+ ldr r9, [r4, #40]
+ mov r6, #0
+.L1006:
+ ldrb r2, [r5] @ zero_extendqisi2
+ add r1, r8, r6, lsl #3
+ mov r0, r7
+ bl FlashMemCmp8
+ cmp r0, #0
bne .L1004
- b .L1005
-.L1014:
+ ldrh r3, [r5, #14]
+ ldrb r2, [r4, #2234] @ zero_extendqisi2
+ and r1, r3, #65280
+ ldrb r3, [r5, #13] @ zero_extendqisi2
+ mul r3, r9, r3
+ mul r3, r3, r1
+ add r1, r4, r2, lsl #2
+ str r3, [r1, #1180]
+ ldrb r0, [r5, #23] @ zero_extendqisi2
+ cmp r0, #0
+ lslne r3, r3, #1
+ strne r3, [r1, #1180]
+ add r3, r2, #1
+ add r2, r4, r2
+ strb r3, [r4, #2234]
+ strb r6, [r2, #2236]
+.L1004:
+ add r6, r6, #1
+ cmp r6, #4
+ bne .L1006
+ b .L1007
+.L1016:
.align 2
-.L1013:
- .word .LANCHOR1+472
+.L1015:
+ .word .LANCHOR1+468
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2232
- .word .LANCHOR0+1172
- .word .LANCHOR0+2100
- .word .LANCHOR0+2068
+ .word .LANCHOR0+2236
+ .word .LANCHOR0+1180
+ .word .LANCHOR0+2104
+ .word .LANCHOR0+2072
.word .LANCHOR2-568
.fnend
.size FlashDieInfoInit, .-FlashDieInfoInit
.align 2
.global ftl_read_flash_info
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_read_flash_info, %function
ftl_read_flash_info:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, lr}
+ push {r4, lr}
.save {r4, lr}
- mov r1, #0
mov r2, #11
+ mov r1, #0
mov r4, r0
bl ftl_memset
- ldr r2, .L1020
- ldr r0, .L1020+4
+ ldr r2, .L1021
mov ip, #1
- ldr r3, [r2, #44]
- ldrb r1, [r3, #9] @ zero_extendqisi2
- ldr r3, [r2, #4]
- smulbb r3, r1, r3
+ ldr r0, .L1021+4
+ ldr r3, [r2, #48]
+ ldr r1, [r2, #40]
+ ldrb r3, [r3, #9] @ zero_extendqisi2
+ smulbb r3, r3, r1
strh r3, [r4, #4] @ unaligned
- ldrb r3, [r2, #2312] @ zero_extendqisi2
+ ldrb r3, [r2, #2316] @ zero_extendqisi2
strb r3, [r4, #7]
- ldr r3, [r2, #2428]
+ ldr r3, [r2, #2432]
str r3, [r4] @ unaligned
- ldr r3, [r2, #44]
+ ldr r3, [r2, #48]
ldrb r1, [r3, #9] @ zero_extendqisi2
strb r1, [r4, #6]
mov r1, #32
strb r1, [r4, #8]
- ldrb r1, [r2, #2230] @ zero_extendqisi2
+ ldrb r1, [r2, #2234] @ zero_extendqisi2
ldrb r3, [r3, #7] @ zero_extendqisi2
strb r3, [r4, #9]
mov r3, #0
strb r3, [r4, #10]
-.L1016:
+.L1018:
uxtb r2, r3
- cmp r2, r1
- bcs .L1019
+ cmp r1, r2
+ bhi .L1019
+ pop {r4, pc}
+.L1019:
ldrb lr, [r3, r0] @ zero_extendqisi2
add r3, r3, #1
ldrb r2, [r4, #10] @ zero_extendqisi2
- orr r2, r2, ip, asl lr
+ orr r2, r2, ip, lsl lr
strb r2, [r4, #10]
- b .L1016
-.L1019:
- ldmfd sp!, {r4, pc}
-.L1021:
+ b .L1018
+.L1022:
.align 2
-.L1020:
+.L1021:
.word .LANCHOR0
- .word .LANCHOR0+2232
+ .word .LANCHOR0+2236
.fnend
.size ftl_read_flash_info, .-ftl_read_flash_info
.align 2
.global FtlMemInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlMemInit, %function
FtlMemInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r6, #0
- ldr r4, .L1127
+ ldr r4, .L1126
mvn r2, #0
- ldr r5, .L1127+4
mov r1, #32
- sub r3, r4, #568
mov r0, #1024
+ ldr r5, .L1126+4
+ mov r8, #12
+ sub r3, r4, #568
str r6, [r4, #-564]
- add r7, r5, #2320
strh r6, [r3] @ movhi
movw r3, #65535
str r3, [r4, #-556]
sub r3, r4, #2656
- str r6, [r4, #-3236]
- mov r8, #36
strh r2, [r3, #-10] @ movhi
+ movw r9, #2324
strh r2, [r3, #-8] @ movhi
+ mov r7, #36
strh r2, [r3, #-6] @ movhi
strh r2, [r3, #-4] @ movhi
sub r2, r4, #2720
@@ -6409,12 +6808,11 @@
strh r1, [r2] @ movhi
sub r2, r4, #2704
strh r6, [r3] @ movhi
- sub r3, r4, #2608
- strh r6, [r2, #-8] @ movhi
mov r1, #128
- strh r6, [r3, #-14] @ movhi
- movw r3, #2394
+ sub r3, r4, #2608
strh r1, [r2, #-14] @ movhi
+ strh r6, [r2, #-8] @ movhi
+ str r6, [r4, #-2724]
str r6, [r4, #-3332]
str r6, [r4, #-3328]
str r6, [r4, #-3344]
@@ -6425,7 +6823,7 @@
str r6, [r4, #-3364]
str r6, [r4, #-3324]
str r6, [r4, #-3320]
- str r6, [r4, #-3604]
+ str r6, [r4, #-3600]
str r6, [r4, #-3312]
str r6, [r4, #-3308]
str r6, [r4, #-560]
@@ -6433,27 +6831,29 @@
str r6, [r4, #-552]
str r6, [r4, #-2716]
str r6, [r4, #-548]
+ strh r6, [r3, #-14] @ movhi
+ movw r3, #2396
ldrh r1, [r5, r3]
bl __aeabi_idiv
- ldrh r10, [r7]
- str r6, [r5, #2440]
- movw r6, #2392
- mov r9, r10, asl #2
- cmp r0, r9
+ movw r3, #2324
+ str r6, [r5, #2444]
+ ldrh r3, [r5, r3]
+ movw r6, #2394
str r0, [r4, #-540]
+ lsl r3, r3, #2
+ cmp r0, r3
ldrh r0, [r5, r6]
- strhi r9, [r4, #-540]
- mov r9, #12
- mov r0, r0, asl #1
+ strhi r3, [r4, #-540]
+ lsl r0, r0, #1
bl ftl_malloc
str r0, [r4, #-2680]
ldrh r0, [r5, r6]
- mul r0, r9, r0
+ mul r0, r8, r0
bl ftl_malloc
- ldrh r6, [r7]
- mul r6, r8, r6
- mov r10, r6, asl #3
+ ldrh r6, [r5, r9]
str r0, [r4, #-2672]
+ mul r6, r7, r6
+ lsl r10, r6, #3
mov r0, r10
bl ftl_malloc
str r0, [r4, #-536]
@@ -6462,421 +6862,437 @@
str r0, [r4, #-532]
mov r0, r10
bl ftl_malloc
- movw r10, #2398
str r0, [r4, #-528]
mov r0, r6
bl ftl_malloc
- str r0, [r4, #-3612]
+ str r0, [r4, #-3608]
mov r0, r6
bl ftl_malloc
str r0, [r4, #-2688]
+ movw r10, #2402
ldr r0, [r4, #-540]
- mul r0, r8, r0
+ ldr r6, .L1126+8
+ mul r0, r7, r0
bl ftl_malloc
- ldrh r6, [r5, r10]
- ldrh r3, [r7]
- movw r8, #2330
- mov r3, r3, asl #1
+ ldrh r3, [r5, r9]
+ ldrh r7, [r6]
+ str r0, [r5, #2448]
+ lsl r3, r3, #1
+ mov r0, r7
add r3, r3, #1
str r3, [r4, #-2684]
- str r0, [r5, #2444]
- mov r0, r6
bl ftl_malloc
str r0, [r4, #-524]
- mov r0, r6
+ mov r0, r7
bl ftl_malloc
str r0, [r4, #-520]
- mov r0, r6
+ mov r0, r7
bl ftl_malloc
str r0, [r4, #-516]
ldr r0, [r4, #-2684]
- mul r0, r0, r6
+ mul r0, r0, r7
bl ftl_malloc
str r0, [r4, #-2696]
ldr r0, [r4, #-540]
- mul r0, r0, r6
+ mul r0, r0, r7
bl ftl_malloc
str r0, [r4, #-512]
- mov r0, r6
+ mov r0, r7
bl ftl_malloc
str r0, [r4, #-508]
- mov r0, r6
+ mov r0, r7
bl ftl_malloc
- ldr r6, .L1127+8
str r0, [r4, #-504]
ldr r0, [r4, #-2684]
- mul r0, r9, r0
+ mul r0, r8, r0
bl ftl_malloc
- ldrh r3, [r6]
- ldrh r7, [r7]
- mul r7, r7, r3
+ ldrh r3, [r5, r10]
+ ldrh r7, [r5, r9]
+ movw r9, #2334
str r0, [r4, #-2700]
+ mul r7, r7, r3
mov r0, r7
bl ftl_malloc
str r0, [r4, #-500]
- mov r0, r7, asl #3
+ lsl r0, r7, #3
+ ldr r7, .L1126+12
bl ftl_malloc
- ldrh r3, [r6]
- ldr r7, .L1127+12
+ ldrh r3, [r5, r10]
str r0, [r4, #-496]
ldr r0, [r4, #-2684]
mul r0, r0, r3
bl ftl_malloc
- ldrh r3, [r6], #80
+ ldrh r3, [r5, r10]
str r0, [r4, #-2692]
ldr r0, [r4, #-540]
mul r0, r0, r3
bl ftl_malloc
str r0, [r4, #-492]
- ldrh r0, [r5, r8]
- mov r0, r0, asl #1
+ ldrh r0, [r5, r9]
+ lsl r0, r0, #1
uxth r0, r0
strh r0, [r7] @ movhi
bl ftl_malloc
str r0, [r4, #-484]
ldrh r0, [r7]
+ ldr r3, .L1126+16
add r0, r0, #544
add r0, r0, #3
- mov r0, r0, lsr #9
+ lsr r0, r0, #9
strh r0, [r7] @ movhi
- mov r0, r0, asl #9
+ and r0, r3, r0, lsl #9
bl ftl_malloc
- ldrh fp, [r5, r8]
- mov fp, fp, asl #1
+ ldrh r10, [r5, r9]
str r0, [r4, #-480]
add r0, r0, #32
- str r0, [r4, #-3608]
- mov r0, fp
+ str r0, [r4, #-3604]
+ lsl r10, r10, #1
+ mov r0, r10
bl ftl_malloc
str r0, [r4, #-476]
- mov r0, fp
+ mov r0, r10
bl ftl_malloc
- ldr fp, [r5, #2416]
- mov fp, fp, asl #1
- str r0, [r4, #-3544]
- mov r0, fp
+ ldr r10, [r5, #2420]
+ str r0, [r4, #-3540]
+ lsl r10, r10, #1
+ mov r0, r10
bl ftl_malloc
str r0, [r4, #-472]
- mov r0, fp
+ mov r0, r10
bl ftl_malloc
- movw fp, #2408
str r0, [r4, #-468]
- ldrh r0, [r5, r8]
- mov r0, r0, lsr #3
+ movw r10, #2412
+ ldrh r0, [r5, r9]
+ lsr r0, r0, #3
add r0, r0, #4
bl ftl_malloc
- str r0, [r4, #-3368]
- ldrh r0, [r5, fp]
- mov r0, r0, asl #1
+ str r0, [r5, #32]
+ ldrh r0, [r5, r10]
+ lsl r0, r0, #1
bl ftl_malloc
- str r0, [r5, #2436]
- ldrh r0, [r5, fp]
- mov r0, r0, asl #1
+ str r0, [r5, #2440]
+ ldrh r0, [r5, r10]
+ lsl r0, r0, #1
bl ftl_malloc
str r0, [r4, #-464]
- ldrh r0, [r5, fp]
- movw fp, #2410
- mov r0, r0, asl #2
+ ldrh r0, [r5, r10]
+ movw r10, #2414
+ lsl r0, r0, #2
bl ftl_malloc
str r0, [r4, #-460]
- ldrh r0, [r5, fp]
- mov r0, r0, asl #2
+ ldrh r0, [r5, r10]
+ lsl r0, r0, #2
bl ftl_malloc
- ldrh r2, [r5, fp]
+ ldrh r2, [r5, r10]
mov r1, #0
- mov r2, r2, asl #2
str r0, [r4, #-456]
+ lsl r2, r2, #2
bl ftl_memset
- movw r3, #2424
- ldrh fp, [r5, r3]
- mov fp, fp, asl #2
- mov r0, fp
+ movw r3, #2428
+ ldrh r10, [r5, r3]
+ lsl r10, r10, #2
+ mov r0, r10
bl ftl_malloc
str r0, [r4, #-452]
- mov r0, fp
+ mov r0, r10
bl ftl_malloc
- movw fp, #2426
str r0, [r4, #-448]
- ldr r0, [r5, #2416]
- mov r0, r0, asl #2
+ movw r10, #2430
+ ldr r0, [r5, #2420]
+ lsl r0, r0, #2
bl ftl_malloc
str r0, [r4, #-444]
- ldrh r0, [r5, fp]
- mul r0, r9, r0
- bl ftl_malloc
- ldrh r3, [r5, fp]
- str r0, [r4, #-3380]
ldrh r0, [r5, r10]
+ mul r0, r8, r0
+ mov r8, r6
+ add r6, r6, #56
+ bl ftl_malloc
+ ldrh r3, [r5, r10]
+ str r0, [r4, #-3376]
+ ldrh r0, [r8], #84
mul r0, r0, r3
bl ftl_malloc
- ldrh r3, [r5, r8]
- movw r8, #2342
+ ldrh r3, [r5, r9]
+ movw r9, #2346
str r0, [r4, #-440]
mov r0, #6
mul r0, r0, r3
bl ftl_malloc
- movw r3, #2386
- ldrh r3, [r5, r3]
- add r3, r3, #31
- mov r3, r3, asr #5
- strh r3, [r7, #52]! @ movhi
- str r0, [r4, #-3552]
- ldrh r0, [r5, r8]
+ movw r3, #2388
+ str r0, [r4, #-3548]
+ ldrh r0, [r5, r3]
+ ldrh r3, [r5, r9]
+ add r0, r0, #31
+ asr r0, r0, #5
+ strh r0, [r7, #52]! @ movhi
mul r0, r0, r3
- mov r0, r0, asl #2
+ lsl r0, r0, #2
bl ftl_malloc
ldrh r2, [r7]
- ldrh ip, [r5, r8]
mov r3, #1
- mov r2, r2, asl #2
+ ldrh ip, [r5, r9]
+ str r0, [r5, #2484]
+ lsl r2, r2, #2
mov r1, r2
- str r0, [r5, #2480]
-.L1024:
+.L1025:
cmp r3, ip
- bcs .L1125
- ldr r0, [r5, #2480]
+ bcc .L1026
+ add r6, r6, r3, lsl #2
+ ldr r3, .L1126+20
+ mov r2, #0
+ add r6, r6, #24
+.L1027:
+ cmp r3, r6
+ bne .L1028
+ ldr r3, [r4, #-472]
+ cmp r3, #0
+ bne .L1029
+.L1031:
+ ldr r1, .L1126+24
+ ldr r0, .L1126+28
+ bl printk
+ mvn r0, #0
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1026:
+ ldr r0, [r5, #2484]
add r3, r3, #1
add r0, r0, r1
add r1, r1, r2
- str r0, [r6, #4]!
- b .L1024
-.L1125:
- ldr r2, .L1127+16
- mov r1, #0
-.L1026:
- cmp r3, #8
- addne r0, r2, r3, asl #2
- addne r3, r3, #1
- strne r1, [r0, #28]
- bne .L1026
-.L1126:
- ldr r2, [r4, #-472]
- ldr r3, .L1127
- cmp r2, #0
- bne .L1028
-.L1030:
- ldr r1, .L1127+20
- ldr r0, .L1127+24
- bl printk
- mvn r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ str r0, [r8, #4]!
+ b .L1025
.L1028:
- ldr r2, [r3, #-468]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-452]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-444]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-3380]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-440]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-3552]
- cmp r2, #0
- beq .L1030
- ldr r2, [r5, #2480]
- cmp r2, #0
- beq .L1030
- ldr r3, [r3, #-3544]
+ str r2, [r6, #4]!
+ b .L1027
+.L1029:
+ ldr r3, [r4, #-468]
cmp r3, #0
- beq .L1030
- ldr r2, [r4, #-2680]
- ldr r3, .L1127
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-2672]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-536]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-528]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-3612]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-2688]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-532]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-524]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-520]
- cmp r2, #0
- beq .L1030
- ldr r3, [r3, #-516]
+ beq .L1031
+ ldr r3, [r4, #-452]
cmp r3, #0
- beq .L1030
- ldr r2, [r4, #-2696]
- ldr r3, .L1127
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-508]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-504]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-2700]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-500]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-496]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-2692]
- cmp r2, #0
- beq .L1030
- ldr r2, [r3, #-3608]
- cmp r2, #0
- beq .L1030
- ldr r3, [r3, #-484]
+ beq .L1031
+ ldr r3, [r4, #-444]
cmp r3, #0
- beq .L1030
- ldr r3, .L1127+4
- ldr r3, [r3, #2436]
+ beq .L1031
+ ldr r3, [r4, #-3376]
cmp r3, #0
- beq .L1030
- ldr r3, .L1127
+ beq .L1031
+ ldr r3, [r4, #-440]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-3548]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r5, #2484]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-3540]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2680]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2672]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-536]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-528]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-3608]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2688]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-532]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-524]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-520]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-516]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2696]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-508]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-504]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2700]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-500]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-496]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-2692]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-3604]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, [r4, #-484]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, .L1126+4
+ ldr r3, [r3, #2440]
+ cmp r3, #0
+ beq .L1031
+ ldr r3, .L1126
ldr r2, [r3, #-464]
cmp r2, #0
- beq .L1030
+ beq .L1031
ldr r2, [r3, #-460]
cmp r2, #0
- beq .L1030
+ beq .L1031
ldr r3, [r3, #-456]
cmp r3, #0
- beq .L1030
+ beq .L1031
mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1128:
- .align 2
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
.L1127:
+ .align 2
+.L1126:
.word .LANCHOR2
.word .LANCHOR0
.word .LANCHOR0+2400
.word .LANCHOR2-488
- .word .LANCHOR0+2452
+ .word 33553920
+ .word .LANCHOR0+2512
.word .LANCHOR3
.word .LC81
.fnend
.size FtlMemInit, .-FtlMemInit
.align 2
.global FtlBbt2Bitmap
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbt2Bitmap, %function
FtlBbt2Bitmap:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L1135
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r3, .L1134
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- mov r4, r0
- ldrh r2, [r3]
- mov r0, r1
mov r5, r1
+ mov r4, r0
mov r1, #0
+ mov r0, r5
movw r6, #65535
- mov r2, r2, asl #2
+ ldrh r2, [r3]
+ lsl r2, r2, #2
bl ftl_memset
- add r3, r4, #1020
- ldr ip, .L1135+4
- add r3, r3, #2
- sub r1, r4, #2
+ ldr ip, .L1134+4
+ add r0, r4, #1020
+ sub r2, r4, #2
+ add r0, r0, #2
mov r4, #1
-.L1131:
- ldrh r2, [r1, #2]!
- cmp r2, r6
- ldmeqfd sp!, {r4, r5, r6, pc}
- mov lr, r2, lsr #5
- and r2, r2, #31
- cmp r1, r3
- ldr r0, [r5, lr, asl #2]
- orr r2, r0, r4, asl r2
- str r2, [r5, lr, asl #2]
- ldrh r2, [ip, #6]
- add r2, r2, #1
- strh r2, [ip, #6] @ movhi
- bne .L1131
- ldmfd sp!, {r4, r5, r6, pc}
-.L1136:
- .align 2
+.L1130:
+ ldrh r3, [r2, #2]!
+ cmp r3, r6
+ popeq {r4, r5, r6, pc}
+ lsr lr, r3, #5
+ and r3, r3, #31
+ cmp r2, r0
+ ldr r1, [r5, lr, lsl #2]
+ orr r3, r1, r4, lsl r3
+ str r3, [r5, lr, lsl #2]
+ ldrh r3, [ip, #6]
+ add r3, r3, #1
+ strh r3, [ip, #6] @ movhi
+ bne .L1130
+ pop {r4, r5, r6, pc}
.L1135:
+ .align 2
+.L1134:
.word .LANCHOR2-436
- .word .LANCHOR0+2452
+ .word .LANCHOR0+2456
.fnend
.size FtlBbt2Bitmap, .-FtlBbt2Bitmap
.align 2
.global FtlBbtMemInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbtMemInit, %function
FtlBbtMemInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r0, .L1138
- movw r3, #2452
+ ldr r2, .L1137
+ movw r3, #2456
mvn r1, #0
- add r2, r0, r3
- strh r1, [r0, r3] @ movhi
+ add r0, r2, r3
+ strh r1, [r2, r3] @ movhi
mov r3, #0
- add r0, r0, #2464
- strh r3, [r2, #6] @ movhi
- mov r1, #255
mov r2, #16
+ strh r3, [r0, #6] @ movhi
+ mov r1, #255
+ add r0, r0, #12
b ftl_memset
-.L1139:
- .align 2
.L1138:
+ .align 2
+.L1137:
.word .LANCHOR0
.fnend
.size FtlBbtMemInit, .-FtlBbtMemInit
.align 2
.global FtlFreeSysBlkQueueInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlFreeSysBlkQueueInit, %function
FtlFreeSysBlkQueueInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L1142
- mov r2, #2048
- stmfd sp!, {r4, lr}
+ ldr r1, .L1141
+ movw r2, #2516
+ push {r4, lr}
.save {r4, lr}
mov r4, #0
+ add r3, r1, r2
+ strh r0, [r1, r2] @ movhi
+ mov r2, #2048
mov r1, r4
+ add r0, r3, #8
strh r4, [r3, #2] @ movhi
strh r4, [r3, #4] @ movhi
strh r4, [r3, #6] @ movhi
- strh r0, [r3], #8 @ movhi
- mov r0, r3
bl ftl_memset
mov r0, r4
- ldmfd sp!, {r4, pc}
-.L1143:
- .align 2
+ pop {r4, pc}
.L1142:
- .word .LANCHOR0+2512
+ .align 2
+.L1141:
+ .word .LANCHOR0
.fnend
.size FtlFreeSysBlkQueueInit, .-FtlFreeSysBlkQueueInit
.align 2
.global ftl_free_no_use_map_blk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_free_no_use_map_blk, %function
ftl_free_no_use_map_blk:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r1, #0
ldrh r2, [r0, #10]
@@ -6884,165 +7300,148 @@
ldr r5, [r0, #20]
ldr r7, [r0, #12]
ldr r6, [r0, #24]
- mov r2, r2, asl #1
+ lsl r2, r2, #1
mov r0, r5
bl ftl_memset
mov r2, #0
-.L1145:
+.L1144:
ldrh r1, [r4, #6]
uxth r3, r2
cmp r1, r3
- bls .L1165
- ldr r0, [r6, r3, asl #2]
+ bhi .L1148
+ ldr r2, .L1164
+ movw r3, #2392
+ mov r6, #0
+ mov r8, r6
+ mov r10, r6
+ ldrh r2, [r2, r3]
+ ldrh r3, [r4]
+ lsl r3, r3, #1
+ strh r2, [r5, r3] @ movhi
+ ldrh r9, [r5]
+.L1149:
+ ldrh r3, [r4, #10]
+ uxth r1, r6
+ cmp r3, r1
+ bhi .L1153
+ mov r0, r8
+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1148:
+ uxth r3, r2
mov r1, #0
+ ldr r0, [r6, r3, lsl #2]
ubfx r0, r0, #10, #16
-.L1146:
+.L1145:
ldrh ip, [r4, #10]
uxth r3, r1
cmp ip, r3
- bls .L1166
- mov r3, r3, asl #1
+ addls r2, r2, #1
+ bls .L1144
+.L1147:
+ uxth r3, r1
add r1, r1, #1
+ lsl r3, r3, #1
ldrh ip, [r7, r3]
- rsb lr, ip, r0
- cmp ip, #0
- clz lr, lr
- mov lr, lr, lsr #5
- moveq lr, #0
+ adds lr, ip, #0
+ movne lr, #1
+ cmp r0, ip
+ movne lr, #0
cmp lr, #0
- ldrneh ip, [r5, r3]
+ ldrhne ip, [r5, r3]
addne ip, ip, #1
- strneh ip, [r5, r3] @ movhi
- b .L1146
-.L1166:
- add r2, r2, #1
+ strhne ip, [r5, r3] @ movhi
b .L1145
-.L1165:
- ldr r2, .L1168
- movw r3, #2390
- mov r8, #0
- mov r1, r8
- mov fp, r8
- ldrh r2, [r2, r3]
- ldrh r3, [r4]
- mov r3, r3, asl #1
- strh r2, [r5, r3] @ movhi
- ldrh r9, [r5]
-.L1150:
- ldrh r3, [r4, #10]
- uxth r6, r8
- cmp r3, r6
- bls .L1167
- mov r2, r6, asl #1
- ldrh r3, [r5, r2]
- cmp r9, r3
- bls .L1151
- ldrh r0, [r7, r2]
- add r10, r7, r2
+.L1153:
+ uxth r3, r6
+ lsl r3, r3, #1
+ ldrh r2, [r5, r3]
+ cmp r9, r2
+ bls .L1150
+ ldrh r0, [r7, r3]
+ add fp, r7, r3
cmp r0, #0
- bne .L1152
- b .L1153
-.L1151:
- cmp r3, #0
- bne .L1153
- ldrh r0, [r7, r2]
- add r10, r7, r2
- cmp r0, #0
- movne r6, r1
- beq .L1153
- b .L1155
+ bne .L1151
.L1152:
- cmp r3, #0
- movne r1, r6
- movne r9, r3
- bne .L1153
- mov r9, r3
-.L1155:
+ add r6, r6, #1
+ b .L1149
+.L1150:
+ cmp r2, #0
+ bne .L1152
+ ldrh r0, [r7, r3]
+ add fp, r7, r3
+ cmp r0, #0
+ beq .L1152
+.L1154:
mov r1, #1
bl FtlFreeSysBlkQueueIn
- strh fp, [r10] @ movhi
+ strh r10, [fp] @ movhi
ldrh r3, [r4, #8]
- mov r1, r6
sub r3, r3, #1
strh r3, [r4, #8] @ movhi
-.L1153:
- add r8, r8, #1
- b .L1150
-.L1167:
- mov r0, r1
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1169:
+ b .L1152
+.L1151:
+ subs r9, r2, #0
+ mov r8, r1
+ beq .L1154
+ b .L1152
+.L1165:
.align 2
-.L1168:
+.L1164:
.word .LANCHOR0
.fnend
.size ftl_free_no_use_map_blk, .-ftl_free_no_use_map_blk
.align 2
.global FtlL2PDataInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlL2PDataInit, %function
FtlL2PDataInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
- .save {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r1, #0
- ldr r5, .L1175
- mvn r6, #0
- ldr r4, .L1175+4
- ldr r2, [r5, #2416]
- ldr r0, [r4, #-468]
- mov r2, r2, asl #1
+ ldr r4, .L1170
+ mvn r7, #0
+ ldr r5, .L1170+4
+ ldr r2, [r4, #2420]
+ add r6, r4, #2400
+ ldr r0, [r5, #-468]
+ lsl r2, r2, #1
bl ftl_memset
- movw r3, #2398
- movw r2, #2426
- ldrh r3, [r5, r3]
- ldrh r2, [r5, r2]
+ movw r2, #2430
+ ldrh r3, [r6]
+ ldrh r2, [r4, r2]
mov r1, #255
- ldr r0, [r4, #-440]
+ ldr r0, [r5, #-440]
mul r2, r2, r3
bl ftl_memset
- ldr ip, .L1175+8
- mov r1, #0
- mov r3, r4
- sub r7, ip, #28
- mov r4, #12
- mov r5, r1
-.L1171:
- ldrh r2, [ip]
- add lr, r1, #1
- uxth r1, r1
- ldr r0, .L1175
- cmp r2, r1
- bls .L1174
- mul r0, r4, r1
- ldr r2, [r3, #-3380]
- add r8, r2, r0
- str r5, [r8, #4]
- strh r6, [r2, r0] @ movhi
- ldr r2, [r3, #-3380]
- add r0, r2, r0
- ldrh r2, [r7]
- mul r2, r1, r2
- ldr r1, [r3, #-440]
- bic r2, r2, #3
- add r2, r1, r2
- mov r1, lr
- str r2, [r0, #8]
- b .L1171
-.L1174:
- ldr r2, .L1175+12
+ mov r2, #0
+ mov r3, r5
+ mov r1, r6
+ add ip, r6, #30
+ mov r5, #12
+ mov r6, r2
+.L1167:
+ ldrh r8, [ip]
+ uxth r0, r2
+ add lr, r2, #1
+ cmp r8, r0
+ bhi .L1168
+ ldr r2, .L1170+8
mvn r1, #0
strh r1, [r2, #2] @ movhi
strh r1, [r2] @ movhi
- ldr r1, [r0, #2416]
+ ldr r1, [r4, #2420]
strh r1, [r2, #10] @ movhi
- ldr r1, .L1175+16
+ ldr r1, .L1170+12
strh r1, [r2, #4] @ movhi
ldrh r1, [r2, #44]
strh r1, [r2, #8] @ movhi
- movw r1, #2424
- ldrh r1, [r0, r1]
+ movw r1, #2428
+ ldrh r1, [r4, r1]
strh r1, [r2, #6] @ movhi
ldr r2, [r3, #-472]
str r2, [r3, #-420]
@@ -7052,236 +7451,249 @@
str r2, [r3, #-412]
ldr r2, [r3, #-452]
str r2, [r3, #-408]
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L1176:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1168:
+ uxth r2, r2
+ ldr r8, [r3, #-3376]
+ mul r0, r5, r2
+ add r9, r8, r0
+ str r6, [r9, #4]
+ strh r7, [r8, r0] @ movhi
+ ldr r8, [r3, #-3376]
+ add r0, r8, r0
+ ldrh r8, [r1]
+ mul r2, r2, r8
+ ldr r8, [r3, #-440]
+ bic r2, r2, #3
+ add r2, r8, r2
+ str r2, [r0, #8]
+ mov r2, lr
+ b .L1167
+.L1171:
.align 2
-.L1175:
+.L1170:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2426
.word .LANCHOR2-432
.word -3902
.fnend
.size FtlL2PDataInit, .-FtlL2PDataInit
.align 2
.global FtlVariablesInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlVariablesInit, %function
FtlVariablesInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mvn r3, #0
- ldr r5, .L1179
+ ldr r5, .L1174
mov r4, #0
- ldr r6, .L1179+4
mov r1, r4
+ movw r7, #2334
+ ldr r6, .L1174+4
sub r2, r5, #380
- movw r7, #2330
str r3, [r5, #-368]
strh r3, [r2] @ movhi
- movw r3, #2434
+ movw r3, #2438
strh r4, [r6, r3] @ movhi
- movw r3, #2408
+ movw r3, #2412
ldrh r2, [r6, r3]
- ldr r0, [r6, #2436]
+ ldr r0, [r6, #2440]
str r4, [r5, #-384]
- mov r2, r2, asl #1
str r4, [r5, #-376]
+ lsl r2, r2, #1
str r4, [r5, #-372]
- str r4, [r6, #2244]
+ str r4, [r6, #2248]
bl ftl_memset
ldrh r2, [r6, r7]
mov r1, r4
- ldr r0, [r5, #-3608]
- mov r2, r2, asl #1
+ ldr r0, [r5, #-3604]
+ lsl r2, r2, #1
bl ftl_memset
ldrh r2, [r6, r7]
mov r1, r4
ldr r0, [r5, #-484]
- mov r2, r2, asl #1
+ lsl r2, r2, #1
bl ftl_memset
+ sub r0, r5, #3584
mov r1, r4
- sub r0, r5, #3600
mov r2, #48
+ sub r0, r0, #12
bl ftl_memset
- mov r1, r4
- mov r2, #512
sub r0, r5, #3232
+ mov r2, #512
+ mov r1, r4
+ sub r0, r0, #4
bl ftl_memset
bl FtlGcBufInit
bl FtlL2PDataInit
mov r0, r4
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L1180:
+ pop {r4, r5, r6, r7, r8, pc}
+.L1175:
.align 2
-.L1179:
+.L1174:
.word .LANCHOR2
.word .LANCHOR0
.fnend
.size FtlVariablesInit, .-FtlVariablesInit
.align 2
.global SupperBlkListInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type SupperBlkListInit, %function
SupperBlkListInit:
.fnstart
- @ args = 0, pretend = 0, frame = 24
+ @ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2330
- ldr r10, .L1193
+ movw r3, #2334
+ ldr r6, .L1187
+ mov r4, #0
mov r2, #6
- ldr r6, .L1193+4
+ .pad #20
+ sub sp, sp, #20
+ ldr r5, .L1187+4
mov r1, #0
- .pad #28
- sub sp, sp, #28
- mov r7, #0
- ldrh r3, [r10, r3]
- mov r4, r7
- ldr r0, [r6, #-3552]
- mov r8, r7
- mov r9, r7
- mov r5, r6
+ ldrh r3, [r6, r3]
+ mov r9, r4
+ mov r10, r4
+ ldr r0, [r5, #-3548]
+ sub r7, r5, #3520
mul r2, r2, r3
bl ftl_memset
- sub r3, r6, #3520
- sub r1, r6, #3536
- mov fp, r6
- strh r7, [r3, #-8] @ movhi
- sub r3, r6, #568
- str r7, [r6, #-3532]
- str r7, [r6, #-3548]
- str r7, [r6, #-3540]
- strh r7, [r1] @ movhi
- strh r7, [r3] @ movhi
- str r10, [sp, #8]
- str r1, [sp, #12]
-.L1182:
- ldr r3, .L1193+8
- uxth r7, r4
- sxth r10, r7
- ldrh r2, [r3]
- cmp r10, r2
- bge .L1189
- sub r3, r3, #8
- ldr r2, .L1193+12
- mov ip, r7
+ sub r3, r5, #568
+ str r4, [r5, #-3528]
+ str r4, [r5, #-3544]
+ str r4, [r5, #-3536]
+ strh r4, [r7, #-12] @ movhi
+ strh r4, [r7, #-4] @ movhi
+ strh r4, [r3] @ movhi
+ str r6, [sp]
+.L1177:
+ ldr r3, .L1187+8
+ sxth r8, r4
ldrh r3, [r3]
- str r3, [sp]
- ldrh r3, [r2]
- mov r2, #0
- mov r6, r2
- str r3, [sp, #4]
-.L1190:
+ cmp r8, r3
+ bge .L1184
+ ldr r3, .L1187+12
+ uxth r1, r4
+ mov fp, #0
+ mov r6, fp
+ str r1, [sp, #4]
+ ldrh r2, [r3]
+ add r3, r3, #66
+ ldrh r3, [r3]
+ b .L1185
+.L1179:
+ str r3, [sp, #12]
+ add fp, fp, #1
ldr r3, [sp]
- sxth r1, r2
- cmp r1, r3
- bge .L1192
- ldr r3, [sp, #8]
- str r2, [sp, #20]
- add r1, r3, r1
- str ip, [sp, #16]
- ldrb r0, [r1, #2348] @ zero_extendqisi2
- mov r1, ip
+ str r2, [sp, #8]
+ add r0, r3, r1
+ ldr r1, [sp, #4]
+ ldrb r0, [r0, #2350] @ zero_extendqisi2
bl V2P_block
bl FtlBbmIsBadBlock
+ ldr r3, [sp, #12]
cmp r0, #0
- ldr r2, [sp, #20]
- ldr ip, [sp, #16]
- ldreq r3, [sp, #4]
- add r2, r2, #1
+ ldr r2, [sp, #8]
addeq r6, r3, r6
- uxtheq r6, r6
- b .L1190
-.L1192:
+ sxtheq r6, r6
+.L1185:
+ sxth r1, fp
+ cmp r1, r2
+ blt .L1179
cmp r6, #0
- beq .L1185
- sxth r1, r6
+ lsl fp, r8, #1
+ ldreq r3, [r5, #-3540]
+ mvneq r2, #0
+ strheq r2, [r3, fp] @ movhi
+ beq .L1181
+ mov r1, r6
mov r0, #32768
bl __aeabi_idiv
- uxth r6, r0
- b .L1186
-.L1185:
- sxth r7, r7
- ldr r2, [r5, #-3544]
- mvn r1, #0
- mov r7, r7, asl #1
- strh r1, [r2, r7] @ movhi
-.L1186:
- mov r1, r10, asl #1
- ldr r2, [r5, #-3552]
- add r0, r1, r10
- add r2, r2, r0, asl #1
- strh r6, [r2, #4] @ movhi
- ldr r2, .L1193+16
- ldrh r0, [r2]
- cmp r10, r0
- beq .L1187
- ldrh r0, [r2, #48]
- cmp r10, r0
- beq .L1187
- ldrh r2, [r2, #96]
- cmp r10, r2
- beq .L1187
- ldr r3, [fp, #-3544]
+ sxth r6, r0
+.L1181:
+ ldr r2, [r5, #-3548]
+ add r3, fp, r8
+ add r3, r2, r3, lsl #1
+ strh r6, [r3, #4] @ movhi
+ ldrh r3, [r7]
+ cmp r8, r3
+ beq .L1182
+ ldr r3, .L1187+16
+ ldrh r3, [r3]
+ cmp r8, r3
+ beq .L1182
+ ldr r3, .L1187+20
+ ldrh r3, [r3]
+ cmp r8, r3
+ beq .L1182
+ ldr r3, [r5, #-3540]
uxth r0, r4
- ldrh r3, [r3, r1]
+ ldrh r3, [r3, fp]
cmp r3, #0
- bne .L1188
- add r8, r8, #1
- uxth r8, r8
- bl INSERT_FREE_LIST
- b .L1187
-.L1188:
+ bne .L1183
add r9, r9, #1
uxth r9, r9
- bl INSERT_DATA_LIST
-.L1187:
+ bl INSERT_FREE_LIST
+.L1182:
add r4, r4, #1
+ b .L1177
+.L1183:
+ add r10, r10, #1
+ uxth r10, r10
+ bl INSERT_DATA_LIST
b .L1182
-.L1189:
- ldr r3, [sp, #12]
+.L1184:
mov r0, #0
- strh r9, [r3] @ movhi
- ldr r3, .L1193+20
- strh r8, [r3, #-8] @ movhi
- add sp, sp, #28
+ strh r10, [r7, #-12] @ movhi
+ strh r9, [r7, #-4] @ movhi
+ add sp, sp, #20
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1194:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1188:
.align 2
-.L1193:
+.L1187:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2328
- .word .LANCHOR0+2388
- .word .LANCHOR2-3524
- .word .LANCHOR2-3520
+ .word .LANCHOR0+2332
+ .word .LANCHOR0+2324
+ .word .LANCHOR2-3472
+ .word .LANCHOR2-3424
.fnend
.size SupperBlkListInit, .-SupperBlkListInit
.align 2
.global FtlGcPageVarInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcPageVarInit, %function
FtlGcPageVarInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r3, #0
- ldr r4, .L1197
- movw r5, #2392
- ldr r6, .L1197+4
+ ldr r4, .L1191
+ movw r5, #2394
mov r1, #255
+ ldr r6, .L1191+4
sub r2, r4, #2672
ldr r0, [r4, #-2680]
strh r3, [r2, #-4] @ movhi
sub r2, r4, #2656
strh r3, [r2, #-12] @ movhi
ldrh r2, [r6, r5]
- mov r2, r2, asl #1
+ lsl r2, r2, #1
bl ftl_memset
ldrh r3, [r6, r5]
mov r2, #12
@@ -7289,17 +7701,20 @@
mov r1, #255
mul r2, r2, r3
bl ftl_memset
- ldmfd sp!, {r4, r5, r6, lr}
+ pop {r4, r5, r6, lr}
b FtlGcBufInit
-.L1198:
+.L1192:
.align 2
-.L1197:
+.L1191:
.word .LANCHOR2
.word .LANCHOR0
.fnend
.size FtlGcPageVarInit, .-FtlGcPageVarInit
.align 2
.global ftl_memcpy
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_memcpy, %function
ftl_memcpy:
.fnstart
@@ -7311,158 +7726,155 @@
.size ftl_memcpy, .-ftl_memcpy
.align 2
.global FlashReadIdbData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadIdbData, %function
FlashReadIdbData:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
mov r2, #2048
- ldr r1, .L1202
+ ldr r1, .L1196
bl ftl_memcpy
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L1203:
+ pop {r4, pc}
+.L1197:
.align 2
-.L1202:
+.L1196:
.word .LANCHOR2-364
.fnend
.size FlashReadIdbData, .-FlashReadIdbData
.align 2
.global FlashLoadPhyInfoInRam
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashLoadPhyInfoInRam, %function
FlashLoadPhyInfoInRam:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r4, #0
- ldr r8, .L1217
-.L1208:
- mov r7, r4, asl #5
- ldr r1, .L1217+4
- add r0, r7, #1
- ldrb r2, [r8, r4, asl #5] @ zero_extendqisi2
- add r0, r8, r0
- ldr r6, .L1217+8
+ ldr r5, .L1207
+ ldr r9, .L1207+4
+ add r6, r5, #504
+.L1201:
+ lsl r8, r4, #5
+ ldrb r2, [r6, r4, lsl #5] @ zero_extendqisi2
+ mov r1, r9
+ add r0, r8, #1
+ add r0, r6, r0
bl FlashMemCmp8
- add r9, r6, #508
- subs r5, r0, #0
- bne .L1205
- adds r9, r9, r7
- beq .L1211
- add r4, r6, r7
- mov r3, r5
- ldr r1, .L1217+12
- ldrb r2, [r4, #530] @ zero_extendqisi2
- b .L1210
-.L1205:
- add r4, r4, #1
- cmp r4, #86
- bne .L1208
- b .L1211
-.L1216:
+ subs r7, r0, #0
+ bne .L1199
+ add r5, r5, r8
+ ldr r2, .L1207+8
+ ldrb r0, [r5, #526] @ zero_extendqisi2
+ add r6, r6, r8
+ mov r3, r7
+ mov r1, r2
+.L1200:
+ ldrb ip, [r2, r3, lsl #5] @ zero_extendqisi2
+ cmp ip, r0
+ beq .L1203
add r3, r3, #1
cmp r3, #4
- beq .L1209
-.L1210:
- ldrb r0, [r1, r3, asl #5] @ zero_extendqisi2
- cmp r0, r2
- bne .L1216
-.L1209:
- ldr r4, .L1217+16
+ bne .L1200
+.L1203:
+ ldr r4, .L1207+12
+ add r1, r1, r3, lsl #5
mov r2, #32
- ldr r1, .L1217+12
- ldr r0, .L1217+20
- add r1, r1, r3, asl #5
+ ldr r0, .L1207+16
bl ftl_memcpy
- mov r0, r4
- mov r1, r9
mov r2, #32
+ mov r1, r6
+ mov r0, r4
bl ftl_memcpy
ldrh r0, [r4, #10]
bl FlashBlockAlignInit
- b .L1206
-.L1211:
- mvn r5, #0
-.L1206:
- mov r0, r5
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L1218:
+ b .L1198
+.L1199:
+ add r4, r4, #1
+ cmp r4, #86
+ bne .L1201
+ mvn r7, #0
+.L1198:
+ mov r0, r7
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1208:
.align 2
-.L1217:
- .word .LANCHOR1+508
- .word .LANCHOR0+2068
+.L1207:
.word .LANCHOR1
- .word .LANCHOR1+3260
- .word .LANCHOR1+472
- .word .LANCHOR0+48
+ .word .LANCHOR0+2072
+ .word .LANCHOR1+3256
+ .word .LANCHOR1+468
+ .word .LANCHOR0+52
.fnend
.size FlashLoadPhyInfoInRam, .-FlashLoadPhyInfoInRam
.align 2
.global NandcCopy1KB
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcCopy1KB, %function
NandcCopy1KB:
.fnstart
@ args = 4, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
cmp r1, #1
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r4, r2
add r2, r0, #4096
- ldr r5, [sp, #16]
add r6, r0, #512
- add r2, r2, r4, asl #9
- bne .L1220
+ add r0, r2, r4, lsl #9
+ ldr r5, [sp, #16]
+ bne .L1210
cmp r3, #0
- beq .L1221
- mov r0, r2
+ beq .L1211
+ mov r2, #1024
mov r1, r3
- mov r2, #1024
bl ftl_memcpy
-.L1221:
+.L1211:
cmp r5, #0
- ldmeqfd sp!, {r4, r5, r6, pc}
- ldrb r3, [r5, #2] @ zero_extendqisi2
- mov r4, r4, lsr #1
- ldrb r2, [r5, #1] @ zero_extendqisi2
- add r4, r4, r4, asl #1
- mov r3, r3, asl #16
- orr r2, r3, r2, asl #8
- ldrb r3, [r5] @ zero_extendqisi2
- orr r3, r2, r3
- ldrb r2, [r5, #3] @ zero_extendqisi2
- orr r3, r3, r2, asl #24
- str r3, [r6, r4, asl #4]
- ldmfd sp!, {r4, r5, r6, pc}
-.L1220:
+ lsrne r4, r4, #1
+ ldrne r3, [r5] @ unaligned
+ addne r4, r4, r4, lsl #1
+ strne r3, [r6, r4, lsl #4]
+ pop {r4, r5, r6, pc}
+.L1210:
cmp r3, #0
- beq .L1224
- mov r1, r2
- mov r0, r3
+ beq .L1214
+ mov r1, r0
mov r2, #1024
+ mov r0, r3
bl ftl_memcpy
-.L1224:
+.L1214:
cmp r5, #0
- ldmeqfd sp!, {r4, r5, r6, pc}
- mov r4, r4, lsr #1
- add r4, r4, r4, asl #1
- ldr r3, [r6, r4, asl #4]
- mov r2, r3, lsr #8
+ popeq {r4, r5, r6, pc}
+ lsr r4, r4, #1
+ add r4, r4, r4, lsl #1
+ ldr r3, [r6, r4, lsl #4]
strb r3, [r5]
+ lsr r2, r3, #8
strb r2, [r5, #1]
- mov r2, r3, lsr #16
- mov r3, r3, lsr #24
+ lsr r2, r3, #16
+ lsr r3, r3, #24
strb r2, [r5, #2]
strb r3, [r5, #3]
- ldmfd sp!, {r4, r5, r6, pc}
+ pop {r4, r5, r6, pc}
.fnend
.size NandcCopy1KB, .-NandcCopy1KB
.align 2
.global ftl_memcpy32
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_memcpy32, %function
ftl_memcpy32:
.fnstart
@@ -7470,18 +7882,22 @@
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
mov r3, #0
-.L1237:
+.L1227:
cmp r3, r2
- ldrne ip, [r1, r3, asl #2]
- strne ip, [r0, r3, asl #2]
- addne r3, r3, #1
- bne .L1237
-.L1239:
+ bne .L1228
bx lr
+.L1228:
+ ldr ip, [r1, r3, lsl #2]
+ str ip, [r0, r3, lsl #2]
+ add r3, r3, #1
+ b .L1227
.fnend
.size ftl_memcpy32, .-ftl_memcpy32
.align 2
.global ftl_memcmp
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_memcmp, %function
ftl_memcmp:
.fnstart
@@ -7493,52 +7909,60 @@
.size ftl_memcmp, .-ftl_memcmp
.align 2
.global timer_get_time
+ .syntax unified
+ .arm
+ .fpu softvfp
.type timer_get_time, %function
timer_get_time:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L1242
+ ldr r3, .L1231
ldr r0, [r3]
b jiffies_to_msecs
-.L1243:
+.L1232:
.align 2
-.L1242:
+.L1231:
.word jiffies
.fnend
.size timer_get_time, .-timer_get_time
.align 2
.global FlashSramLoadStore
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashSramLoadStore, %function
FlashSramLoadStore:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr ip, .L1248
+ ldr ip, .L1238
cmp r2, #0
moveq r2, r3
ldr ip, [ip, #1684]
add ip, ip, #4096
- add r1, ip, r1
- beq .L1247
- str lr, [sp, #-4]!
+ add ip, ip, r1
+ moveq r1, ip
+ strne lr, [sp, #-4]!
.save {lr}
- mov lr, r0
- mov r0, r1
- mov r1, lr
- ldr lr, [sp], #4
- mov r2, r3
-.L1247:
+ movne r1, r0
+ ldrne lr, [sp], #4
+ movne r2, r3
+ movne r0, ip
+.L1237:
b ftl_memcpy
-.L1249:
+.L1239:
.align 2
-.L1248:
+.L1238:
.word .LANCHOR2
.fnend
.size FlashSramLoadStore, .-FlashSramLoadStore
.align 2
.global FlashCs123Init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashCs123Init, %function
FlashCs123Init:
.fnstart
@@ -7549,7 +7973,51 @@
.fnend
.size FlashCs123Init, .-FlashCs123Init
.align 2
+ .global ftl_dma32_malloc
+ .syntax unified
+ .arm
+ .fpu softvfp
+ .type ftl_dma32_malloc, %function
+ftl_dma32_malloc:
+ .fnstart
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ cmp r0, #8192
+ ble .L1242
+ b ftl_malloc
+.L1242:
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ add r4, r0, #63
+ ldr r5, .L1246
+ bic r4, r4, #63
+ ldr r3, [r5, #1688]
+ cmp r4, r3
+ ble .L1243
+ mov r0, #16384
+ bl ftl_malloc
+ mov r3, #16384
+ str r0, [r5, #1692]
+ str r3, [r5, #1688]
+.L1243:
+ ldr r3, [r5, #1688]
+ ldr r0, [r5, #1692]
+ sub r3, r3, r4
+ add r4, r0, r4
+ str r3, [r5, #1688]
+ str r4, [r5, #1692]
+ pop {r4, r5, r6, pc}
+.L1247:
+ .align 2
+.L1246:
+ .word .LANCHOR2
+ .fnend
+ .size ftl_dma32_malloc, .-ftl_dma32_malloc
+ .align 2
.global rk_nand_suspend
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_nand_suspend, %function
rk_nand_suspend:
.fnstart
@@ -7561,6 +8029,9 @@
.size rk_nand_suspend, .-rk_nand_suspend
.align 2
.global rk_nand_resume
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_nand_resume, %function
rk_nand_resume:
.fnstart
@@ -7572,23 +8043,29 @@
.size rk_nand_resume, .-rk_nand_resume
.align 2
.global rk_ftl_get_capacity
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_get_capacity, %function
rk_ftl_get_capacity:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L1254
- ldr r0, [r3, #2428]
+ ldr r3, .L1251
+ ldr r0, [r3, #2432]
bx lr
-.L1255:
+.L1252:
.align 2
-.L1254:
+.L1251:
.word .LANCHOR0
.fnend
.size rk_ftl_get_capacity, .-rk_ftl_get_capacity
.align 2
.global rk_nandc_get_irq_status
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_nandc_get_irq_status, %function
rk_nandc_get_irq_status:
.fnstart
@@ -7601,6 +8078,9 @@
.size rk_nandc_get_irq_status, .-rk_nandc_get_irq_status
.align 2
.global rknand_proc_ftlread
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rknand_proc_ftlread, %function
rknand_proc_ftlread:
.fnstart
@@ -7612,6 +8092,9 @@
.size rknand_proc_ftlread, .-rknand_proc_ftlread
.align 2
.global ReadFlashInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ReadFlashInfo, %function
ReadFlashInfo:
.fnstart
@@ -7623,266 +8106,275 @@
.size ReadFlashInfo, .-ReadFlashInfo
.align 2
.global rknand_print_hex
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rknand_print_hex, %function
rknand_print_hex:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r5, #0
- mov r9, r0
+ ldr r7, .L1266
+ mov r10, r0
mov r6, r1
- mov r7, r2
- mov r8, r3
+ mov r8, r2
+ ldr fp, .L1266+4
+ mov r9, r3
mov r4, r5
-.L1260:
- cmp r4, r8
- beq .L1269
+.L1257:
+ cmp r4, r9
+ bne .L1263
+ ldr r1, .L1266+4
+ ldr r0, .L1266+8
+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ b printk
+.L1263:
cmp r5, #0
- bne .L1261
- ldr r0, .L1270
- mov r1, r9
- mov r2, r6
+ bne .L1258
mov r3, r4
+ mov r2, r6
+ mov r1, r10
+ ldr r0, .L1266+12
bl printk
-.L1261:
- cmp r7, #4
- ldreq r0, .L1270+4
- ldreq r1, [r6, r4, asl #2]
- beq .L1268
- cmp r7, #2
- moveq r3, r4, asl #1
- ldreq r0, .L1270+4
- ldreqsh r1, [r6, r3]
- ldrne r0, .L1270+4
- ldrneb r1, [r6, r4] @ zero_extendqisi2
-.L1268:
+.L1258:
+ cmp r8, #4
+ ldreq r1, [r6, r4, lsl #2]
+ beq .L1265
+ cmp r8, #2
+ lsleq r3, r4, #1
+ ldrbne r1, [r6, r4] @ zero_extendqisi2
+ ldrsheq r1, [r6, r3]
+.L1265:
+ mov r0, r7
add r5, r5, #1
bl printk
cmp r5, #15
- bls .L1265
- ldr r0, .L1270+8
+ bls .L1262
mov r5, #0
- ldr r1, .L1270+12
+ mov r1, fp
+ ldr r0, .L1266+8
bl printk
-.L1265:
+.L1262:
add r4, r4, #1
- b .L1260
-.L1269:
- ldr r0, .L1270+8
- ldr r1, .L1270+12
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- b printk
-.L1271:
+ b .L1257
+.L1267:
.align 2
-.L1270:
- .word .LC82
+.L1266:
.word .LC83
- .word .LC76
.word .LC84
+ .word .LC77
+ .word .LC82
.fnend
.size rknand_print_hex, .-rknand_print_hex
.align 2
.global HynixGetReadRetryDefault
+ .syntax unified
+ .arm
+ .fpu softvfp
.type HynixGetReadRetryDefault, %function
HynixGetReadRetryDefault:
.fnstart
- @ args = 0, pretend = 0, frame = 40
+ @ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- cmp r0, #2
- ldr r7, .L1381
mvn r3, #83
+ ldr r7, .L1384
+ cmp r0, #2
mvn r1, #82
mvn r2, #81
- .pad #44
- sub sp, sp, #44
+ .pad #60
+ sub sp, sp, #60
mov r4, r0
- strb r3, [r7, #1214]
- mvn r3, #80
- strb r0, [r7, #1210]
- strb r1, [r7, #1215]
- strb r2, [r7, #1216]
- strb r3, [r7, #1217]
- bne .L1273
- mvn r3, #88
- strb r3, [r7, #1214]
- ldr r3, .L1381+4
- mvn r2, #8
- mov r5, #7
- strb r2, [r3, #3405]
- b .L1334
-.L1273:
- cmp r0, #3
- bne .L1275
- mvn r3, #79
- strb r3, [r7, #1214]
- mvn r3, #78
- strb r3, [r7, #1215]
- mvn r3, #77
- strb r3, [r7, #1216]
- mvn r3, #76
- strb r3, [r7, #1217]
- mvn r3, #75
- strb r3, [r7, #1218]
- mvn r3, #74
- strb r3, [r7, #1219]
- mvn r3, #73
strb r3, [r7, #1220]
- mvn r3, #72
- b .L1375
-.L1275:
- cmp r0, #4
- bne .L1276
- mvn r0, #51
- strb r1, [r7, #1219]
- strb r0, [r7, #1214]
- mvn r0, #64
- strb r2, [r7, #1220]
- strb r0, [r7, #1215]
- mvn r0, #85
+ mvn r3, #80
strb r0, [r7, #1216]
- mvn r0, #84
- strb r0, [r7, #1217]
- mvn r0, #50
- strb r0, [r7, #1218]
-.L1375:
- mov r5, #8
+ strb r1, [r7, #1221]
+ strb r2, [r7, #1222]
+ strb r3, [r7, #1223]
+ bne .L1269
+ mvn r3, #88
+ mov r5, #7
+ strb r3, [r7, #1220]
+ mvn r2, #8
+ ldr r3, .L1384+4
+ strb r2, [r3, #3401]
+.L1334:
+ mov r6, #4
+ b .L1270
+.L1269:
+ cmp r0, #3
+ bne .L1271
+ mvn r3, #79
+ strb r3, [r7, #1220]
+ mvn r3, #78
strb r3, [r7, #1221]
+ mvn r3, #77
+ strb r3, [r7, #1222]
+ mvn r3, #76
+ strb r3, [r7, #1223]
+ mvn r3, #75
+ strb r3, [r7, #1224]
+ mvn r3, #74
+ strb r3, [r7, #1225]
+ mvn r3, #73
+ strb r3, [r7, #1226]
+ mvn r3, #72
+.L1379:
+ mov r5, #8
+ strb r3, [r7, #1227]
mov r6, r5
- b .L1274
-.L1276:
+.L1270:
+ sub r3, r4, #1
+ cmp r3, #1
+ bhi .L1276
+ ldr fp, .L1384+8
+ mov r10, #0
+ ldr r2, .L1384+12
+.L1277:
+ ldrb r1, [r7, #2234] @ zero_extendqisi2
+ uxtb r3, r10
+ cmp r1, r3
+ bhi .L1283
+.L1284:
+ ldr r3, .L1384
+ strb r6, [r3, #1217]
+ strb r5, [r3, #1218]
+ add sp, sp, #60
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1271:
+ cmp r0, #4
+ bne .L1272
+ mvn r0, #51
+ strb r1, [r7, #1225]
+ strb r0, [r7, #1220]
+ mvn r0, #64
+ strb r0, [r7, #1221]
+ mvn r0, #85
+ strb r0, [r7, #1222]
+ mvn r0, #84
+ strb r0, [r7, #1223]
+ mvn r0, #50
+ strb r0, [r7, #1224]
+ strb r2, [r7, #1226]
+ b .L1379
+.L1272:
cmp r0, #5
- bne .L1277
+ bne .L1273
mov r3, #56
mov r5, #8
- strb r3, [r7, #1214]
+ strb r3, [r7, #1220]
mov r3, #57
- strb r3, [r7, #1215]
+ strb r3, [r7, #1221]
mov r3, #58
- strb r3, [r7, #1216]
+ strb r3, [r7, #1222]
mov r3, #59
- strb r3, [r7, #1217]
+ strb r3, [r7, #1223]
b .L1334
-.L1277:
+.L1273:
cmp r0, #6
- bne .L1278
+ bne .L1274
mov r3, #14
mov r5, #12
- strb r3, [r7, #1214]
+ strb r3, [r7, #1220]
mov r3, #15
- strb r3, [r7, #1215]
+ strb r3, [r7, #1221]
mov r3, #16
- strb r3, [r7, #1216]
+ strb r3, [r7, #1222]
mov r3, #17
- strb r3, [r7, #1217]
+ strb r3, [r7, #1223]
b .L1334
-.L1278:
+.L1274:
cmp r0, #7
- bne .L1279
+ bne .L1275
mvn r3, #79
mov r5, #12
- strb r3, [r7, #1214]
- mov r6, #10
- mvn r3, #78
- strb r3, [r7, #1215]
- mvn r3, #77
- strb r3, [r7, #1216]
- mvn r3, #76
- strb r3, [r7, #1217]
- mvn r3, #75
- strb r3, [r7, #1218]
- mvn r3, #74
- strb r3, [r7, #1219]
- mvn r3, #73
strb r3, [r7, #1220]
- mvn r3, #72
+ mvn r3, #78
strb r3, [r7, #1221]
- mvn r3, #43
+ mvn r3, #77
strb r3, [r7, #1222]
- mvn r3, #42
+ mvn r3, #76
strb r3, [r7, #1223]
- b .L1274
-.L1279:
+ mvn r3, #75
+ strb r3, [r7, #1224]
+ mvn r3, #74
+ strb r3, [r7, #1225]
+ mvn r3, #73
+ strb r3, [r7, #1226]
+ mvn r3, #72
+ strb r3, [r7, #1227]
+ mvn r3, #43
+ strb r3, [r7, #1228]
+ mvn r3, #42
+ strb r3, [r7, #1229]
+ mov r6, #10
+ b .L1270
+.L1275:
cmp r0, #8
mov r5, #7
bne .L1334
mov r3, #6
- strb r5, [r7, #1215]
- strb r3, [r7, #1214]
- mov r5, #50
+ strb r5, [r7, #1221]
+ strb r3, [r7, #1220]
mov r3, #9
- strb r0, [r7, #1216]
- strb r3, [r7, #1217]
- mov r6, #5
+ strb r3, [r7, #1223]
mov r3, #10
- strb r3, [r7, #1218]
- b .L1274
-.L1334:
- mov r6, #4
-.L1274:
- sub r3, r4, #1
- cmp r3, #1
- bhi .L1371
- ldr r10, .L1381+8
- mov r9, #0
-.L1280:
- ldrb r1, [r7, #2230] @ zero_extendqisi2
- uxtb r2, r9
- ldr r3, .L1381
- cmp r1, r2
- bls .L1287
- add r2, r3, r2
- ldr r4, .L1381+12
- ldr r1, .L1381+16
- mov ip, #55
- ldrb r2, [r2, #2232] @ zero_extendqisi2
- add r3, r3, r2, asl #3
- add r4, r4, r2, asl #6
- add r4, r4, #20
- ldrb r8, [r3, #16] @ zero_extendqisi2
- ldr r0, [r3, #12]
- mov fp, r4
- mov r2, r4
- add r8, r0, r8, asl #8
-.L1282:
- str ip, [r8, #2056]
- mov r0, #80
- ldrb r3, [r1, #1]! @ zero_extendqisi2
- str r2, [sp, #12]
- str ip, [sp, #8]
- str r3, [r8, #2052]
- str r1, [sp, #4]
- str r1, [sp, #16]
- bl NandcDelayns
- ldr r3, [r8, #2048]
- ldr r2, [sp, #12]
- ldmib sp, {r1, ip}
- strb r3, [r2], #1
- rsb r3, r4, r2
- uxtb r3, r3
- cmp r3, r6
- bcc .L1282
- mov r2, #0
+ strb r0, [r7, #1222]
+ mov r5, #50
+ strb r3, [r7, #1224]
+ mov r6, #5
+ b .L1270
.L1283:
- add r0, r10, r2
+ add r3, r7, r3
+ mov r8, #0
+ ldrb r3, [r3, #2236] @ zero_extendqisi2
+ mov r1, #55
+ ldr r9, [r7, r3, lsl #3]
+ add r4, fp, r3, lsl #6
+ add r3, r7, r3, lsl #3
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ add r4, r4, #20
+ add r9, r9, r3, lsl #8
+.L1278:
+ add r3, fp, r8
+ str r1, [r9, #2056]
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ mov r0, #80
+ str r2, [sp, #4]
+ str r1, [sp]
+ str r3, [r9, #2052]
+ bl ndelay
+ ldr r3, [r9, #2048]
+ ldm sp, {r1, r2}
+ strb r3, [r4, r8]
+ add r8, r8, #1
+ uxtb r3, r8
+ cmp r6, r3
+ bhi .L1278
+ mov r0, r4
+ mov r1, #0
+.L1281:
mov r3, #1
-.L1284:
- ldrb r1, [r0, r3, asl #2] @ zero_extendqisi2
- ldrb ip, [fp] @ zero_extendqisi2
- add r1, r1, ip
- strb r1, [fp, r3, asl #3]
+ add lr, r2, r1
+.L1280:
+ ldrb ip, [lr, r3, lsl #2] @ zero_extendqisi2
+ ldrb r8, [r0] @ zero_extendqisi2
+ add ip, ip, r8
+ strb ip, [r0, r3, lsl #3]
add r3, r3, #1
cmp r3, #7
- bne .L1284
- add r2, r2, #1
- add fp, fp, #1
- cmp r2, #4
- bne .L1283
+ bne .L1280
+ add r1, r1, #1
+ add r0, r0, #1
+ cmp r1, #4
+ bne .L1281
mov r3, #0
- add r9, r9, #1
+ add r10, r10, #1
strb r3, [r4, #16]
strb r3, [r4, #24]
strb r3, [r4, #32]
@@ -7890,102 +8382,71 @@
strb r3, [r4, #48]
strb r3, [r4, #41]
strb r3, [r4, #49]
- b .L1280
-.L1371:
+ b .L1277
+.L1276:
sub r3, r4, #3
cmp r3, #5
- bhi .L1287
- smulbb r2, r6, r5
- mov r3, r2, asl #4
- mov r2, r2, asr #1
- str r3, [sp, #36]
- mov r3, r2, asl #1
- str r3, [sp, #8]
+ bhi .L1284
+ smulbb r3, r6, r5
+ ldr r8, .L1384
+ asr r2, r3, #1
+ lsl r3, r3, #4
+ str r3, [sp, #48]
+ lsl r3, r2, #2
+ str r2, [sp, #4]
+ str r3, [sp, #40]
+ lsl r3, r2, #1
+ str r3, [sp, #28]
mov r3, #0
-.L1379:
- str r3, [sp, #16]
- ldrb r3, [sp, #16] @ zero_extendqisi2
- str r3, [sp, #12]
- ldr r3, .L1381
- ldr r2, [sp, #12]
- ldrb r3, [r3, #2230] @ zero_extendqisi2
+ str r3, [sp, #24]
+ add r3, r8, #1216
+ add r3, r3, #28
+ str r3, [sp, #52]
+.L1285:
+ ldrb r3, [sp, #24] @ zero_extendqisi2
+ str r3, [sp, #8]
+ ldr r2, [sp, #8]
+ ldrb r3, [r8, #2234] @ zero_extendqisi2
cmp r3, r2
- bhi .L1332
-.L1287:
- ldr r3, .L1381
- strb r6, [r3, #1211]
- strb r5, [r3, #1212]
- add sp, sp, #44
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1332:
- ldr r2, [sp, #12]
- ldr r3, .L1381
- add r3, r3, r2
- ldrb r10, [r3, #2232] @ zero_extendqisi2
- ldr r3, .L1381
- add r3, r3, r10, asl #3
- mov r0, r10
- ldrb fp, [r3, #16] @ zero_extendqisi2
- ldr r8, [r3, #12]
+ bls .L1284
+ ldr r3, [sp, #8]
+ add r3, r8, r3
+ ldrb r9, [r3, #2236] @ zero_extendqisi2
+ ldr fp, [r8, r9, lsl #3]
+ mov r0, r9
+ add r3, r8, r9, lsl #3
+ ldrb r10, [r3, #4] @ zero_extendqisi2
mov r3, #255
- mov r9, fp, asl #8
- add r7, r8, r9
+ add r7, fp, r10, lsl #8
str r3, [r7, #2056]
bl NandcWaitFlashReady
cmp r4, #7
- ldreq r3, .L1381+12
- moveq r7, #160
- mlaeq r7, r7, r10, r3
- addeq r3, r7, #28
- beq .L1376
-.L1289:
- cmp r4, #8
- beq .L1291
- ldr r3, .L1381+12
- add r7, r3, r10, asl #6
- add r3, r7, #20
-.L1376:
+ bne .L1286
+ ldr r3, .L1384+8
+ mov r0, #160
+ mla r0, r0, r9, r3
+ add r3, r0, #28
+.L1380:
str r3, [sp, #20]
cmp r4, #4
- add r3, r8, fp, asl #8
+ add r3, fp, r10, lsl #8
mov r2, #54
str r2, [r3, #2056]
- bne .L1292
- add r9, r8, r9
- mov r3, #255
- str r3, [r9, #2052]
- mov r3, #64
- str r3, [r9, #2048]
- mov r3, #204
- b .L1377
-.L1292:
- sub r2, r4, #5
- cmp r2, #1
- bhi .L1294
- ldr r2, .L1381
- ldrb r2, [r2, #1214] @ zero_extendqisi2
+ bne .L1289
+ mov r2, #255
str r2, [r3, #2052]
- mov r2, #82
+ mov r2, #64
str r2, [r3, #2048]
- b .L1293
-.L1294:
- cmp r4, #7
- bne .L1293
- add r9, r8, r9
- mov r3, #174
- str r3, [r9, #2052]
- mov r3, #0
- str r3, [r9, #2048]
- mov r3, #176
-.L1377:
- str r3, [r9, #2052]
- mov r3, #77
- str r3, [r9, #2048]
-.L1293:
- add r3, r8, fp, asl #8
- cmp r4, #6
+ mov r2, #204
+.L1381:
+ str r2, [r3, #2052]
+ mov r2, #77
+.L1382:
+ str r2, [r3, #2048]
+.L1290:
+ add r3, fp, r10, lsl #8
mov r2, #22
+ cmp r4, #6
str r2, [r3, #2056]
mov r2, #23
str r2, [r3, #2056]
@@ -8004,174 +8465,153 @@
mov r2, #0
str r2, [r3, #2052]
.L1333:
- add r3, r8, fp, asl #8
+ add r3, fp, r10, lsl #8
mov r2, #48
- mov r0, r10
+ mov r0, r9
str r2, [r3, #2056]
bl NandcWaitFlashReady
sub r3, r4, #5
- cmp r3, #1
- movhi r3, #0
- movls r3, #1
- str r3, [sp, #24]
- sub r3, r4, #8
- clz r3, r3
- mov r3, r3, lsr #5
- str r3, [sp, #4]
- ldr r2, [sp, #4]
- ldr r3, [sp, #24]
- orrs r3, r3, r2
- movne ip, #16
- bne .L1297
+ cmp r4, #8
+ cmpne r3, #1
+ str r3, [sp, #44]
+ movls r2, #16
+ bls .L1294
cmp r4, #7
- movne ip, #2
- moveq ip, #32
-.L1297:
- ldr r3, .L1381+20
- add r0, r8, fp, asl #8
- ldr r3, [r3, #1688]
- mov r1, r3
-.L1298:
- ldr r2, [r0, #2048]
- strb r2, [r1], #1
- rsb r2, r3, r1
- uxtb r2, r2
- cmp r2, ip
- bcc .L1298
- ldr r2, [sp, #4]
- cmp r2, #0
- beq .L1299
+ moveq r2, #32
+ movne r2, #2
+.L1294:
+ ldr r3, .L1384+16
+ sub r2, r2, #1
+ add ip, fp, r10, lsl #8
+ ldr r3, [r3, #1696]
+ str ip, [sp]
+ sub r1, r3, #1
+ uxtab r2, r3, r2
+ mov r0, r1
+.L1295:
+ ldr ip, [sp]
+ ldr ip, [ip, #2048]
+ strb ip, [r0, #1]!
+ cmp r2, r0
+ bne .L1295
+ cmp r4, #8
+ bne .L1296
mov r2, #0
-.L1301:
- ldrb ip, [r3, r2, asl #2] @ zero_extendqisi2
+.L1298:
+ ldrb r0, [r3, r2, lsl #2] @ zero_extendqisi2
uxtb r1, r2
- cmp ip, #50
- beq .L1300
- add ip, r3, r2, asl #2
- ldrb ip, [ip, #1] @ zero_extendqisi2
- cmp ip, #5
- beq .L1300
+ cmp r0, #50
+ beq .L1297
+ add r0, r3, r2, lsl #2
+ ldrb r0, [r0, #1] @ zero_extendqisi2
+ cmp r0, #5
+ beq .L1297
add r2, r2, #1
cmp r2, #8
- bne .L1301
- b .L1302
-.L1300:
- cmp r1, #6
- bls .L1303
-.L1302:
- ldr r0, .L1381+24
- mov r1, #0
- bl printk
-.L1304:
- b .L1304
+ bne .L1298
.L1299:
+ mov r1, #0
+ ldr r0, .L1384+20
+ bl printk
+.L1301:
+ b .L1301
+.L1286:
+ cmp r4, #8
+ beq .L1288
+ ldr r3, .L1384+8
+ add r0, r3, r9, lsl #6
+ add r3, r0, #20
+ b .L1380
+.L1289:
+ sub r2, r4, #5
+ cmp r2, #1
+ ldrbls r2, [r8, #1220] @ zero_extendqisi2
+ strls r2, [r3, #2052]
+ movls r2, #82
+ bls .L1382
cmp r4, #7
- bne .L1305
- ldr r2, [sp, #4]
-.L1307:
- ldrb ip, [r3, r2, asl #2] @ zero_extendqisi2
- uxtb r1, r2
- cmp ip, #12
- beq .L1306
- add ip, r3, r2, asl #2
- ldrb ip, [ip, #1] @ zero_extendqisi2
- cmp ip, #10
- beq .L1306
- add r2, r2, #1
- cmp r2, #8
- bne .L1307
- b .L1308
-.L1306:
- cmp r1, #7
- bne .L1303
-.L1308:
- ldr r0, .L1381+24
- mov r1, #0
- bl printk
-.L1309:
- b .L1309
-.L1305:
- cmp r4, #6
- bne .L1303
- sub r2, r3, #1
- add r3, r3, #7
-.L1310:
- ldrb r1, [r2, #1]! @ zero_extendqisi2
- cmp r1, #12
- beq .L1303
- ldrb r1, [r2, #8] @ zero_extendqisi2
- cmp r1, #4
- beq .L1303
- cmp r2, r3
- bne .L1310
- ldr r0, .L1381+24
- mov r1, #0
- bl printk
-.L1312:
- b .L1312
-.L1303:
- ldr r1, .L1381+20
- ldr ip, [sp, #36]
- ldr r2, [r1, #1688]
- add ip, r2, ip
+ bne .L1290
+ mov r2, #174
+ str r2, [r3, #2052]
+ mov r2, #0
+ str r2, [r3, #2048]
+ mov r2, #176
+ b .L1381
+.L1297:
+ cmp r1, #6
+ bhi .L1299
+.L1300:
+ ldr r1, .L1384+16
+ ldr r2, [r1, #1696]
mov r3, r2
+.L1310:
+ ldr ip, [sp, #48]
+ sub r0, r3, r2
+ cmp r0, ip
+ blt .L1311
+ ldr r3, [sp, #28]
+ ldr r1, [r1, #1696]
+ add r0, r1, r3
+ mov r3, #8
.L1313:
- cmp r3, ip
- ldrne lr, [r0, #2048]
- strneb lr, [r3], #1
+ mov lr, r0
+ mov ip, #0
+.L1312:
+ ldrh r7, [lr]
+ add ip, ip, #1
+ mvn r7, r7
+ strh r7, [lr], #2 @ movhi
+ ldr r7, [sp, #4]
+ cmp r7, ip
+ bgt .L1312
+ ldr ip, [sp, #40]
+ subs r3, r3, #1
+ add r0, r0, ip
bne .L1313
-.L1380:
- ldr r3, [r1, #1688]
- mov r0, #8
- ldr r1, [sp, #8]
- add r1, r3, r1
- str r1, [sp, #28]
-.L1316:
- ldr ip, [sp, #8]
- add lr, r1, ip
-.L1315:
- ldrh ip, [r1]
- mvn ip, ip
- strh ip, [r1], #2 @ movhi
- cmp r1, lr
- bne .L1315
- ldr ip, [sp, #8]
- subs r0, r0, #1
- add r1, r1, ip
- bne .L1316
-.L1317:
+ str r1, [sp, #12]
+ str r3, [sp, #16]
+.L1319:
mov ip, #0
mov r0, ip
-.L1320:
- mov r1, #1
- mov lr, #0
- mov r1, r1, asl r0
- mov r7, #16
- str r7, [sp, #32]
- mov r7, lr
.L1318:
- ldrh r9, [r3, lr]
- and r9, r9, r1
- cmp r9, r1
+ mov lr, #1
+ mov r7, #16
+ lsl lr, lr, r0
+ str r7, [sp, #36]
+ mov r7, #0
+ str lr, [sp, #32]
+ ldr lr, [sp, #12]
+.L1316:
+ ldrh r3, [lr]
+ mov r1, r3
+ ldr r3, [sp, #32]
+ bics r3, r3, r1
+ ldr r3, [sp, #28]
addeq r7, r7, #1
- ldr r9, [sp, #8]
- add lr, lr, r9
- ldr r9, [sp, #32]
- subs r9, r9, #1
- str r9, [sp, #32]
- bne .L1318
+ add lr, lr, r3
+ ldr r3, [sp, #36]
+ subs r3, r3, #1
+ str r3, [sp, #36]
+ bne .L1316
cmp r7, #8
add r0, r0, #1
- orrhi ip, ip, r1
+ ldrhi r3, [sp, #32]
+ orrhi ip, ip, r3
uxthhi ip, ip
cmp r0, #16
- bne .L1320
- ldr r1, [sp, #28]
+ bne .L1318
+ ldr r3, [sp, #12]
strh ip, [r3], #2 @ movhi
+ str r3, [sp, #12]
+ ldr r3, [sp, #16]
+ add r3, r3, #1
+ str r3, [sp, #16]
+ ldr r1, [sp, #16]
+ ldr r3, [sp, #4]
cmp r3, r1
- bne .L1317
- ldr r3, .L1381+20
- ldr r1, [r3, #1688]
+ bgt .L1319
+ ldr r3, .L1384+16
+ ldr r1, [r3, #1696]
mov r3, #0
sub r0, r1, #4
add ip, r1, #28
@@ -8179,91 +8619,141 @@
ldr lr, [r0, #4]!
cmp lr, #0
addeq r3, r3, #1
- cmp r0, ip
+ cmp ip, r0
bne .L1322
cmp r3, #7
ble .L1323
- ldr r0, .L1381+28
- mov r2, #1
+ ldr r0, .L1384+24
mov r3, #1024
+ mov r2, #1
bl rknand_print_hex
- ldr r0, .L1381+24
mov r1, #0
+ ldr r0, .L1384+20
bl printk
.L1324:
b .L1324
+.L1296:
+ cmp r4, #7
+ bne .L1302
+ mov r2, #0
+.L1304:
+ ldrb r0, [r3, r2, lsl #2] @ zero_extendqisi2
+ uxtb r1, r2
+ cmp r0, #12
+ beq .L1303
+ add r0, r3, r2, lsl #2
+ ldrb r0, [r0, #1] @ zero_extendqisi2
+ cmp r0, #10
+ beq .L1303
+ add r2, r2, #1
+ cmp r2, #8
+ bne .L1304
+.L1305:
+ mov r1, #0
+ ldr r0, .L1384+20
+ bl printk
+.L1306:
+ b .L1306
+.L1303:
+ cmp r1, #6
+ bls .L1300
+ b .L1305
+.L1302:
+ cmp r4, #6
+ bne .L1300
+ add r3, r3, #7
+.L1307:
+ ldrb r2, [r1, #1]! @ zero_extendqisi2
+ cmp r2, #12
+ beq .L1300
+ ldrb r2, [r1, #8] @ zero_extendqisi2
+ cmp r2, #4
+ beq .L1300
+ cmp r3, r1
+ bne .L1307
+ mov r1, #0
+ ldr r0, .L1384+20
+ bl printk
+.L1309:
+ b .L1309
+.L1311:
+ ldr r0, [sp]
+ ldr r0, [r0, #2048]
+ strb r0, [r3], #1
+ b .L1310
.L1323:
cmp r4, #6
- moveq r0, #4
+ moveq ip, #4
beq .L1325
cmp r4, #7
- moveq r0, #10
+ moveq ip, #10
beq .L1325
- ldr r3, [sp, #4]
- cmp r3, #0
- moveq r0, #8
- movne r0, #5
+ cmp r4, #8
+ moveq ip, #5
+ movne ip, #8
.L1325:
- sub r9, r6, #1
- ldr r1, [sp, #20]
- mov ip, #0
- uxtb r9, r9
- add r9, r9, #1
+ sub r3, r6, #1
+ ldr r0, [sp, #20]
+ uxtb r3, r3
+ mov lr, #0
+ add r3, r3, #1
+ str r3, [sp, #12]
.L1326:
- mov r7, r1
- mov r3, r2
+ mov r3, r0
+ mov r1, r2
.L1327:
- ldrb lr, [r3], #1 @ zero_extendqisi2
- strb lr, [r7], #1
- rsb lr, r2, r3
- uxtb lr, lr
- cmp lr, r6
- bcc .L1327
- add ip, ip, #1
- add r2, r2, r9
- cmp ip, r5
- add r1, r1, r0
- blt .L1326
- add r7, r8, fp, asl #8
+ ldrb r7, [r1], #1 @ zero_extendqisi2
+ strb r7, [r3], #1
+ sub r7, r1, r2
+ uxtb r7, r7
+ cmp r6, r7
+ bhi .L1327
+ ldr r3, [sp, #12]
+ add lr, lr, #1
+ cmp r5, lr
+ add r0, r0, ip
+ add r2, r2, r3
+ bgt .L1326
+ add r10, fp, r10, lsl #8
mov r3, #255
- mov r0, r10
- str r3, [r7, #2056]
+ mov r0, r9
+ str r3, [r10, #2056]
+ bl NandcWaitFlashReady
+ ldr r3, [sp, #44]
+ cmp r3, #1
+ bhi .L1329
+ mov r3, #54
+ ldr r2, [sp]
+ str r3, [r10, #2056]
+ mvn r1, #0
+ ldrb r3, [r8, #1220] @ zero_extendqisi2
+ ldr r0, [sp, #8]
+ str r3, [r2, #2052]
+ mov r3, #0
+ str r3, [r2, #2048]
+ mov r3, #22
+ str r3, [r10, #2056]
+ bl FlashReadCmd
+.L1330:
+ mov r0, r9
bl NandcWaitFlashReady
ldr r3, [sp, #24]
- cmp r3, #0
- beq .L1329
- mov r3, #54
- str r3, [r7, #2056]
- ldr r3, .L1381
- mvn r1, #0
- ldr r0, [sp, #12]
- ldrb r3, [r3, #1214] @ zero_extendqisi2
- str r3, [r7, #2052]
- mov r3, #0
- str r3, [r7, #2048]
- mov r3, #22
- str r3, [r7, #2056]
- bl FlashReadCmd
- b .L1330
-.L1329:
- ldr r3, [sp, #4]
- cmp r3, #0
- movne r3, #190
- moveq r3, #56
- str r3, [r7, #2056]
-.L1330:
- mov r0, r10
- bl NandcWaitFlashReady
- ldr r3, [sp, #16]
add r3, r3, #1
- b .L1379
-.L1291:
+ str r3, [sp, #24]
+ b .L1285
+.L1329:
+ cmp r4, #8
+ moveq r3, #190
+ movne r3, #56
+ str r3, [r10, #2056]
+ b .L1330
+.L1288:
mov r3, #120
mov r2, #23
str r3, [r7, #2056]
- mov r1, #25
mov r3, #0
str r3, [r7, #2052]
+ mov r1, #25
str r3, [r7, #2052]
str r3, [r7, #2052]
str r2, [r7, #2056]
@@ -8279,25 +8769,26 @@
str r1, [r7, #2052]
str r2, [r7, #2052]
str r3, [r7, #2052]
- ldr r3, .L1381+32
+ ldr r3, [sp, #52]
str r3, [sp, #20]
b .L1333
-.L1382:
+.L1385:
.align 2
-.L1381:
+.L1384:
.word .LANCHOR0
.word .LANCHOR1
- .word .LANCHOR1+3388
- .word .LANCHOR0+1210
- .word .LANCHOR0+1213
+ .word .LANCHOR0+1216
+ .word .LANCHOR1+3384
.word .LANCHOR2
.word .LC85
.word .LC86
- .word .LANCHOR0+1238
.fnend
.size HynixGetReadRetryDefault, .-HynixGetReadRetryDefault
.align 2
.global FlashGetReadRetryDefault
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashGetReadRetryDefault, %function
FlashGetReadRetryDefault:
.fnstart
@@ -8308,226 +8799,227 @@
bxeq lr
sub r2, r3, #1
cmp r2, #7
- bhi .L1385
+ bhi .L1388
b HynixGetReadRetryDefault
-.L1385:
+.L1388:
cmp r3, #49
- bne .L1386
- ldr r2, .L1397
- ldr r0, .L1397+4
- ldr r1, .L1397+8
- strb r3, [r2, #1210]
+ bne .L1389
+ ldr r2, .L1400
+ ldr r1, .L1400+4
+ strb r3, [r2, #1216]
mov r3, #4
- strb r3, [r2, #1211]
+ strb r3, [r2, #1217]
mov r3, #15
- strb r3, [r2, #1212]
+ strb r3, [r2, #1218]
mov r2, #64
- b .L1395
-.L1386:
+.L1398:
+ ldr r0, .L1400+8
+ b ftl_memcpy
+.L1389:
sub r2, r3, #65
cmp r3, #33
cmpne r2, #1
- ldrls r2, .L1397
- strlsb r3, [r2, #1210]
- movls r3, #4
- bls .L1396
-.L1387:
- cmp r3, #34
- cmpne r3, #67
- bne .L1388
- ldr r2, .L1397
- strb r3, [r2, #1210]
- mov r3, #5
-.L1396:
- strb r3, [r2, #1211]
+ bhi .L1390
+ ldr r2, .L1400
+ strb r3, [r2, #1216]
+ mov r3, #4
+.L1399:
+ strb r3, [r2, #1217]
mov r3, #7
- ldr r0, .L1397+4
- strb r3, [r2, #1212]
+ strb r3, [r2, #1218]
mov r2, #45
- ldr r1, .L1397+12
- b .L1395
-.L1388:
- cmp r3, #35
- cmpne r3, #68
+ ldr r1, .L1400+12
+ b .L1398
+.L1390:
+ cmp r3, #67
+ cmpne r3, #34
+ ldreq r2, .L1400
+ strbeq r3, [r2, #1216]
+ moveq r3, #5
+ beq .L1399
+.L1391:
+ cmp r3, #68
+ cmpne r3, #35
bxne lr
- ldr r2, .L1397
- ldr r0, .L1397+4
- ldr r1, .L1397+16
- strb r3, [r2, #1210]
+ ldr r2, .L1400
+ ldr r1, .L1400+16
+ strb r3, [r2, #1216]
mov r3, #5
- strb r3, [r2, #1211]
+ strb r3, [r2, #1217]
mov r3, #17
- strb r3, [r2, #1212]
+ strb r3, [r2, #1218]
mov r2, #95
-.L1395:
- b ftl_memcpy
-.L1398:
+ b .L1398
+.L1401:
.align 2
-.L1397:
+.L1400:
.word .LANCHOR0
- .word .LANCHOR0+1214
- .word .LANCHOR1+408
+ .word .LANCHOR1+404
+ .word .LANCHOR0+1220
.word .LANCHOR1+256
- .word .LANCHOR1+304
+ .word .LANCHOR1+301
.fnend
.size FlashGetReadRetryDefault, .-FlashGetReadRetryDefault
.align 2
.global NandcXferComp
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcXferComp, %function
NandcXferComp:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, lr}
- .save {r4, r5, r6, lr}
+ push {r0, r1, r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
.pad #8
- ldr r5, .L1439
- add r0, r5, r0, asl #3
- ldr r3, [r5, #2260]
- ldr r4, [r0, #12]
+ ldr r5, .L1442
+ ldr r3, [r5, #2264]
+ ldr r4, [r5, r0, lsl #3]
cmp r3, #3
- bls .L1430
+ bls .L1433
ldr r3, [r4, #16]
tst r3, #4
- beq .L1430
+ beq .L1433
ldr r6, [r4, #16]
ldr r3, [r4, #8]
ubfx r6, r6, #1, #1
cmp r6, #0
str r3, [sp]
- movne r6, #0
- beq .L1412
-.L1402:
+ beq .L1404
+ ldr r7, .L1442+4
+ mov r6, #0
+ ldr r8, .L1442+8
+.L1405:
ldr r2, [r4, #28]
ldr r3, [sp]
ubfx r2, r2, #16, #5
ubfx r3, r3, #22, #6
cmp r2, r3
- bge .L1410
- ldr r3, [r5, #2260]
+ bge .L1413
+ ldr r3, [r5, #2264]
cmp r3, #5
- bhi .L1403
-.L1406:
+ bhi .L1406
+.L1409:
add r6, r6, #1
- bic r3, r6, #-16777216
- cmp r3, #0
- bne .L1405
+ bics r3, r6, #-16777216
+ bne .L1408
ldr r2, [r4, #28]
mov r1, r6
ldr r3, [sp]
+ mov r0, r7
ubfx r2, r2, #16, #5
- ldr r0, .L1439+4
ubfx r3, r3, #22, #6
bl printk
- ldr r0, .L1439+8
- mov r1, r4
- mov r2, #4
mov r3, #512
+ mov r2, #4
+ mov r1, r4
+ mov r0, r8
bl rknand_print_hex
+.L1408:
+ mov r1, #5
+ mov r0, #1
+ bl usleep_range
b .L1405
-.L1403:
+.L1406:
ldr r3, [r4]
str r3, [sp, #4]
ldr r3, [sp, #4]
tst r3, #8192
- beq .L1406
+ beq .L1409
ldr r3, [sp, #4]
tst r3, #131072
- beq .L1406
-.L1410:
- ldr r3, [r5, #2296]
- ldr r4, .L1439
+ beq .L1409
+.L1413:
+ ldr r3, [r5, #2300]
cmp r3, #0
- beq .L1411
+ beq .L1414
ldr r1, [sp]
mov r2, #0
- ldr r0, [r4, #2288]
+ ldr r0, [r5, #2292]
ubfx r1, r1, #22, #5
- mov r1, r1, asl #10
+ lsl r1, r1, #10
bl rknand_dma_unmap_single
- ldr r0, [r4, #2292]
- mov r2, #0
ldr r1, [sp]
+ mov r2, #0
+ ldr r0, [r5, #2296]
ubfx r1, r1, #22, #5
- mov r1, r1, asl #7
+ lsl r1, r1, #7
bl rknand_dma_unmap_single
- b .L1411
-.L1405:
- mov r0, #1
- mov r1, #5
- bl usleep_range
- b .L1402
.L1414:
+ mov r3, #0
+ str r3, [r5, #2300]
+.L1402:
+ add sp, sp, #8
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, pc}
+.L1404:
+ ldr r7, .L1442+12
+ ldr r8, .L1442+8
+.L1415:
+ ldr r3, [sp]
+ tst r3, #1048576
+ beq .L1417
+ ldr r3, [r5, #2308]
+ cmp r3, #0
+ beq .L1418
+ mov r0, r4
+ bl NandcSendDumpDataStart
+.L1418:
+ ldr r3, [r5, #2300]
+ cmp r3, #0
+ beq .L1419
+ ldr r1, [sp]
+ mov r2, #1
+ ldr r0, [r5, #2292]
+ ubfx r1, r1, #22, #5
+ lsl r1, r1, #10
+ bl rknand_dma_unmap_single
+ ldr r1, [sp]
+ mov r2, #1
+ ldr r0, [r5, #2296]
+ ubfx r1, r1, #22, #5
+ lsl r1, r1, #7
+ bl rknand_dma_unmap_single
+.L1419:
+ ldr r3, [r5, #2308]
+ cmp r3, #0
+ beq .L1414
+ mov r0, r4
+ bl NandcSendDumpDataDone
+ b .L1414
+.L1417:
ldr r3, [r4, #8]
add r6, r6, #1
str r3, [sp]
- bic r3, r6, #-16777216
- cmp r3, #0
- bne .L1413
+ bics r3, r6, #-16777216
+ bne .L1416
ldr r2, [sp]
mov r1, r6
ldr r3, [r4, #28]
- ldr r0, .L1439+12
+ mov r0, r7
ubfx r3, r3, #16, #5
bl printk
- ldr r0, .L1439+8
- mov r1, r4
- mov r2, #4
mov r3, #512
+ mov r2, #4
+ mov r1, r4
+ mov r0, r8
bl rknand_print_hex
-.L1413:
- mov r0, #1
- mov r1, #5
- bl usleep_range
-.L1412:
- ldr r3, [sp]
- tst r3, #1048576
- beq .L1414
- ldr r3, [r5, #2304]
- cmp r3, #0
- beq .L1415
- mov r0, r4
- bl NandcSendDumpDataStart
-.L1415:
- ldr r3, [r5, #2296]
- ldr r6, .L1439
- cmp r3, #0
- beq .L1416
- ldr r1, [sp]
- mov r2, #1
- ldr r0, [r6, #2288]
- ubfx r1, r1, #22, #5
- mov r1, r1, asl #10
- bl rknand_dma_unmap_single
- ldr r0, [r6, #2292]
- mov r2, #1
- ldr r1, [sp]
- ubfx r1, r1, #22, #5
- mov r1, r1, asl #7
- bl rknand_dma_unmap_single
.L1416:
- ldr r3, [r5, #2304]
- cmp r3, #0
- beq .L1411
- mov r0, r4
- bl NandcSendDumpDataDone
-.L1411:
- mov r3, #0
- str r3, [r5, #2296]
- b .L1399
-.L1430:
+ mov r1, #5
+ mov r0, #1
+ bl usleep_range
+ b .L1415
+.L1433:
ldr r3, [r4, #8]
str r3, [sp]
ldr r3, [sp]
tst r3, #1048576
- beq .L1430
-.L1399:
- add sp, sp, #8
- @ sp needed
- ldmfd sp!, {r4, r5, r6, pc}
-.L1440:
+ beq .L1433
+ b .L1402
+.L1443:
.align 2
-.L1439:
+.L1442:
.word .LANCHOR0
.word .LC87
.word .LC88
@@ -8536,306 +9028,306 @@
.size NandcXferComp, .-NandcXferComp
.align 2
.global NandcXferData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type NandcXferData, %function
NandcXferData:
.fnstart
@ args = 4, pretend = 0, frame = 80
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r10, r3
- ldr r6, .L1489
- tst r10, #63
+ tst r3, #63
+ ldr r9, .L1484
.pad #92
sub sp, sp, #92
- mov r9, r0
- add r3, r6, r0, asl #3
+ mov r7, r0
mov r5, r1
- mov r7, r2
- ldr r8, [r3, #12]
- bne .L1442
- ldr r3, [sp, #128]
- cmp r3, #0
- bne .L1443
- add r0, sp, #24
- mov r1, #255
- mov r2, #64
- bl ftl_memset
- add r3, sp, #24
- str r3, [sp, #128]
-.L1443:
- ldr r3, [sp, #128]
- mov r0, r9
- mov r1, r5
- mov r2, r7
- str r10, [sp]
- str r3, [sp, #4]
- mov r3, #0
- bl NandcXferStart
- mov r0, r9
- mov r1, r5
- bl NandcXferComp
- cmp r5, #0
- movne fp, #0
- bne .L1444
- ldr r3, [r6, #2308]
- mov r0, r7, lsr #1
- mov r2, r5
- mov r1, r5
- cmp r3, #25
- ldr r3, [sp, #128]
- movcc lr, #64
- movcs lr, #128
-.L1446:
- cmp r1, r0
- add r3, r3, #4
- add ip, r2, lr
- bcs .L1487
- ldr r4, [r6, #2276]
- mov r2, r2, lsr #2
- add r1, r1, #1
- ldr r2, [r4, r2, asl #2]
- mov r4, r2, lsr #8
- strb r2, [r3, #-4]
- strb r4, [r3, #-3]
- mov r4, r2, lsr #16
- mov r2, r2, lsr #24
- strb r4, [r3, #-2]
- strb r2, [r3, #-1]
- mov r2, ip
- b .L1446
-.L1487:
- ldr r0, [r6, #2308]
- mov r2, #0
- ldr r1, [r6, #2260]
- mov r7, r7, lsr #2
- mov fp, r2
-.L1448:
- cmp r2, r7
- bcs .L1444
- cmp r0, #0
- beq .L1444
- add r3, r2, #8
- ldr r3, [r8, r3, asl #2]
- str r3, [sp, #20]
- ldr r3, [sp, #20]
- tst r3, #4
- bne .L1472
- ldr r4, [sp, #20]
- ubfx r4, r4, #15, #1
+ str r2, [sp, #8]
+ mov r8, r3
+ ldr r4, [sp, #128]
+ ldr r6, [r9, r0, lsl #3]
+ bne .L1445
cmp r4, #0
- bne .L1472
- cmp r1, #5
- bls .L1450
- ldr ip, [sp, #20]
- ldr r4, [sp, #20]
- ldr r3, [sp, #20]
- ubfx ip, ip, #3, #5
- ldr lr, [sp, #20]
- ubfx r4, r4, #27, #1
- ubfx r3, r3, #16, #5
- ubfx lr, lr, #29, #1
- orr ip, ip, r4, asl #5
- orr r3, r3, lr, asl #5
- cmp ip, r3
- ldr r3, [sp, #20]
- ldrhi r4, [sp, #20]
- ubfxhi r3, r3, #3, #5
- ldrls r4, [sp, #20]
- ubfxls r3, r3, #16, #5
- ubfxhi r4, r4, #27, #1
- ubfxls r4, r4, #29, #1
- b .L1486
-.L1450:
- cmp r1, #3
- bls .L1452
- ldr ip, [sp, #20]
- ldr r4, [sp, #20]
- ldr r3, [sp, #20]
- ubfx ip, ip, #3, #5
- ldr lr, [sp, #20]
- ubfx r4, r4, #28, #1
- ubfx r3, r3, #16, #5
- ubfx lr, lr, #30, #1
- orr ip, ip, r4, asl #5
- orr r3, r3, lr, asl #5
- cmp ip, r3
- ldr r3, [sp, #20]
- ldrhi r4, [sp, #20]
- ubfxhi r3, r3, #3, #5
- ldrls r4, [sp, #20]
- ubfxls r3, r3, #16, #5
- ubfxhi r4, r4, #28, #1
- ubfxls r4, r4, #30, #1
-.L1486:
- orr r4, r3, r4, asl #5
-.L1452:
- cmp fp, r4
- movcc fp, r4
- b .L1449
-.L1472:
- mvn fp, #0
-.L1449:
- add r2, r2, #1
- b .L1448
-.L1444:
+ bne .L1446
+ mov r2, #64
+ mov r1, #255
+ add r0, sp, #24
+ bl ftl_memset
+ add r4, sp, #24
+.L1446:
mov r3, #0
- str r3, [r8, #16]
- b .L1455
-.L1442:
- cmp r1, #1
- mov r4, #0
- bne .L1484
- mov fp, r4
-.L1456:
- cmp r4, r7
- bcs .L1488
- ldr r2, [sp, #128]
- cmp r10, #0
- addne r3, r10, r4, asl #9
- ldr r1, [sp, #128]
- moveq r3, r10
- cmp r2, #0
- and ip, r4, #3
- mov r0, r8
- movne r2, #2
- moveq r2, #0
- mla r2, r4, r2, r1
- mov r1, #1
- str ip, [sp, #8]
- add r4, r4, #2
- str r2, [sp]
- mov r2, ip
- bl NandcCopy1KB
- mov r0, r9
- mov r1, #1
- mov r2, #2
- ldr ip, [sp, #8]
- str fp, [sp]
- str fp, [sp, #4]
- mov r3, ip
- bl NandcXferStart
- mov r0, r9
- mov r1, #1
- bl NandcXferComp
- b .L1456
-.L1488:
- mov fp, #0
- b .L1455
-.L1484:
- str r4, [sp]
- mov r1, r4
- str r4, [sp, #4]
- mov r2, #2
- mov r3, r4
- mov fp, r4
- bl NandcXferStart
- str r10, [sp, #8]
-.L1461:
- cmp r4, r7
- bcs .L1455
- mov r0, r9
+ ldr r2, [sp, #8]
mov r1, r5
- bl NandcXferComp
- ldr r3, [r8, #32]
- add ip, r4, #2
- cmp ip, r7
- str r3, [sp, #20]
- bcs .L1462
- mov r3, #0
- mov r0, r9
- str r3, [sp]
- mov r1, r3
- str r3, [sp, #4]
- mov r2, #2
- and r3, ip, #3
- str ip, [sp, #12]
+ mov r0, r7
+ str r4, [sp, #4]
+ str r8, [sp]
bl NandcXferStart
- ldr ip, [sp, #12]
-.L1462:
- ldr r3, [sp, #20]
- tst r3, #4
- mvnne fp, #0
- bne .L1463
- ldr r2, [sp, #20]
- ldr r3, [sp, #20]
- ubfx r2, r2, #3, #5
- ubfx r3, r3, #27, #1
- orr r3, r2, r3, asl #5
- cmp fp, r3
- movcc fp, r3
-.L1463:
- ldr r1, [sp, #128]
- cmp r10, #0
- ldr r3, [sp, #8]
- sub r2, ip, #2
- moveq r3, #0
- ldr r0, [sp, #128]
- cmp r1, #0
- and r2, r2, #3
- str ip, [sp, #12]
- movne r1, #2
- moveq r1, #0
- mla r4, r4, r1, r0
- mov r0, r8
- mov r1, #0
- str r4, [sp]
- bl NandcCopy1KB
- ldr ip, [sp, #12]
- ldr r3, [sp, #8]
- mov r4, ip
- add r3, r3, #1024
- str r3, [sp, #8]
- b .L1461
-.L1455:
- ldr r3, [r6, #2260]
- clz r5, r5
- cmp r3, #5
- mov r5, r5, lsr #5
- movls r5, #0
+ mov r1, r5
+ mov r0, r7
+ bl NandcXferComp
cmp r5, #0
- beq .L1467
- ldr r3, [r8]
+ movne r9, #0
+ bne .L1447
+ ldr r3, [r9, #2312]
+ mov r2, r5
+ cmp r3, #25
+ ldr r3, [sp, #8]
+ movcc ip, #64
+ movcs ip, #128
+ lsr r1, r3, #1
+ mov r3, r5
+.L1449:
+ cmp r2, r1
+ add r4, r4, #4
+ add r0, ip, r3
+ bcc .L1450
+ ldr r3, [sp, #8]
+ mov r2, #0
+ ldr r1, [r9, #2312]
+ ldr ip, [r9, #2264]
+ mov r9, r2
+ lsr r0, r3, #2
+.L1451:
+ cmp r2, r0
+ bcs .L1447
+ cmp r1, #0
+ bne .L1457
+.L1447:
+ mov r3, #0
+ str r3, [r6, #16]
+.L1458:
+ ldr r3, .L1484
+ ldr r3, [r3, #2264]
+ cmp r3, #5
+ movls r3, #0
+ movhi r3, #1
+ cmp r5, #0
+ movne r3, #0
+ cmp r3, #0
+ beq .L1444
+ ldr r3, [r6]
and r2, r3, #139264
cmp r2, #139264
+ mvneq r9, #0
orreq r3, r3, #131072
- streq r3, [r8]
- mvneq fp, #0
-.L1467:
- mov r0, fp
+ streq r3, [r6]
+.L1444:
+ mov r0, r9
add sp, sp, #92
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1490:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1450:
+ ldr lr, [r9, #2280]
+ bic r3, r3, #3
+ add r2, r2, #1
+ ldr r3, [lr, r3]
+ strb r3, [r4, #-4]
+ lsr lr, r3, #8
+ strb lr, [r4, #-3]
+ lsr lr, r3, #16
+ lsr r3, r3, #24
+ strb lr, [r4, #-2]
+ strb r3, [r4, #-1]
+ mov r3, r0
+ b .L1449
+.L1457:
+ add r3, r2, #8
+ ldr r3, [r6, r3, lsl #2]
+ str r3, [sp, #20]
+ ldr r3, [sp, #20]
+ tst r3, #4
+ bne .L1473
+ ldr r3, [sp, #20]
+ ubfx r3, r3, #15, #1
+ cmp r3, #0
+ bne .L1473
+ cmp ip, #5
+ bls .L1453
+ ldr lr, [sp, #20]
+ ldr r7, [sp, #20]
+ ldr r3, [sp, #20]
+ ldr r4, [sp, #20]
+ ubfx lr, lr, #3, #5
+ ubfx r7, r7, #27, #1
+ ubfx r3, r3, #16, #5
+ orr lr, lr, r7, lsl #5
+ ubfx r4, r4, #29, #1
+ orr r3, r3, r4, lsl #5
+ cmp lr, r3
+ ldr r3, [sp, #20]
+ ldrhi lr, [sp, #20]
+ ldrls lr, [sp, #20]
+ ubfxhi r3, r3, #3, #5
+ ubfxls r3, r3, #16, #5
+ ubfxhi lr, lr, #27, #1
+ ubfxls lr, lr, #29, #1
+.L1483:
+ orr r3, r3, lr, lsl #5
+.L1455:
+ cmp r9, r3
+ movcc r9, r3
+.L1452:
+ add r2, r2, #1
+ b .L1451
+.L1453:
+ cmp ip, #3
+ bls .L1455
+ ldr lr, [sp, #20]
+ ldr r7, [sp, #20]
+ ldr r3, [sp, #20]
+ ldr r4, [sp, #20]
+ ubfx lr, lr, #3, #5
+ ubfx r7, r7, #28, #1
+ ubfx r3, r3, #16, #5
+ orr lr, lr, r7, lsl #5
+ ubfx r4, r4, #30, #1
+ orr r3, r3, r4, lsl #5
+ cmp lr, r3
+ ldr r3, [sp, #20]
+ ldrhi lr, [sp, #20]
+ ldrls lr, [sp, #20]
+ ubfxhi r3, r3, #3, #5
+ ubfxls r3, r3, #16, #5
+ ubfxhi lr, lr, #28, #1
+ ubfxls lr, lr, #30, #1
+ b .L1483
+.L1473:
+ mvn r9, #0
+ b .L1452
+.L1445:
+ cmp r1, #1
+ bne .L1459
+ mov r9, #0
+ cmp r4, #0
+ mov r10, r9
+ movne r3, #4
+ moveq r3, #0
+ str r3, [sp, #12]
+.L1460:
+ ldr r3, [sp, #8]
+ cmp r9, r3
+ movcs r9, #0
+ bcs .L1458
+.L1462:
+ cmp r8, #0
+ and fp, r9, #3
+ addne r3, r8, r9, lsl #9
+ moveq r3, r8
+ str r4, [sp]
+ mov r2, fp
+ mov r1, #1
+ mov r0, r6
+ bl NandcCopy1KB
+ mov r3, fp
+ mov r2, #2
+ mov r1, #1
+ mov r0, r7
+ str r10, [sp, #4]
+ add r9, r9, #2
+ str r10, [sp]
+ bl NandcXferStart
+ mov r1, #1
+ mov r0, r7
+ bl NandcXferComp
+ ldr r3, [sp, #12]
+ add r4, r4, r3
+ b .L1460
+.L1459:
+ mov r10, #0
+ mov r2, #2
+ mov r3, r10
+ str r10, [sp, #4]
+ str r10, [sp]
+ mov r1, r10
+ bl NandcXferStart
+ mov fp, r8
+ cmp r4, r10
+ mov r9, r10
+ movne r3, #4
+ moveq r3, r10
+ str r3, [sp, #12]
+.L1463:
+ ldr r3, [sp, #8]
+ cmp r10, r3
+ bcs .L1458
+ mov r1, r5
+ mov r0, r7
+ bl NandcXferComp
+ ldr r3, [r6, #32]
+ add r10, r10, #2
+ str r3, [sp, #20]
+ ldr r3, [sp, #8]
+ cmp r3, r10
+ bls .L1464
+ mov r3, #0
+ mov r2, #2
+ str r3, [sp, #4]
+ mov r1, #0
+ str r3, [sp]
+ mov r0, r7
+ and r3, r10, #3
+ bl NandcXferStart
+.L1464:
+ ldr r3, [sp, #20]
+ tst r3, #4
+ mvnne r9, #0
+ bne .L1465
+ ldr r3, [sp, #20]
+ ldr r2, [sp, #20]
+ ubfx r3, r3, #3, #5
+ ubfx r2, r2, #27, #1
+ orr r3, r3, r2, lsl #5
+ cmp r9, r3
+ movcc r9, r3
+.L1465:
+ cmp r8, #0
+ sub r2, r10, #2
+ movne r3, fp
+ str r4, [sp]
+ moveq r3, #0
+ and r2, r2, #3
+ mov r1, #0
+ mov r0, r6
+ bl NandcCopy1KB
+ ldr r3, [sp, #12]
+ add fp, fp, #1024
+ add r4, r4, r3
+ b .L1463
+.L1485:
.align 2
-.L1489:
+.L1484:
.word .LANCHOR0
.fnend
.size NandcXferData, .-NandcXferData
.align 2
.global FlashReadRawPage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadRawPage, %function
FlashReadRawPage:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
+ push {r0, r1, r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
.pad #8
mov r8, r3
- ldr r3, .L1494
+ ldr r3, .L1489
subs r4, r0, #0
mov r6, r1
mov r7, r2
- ldrb r5, [r3, #481] @ zero_extendqisi2
- bne .L1492
- ldr r2, .L1494+4
- ldrb r3, [r2, #1] @ zero_extendqisi2
- ldr r2, [r2, #4]
- mul r2, r2, r3
- cmp r1, r2
- movcc r5, #4
-.L1492:
+ ldrb r5, [r3, #477] @ zero_extendqisi2
+ bne .L1487
+ ldr r1, .L1489+4
+ ldrb r3, [r1, #37] @ zero_extendqisi2
+ ldr r0, [r1, #40]
+ mul r0, r0, r3
+ cmp r0, r6
+ movhi r5, #4
+.L1487:
mov r0, r4
bl NandcWaitFlashReady
mov r0, r4
@@ -8845,181 +9337,177 @@
bl FlashReadCmd
mov r0, r4
bl NandcWaitFlashReady
- mov r2, r5
- mov r1, #0
mov r3, r7
- mov r0, r4
+ mov r2, r5
str r8, [sp]
+ mov r1, #0
+ mov r0, r4
bl NandcXferData
- mov r5, r0
+ mov r1, r0
mov r0, r4
bl NandcFlashDeCs
- mov r0, r5
+ mov r0, r1
add sp, sp, #8
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L1495:
+ pop {r4, r5, r6, r7, r8, pc}
+.L1490:
.align 2
-.L1494:
+.L1489:
.word .LANCHOR1
.word .LANCHOR0
.fnend
.size FlashReadRawPage, .-FlashReadRawPage
.align 2
.global FlashDdrTunningRead
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashDdrTunningRead, %function
FlashDdrTunningRead:
.fnstart
@ args = 4, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r7, r3
- ldr r4, .L1523
+ ldr r4, .L1517
.pad #20
sub sp, sp, #20
- mov r10, r0
mov fp, r2
- str r1, [sp]
- ldr r3, [r4, #80]
+ stm sp, {r0, r1}
+ ldr r3, [r4, #88]
ldr r3, [r3, #304]
- str r3, [sp, #8]
- ldr r3, [r4, #2260]
+ str r3, [sp, #12]
+ ldr r3, [r4, #2264]
cmp r3, #8
ldr r3, [sp, #56]
- movcc r9, #6
- movcs r9, #12
+ movcc r10, #6
+ movcs r10, #12
cmp r3, #0
- moveq r6, #1024
- beq .L1498
+ moveq r5, #1024
+ beq .L1493
mov r0, #1
bl FlashSetInterfaceMode
mov r0, #1
bl NandcSetMode
- mov r0, r10
+ ldr r0, [sp]
bl FlashReset
- mov r2, fp
mov r3, r7
- mov r0, r10
- ldr r1, [sp]
+ mov r2, fp
+ ldm sp, {r0, r1}
bl FlashReadRawPage
- mov r6, r0
- ldrb r0, [r4, #2229] @ zero_extendqisi2
+ mov r5, r0
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
bl FlashSetInterfaceMode
- ldrb r0, [r4, #2229] @ zero_extendqisi2
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
bl NandcSetMode
- cmn r6, #1
- bne .L1499
-.L1508:
- mvn r6, #0
- b .L1500
-.L1499:
- mov r2, r6
- ldr r0, .L1523+4
- ldr r1, [sp]
+ cmn r5, #1
+ bne .L1494
+.L1503:
+ mvn r5, #0
+.L1491:
+ mov r0, r5
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1494:
+ mov r2, r5
+ ldr r1, [sp, #4]
+ ldr r0, .L1517+4
bl printk
- cmp r6, #9
- addls r4, r4, r10, asl #3
- ldrls r3, [r4, #12]
- ldr r4, .L1523+8
+ cmp r5, #9
+ ldrls r3, [sp]
+ ldrls r3, [r4, r3, lsl #3]
ldrls r2, [r3, #3840]
ldrls r2, [r3]
orrls r2, r2, #131072
strls r2, [r3]
- ldr r3, [r4, #1692]
+ ldr r2, .L1517+8
+ ldr r3, [r2, #1700]
add r3, r3, #1
- str r3, [r4, #1692]
cmp r3, #2048
+ str r3, [r2, #1700]
movcs r7, #0
- strcs r7, [r4, #1692]
+ strcs r7, [r2, #1700]
movcs fp, r7
- bcc .L1500
-.L1498:
- mov r4, #0
+ bcc .L1491
+.L1493:
+ mov r9, #0
mvn r8, #0
- mov ip, r4
- mov r5, r4
- str r4, [sp, #4]
-.L1506:
- uxtb r0, r9
- str ip, [sp, #12]
+ mov r6, r9
+ mov r4, r9
+ str r9, [sp, #8]
+.L1501:
+ uxtb r0, r10
bl NandcSetDdrPara
mov r3, r7
- mov r0, r10
mov r2, fp
- ldr r1, [sp]
+ ldm sp, {r0, r1}
bl FlashReadRawPage
- add r3, r6, #1
+ add r3, r5, #1
cmp r0, r3
- ldr ip, [sp, #12]
- bhi .L1502
+ bhi .L1497
cmp r0, #2
- bhi .L1512
- add r5, r5, #1
- cmp r5, #9
- bls .L1512
- rsb r4, r5, r9
- mov r6, r0
+ bhi .L1507
+ add r4, r4, #1
+ cmp r4, #9
+ bls .L1507
+ mov r3, r6
+ mov r5, r0
+ sub r6, r10, r4
mov r8, #0
- b .L1504
-.L1502:
- ldr r3, [sp, #4]
- cmp r3, r5
- bcs .L1513
- cmp r5, #7
- rsb ip, r5, r4
- bhi .L1514
- str r5, [sp, #4]
- b .L1513
-.L1512:
- mov r8, #0
- mov r4, r9
- mov r6, r0
- mov r7, r8
- mov fp, r8
- b .L1503
-.L1513:
- mov r5, #0
-.L1503:
- add r9, r9, #2
- cmp r9, #69
- bls .L1506
-.L1504:
- ldr r3, [sp, #4]
- cmp r3, r5
- movcs r4, ip
- b .L1505
-.L1514:
- mov r4, ip
-.L1505:
- cmp r4, #0
- beq .L1507
- ldr r0, .L1523+12
- mov r1, r4
+.L1499:
+ ldr r2, [sp, #8]
+ cmp r4, r2
+ movls r6, r3
+.L1500:
+ cmp r6, #0
+ beq .L1502
+ mov r1, r6
+ ldr r0, .L1517+12
bl printk
- uxtb r0, r4
+ uxtb r0, r6
bl NandcSetDdrPara
-.L1507:
+.L1502:
cmn r8, #1
- bne .L1500
- ldr r0, .L1523+16
- mov r1, r10
- ldr r2, [sp]
+ bne .L1491
+ ldm sp, {r1, r2}
+ ldr r0, .L1517+16
bl printk
ldr r3, [sp, #56]
cmp r3, #0
- beq .L1508
- ldr r3, [sp, #8]
+ beq .L1503
+ ldr r3, [sp, #12]
ubfx r0, r3, #8, #8
bl NandcSetDdrPara
-.L1500:
- mov r0, r6
- add sp, sp, #20
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1524:
+ b .L1491
+.L1497:
+ ldr r3, [sp, #8]
+ cmp r4, r3
+ bls .L1508
+ cmp r4, #7
+ sub r6, r9, r4
+ bhi .L1500
+ str r4, [sp, #8]
+.L1508:
+ mov r4, #0
+ b .L1498
+.L1507:
+ mov r8, #0
+ mov r9, r10
+ mov r5, r0
+ mov r7, r8
+ mov fp, r8
+.L1498:
+ add r10, r10, #2
+ cmp r10, #69
+ bls .L1501
+ mov r3, r6
+ mov r6, r9
+ b .L1499
+.L1518:
.align 2
-.L1523:
+.L1517:
.word .LANCHOR0
.word .LC90
.word .LANCHOR2
@@ -9029,110 +9517,110 @@
.size FlashDdrTunningRead, .-FlashDdrTunningRead
.align 2
.global FlashReadPage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadPage, %function
FlashReadPage:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
mov r5, r0
mov r6, r1
- mov r8, r2
- mov r7, r3
+ mov r7, r2
+ mov r8, r3
bl FlashReadRawPage
cmn r0, #1
mov r4, r0
- bne .L1526
- ldr r9, .L1546
- ldrb fp, [r9, #8] @ zero_extendqisi2
+ bne .L1520
+ ldr r9, .L1539
+ ldrb fp, [r9, #44] @ zero_extendqisi2
mov r10, r9
cmp fp, #0
- bne .L1527
-.L1529:
- ldrb r3, [r10, #2252] @ zero_extendqisi2
- ldr r9, .L1546
+ bne .L1521
+.L1523:
+ ldrb r3, [r10, #2256] @ zero_extendqisi2
cmp r3, #0
- beq .L1526
- b .L1545
-.L1527:
- mov r3, #0
- mov r0, r5
- strb r3, [r9, #8]
+ beq .L1520
+ ldr r3, [r10, #88]
+ mov r2, r7
mov r1, r6
- mov r2, r8
- mov r3, r7
- bl FlashReadRawPage
- strb fp, [r9, #8]
- cmn r0, #1
- movne r4, r0
- beq .L1529
- b .L1526
-.L1545:
- ldr r3, [r9, #80]
mov r0, r5
- mov r1, r6
- mov r2, r8
- ldr r10, [r3, #304]
+ ldr r9, [r3, #304]
mov r3, #1
str r3, [sp]
- mov r3, r7
+ mov r3, r8
bl FlashDdrTunningRead
cmn r0, #1
mov r4, r0
- beq .L1530
- ldrb r3, [r9, #2312] @ zero_extendqisi2
+ beq .L1524
+ ldrb r3, [r10, #2316] @ zero_extendqisi2
cmp r0, r3, lsr #1
- bls .L1526
-.L1530:
- ubfx r0, r10, #8, #8
+ bls .L1520
+.L1524:
+ ubfx r0, r9, #8, #8
bl NandcSetDdrPara
-.L1526:
- ldr r9, .L1546+4
- ldr ip, [r9, #1696]
- adds r3, ip, #0
+ b .L1520
+.L1521:
+ mov r3, #0
+ mov r2, r7
+ strb r3, [r9, #44]
+ mov r1, r6
+ mov r3, r8
+ mov r0, r5
+ bl FlashReadRawPage
+ cmn r0, #1
+ strb fp, [r9, #44]
+ movne r4, r0
+ beq .L1523
+.L1520:
+ ldr r9, .L1539+4
+ ldr r10, [r9, #1704]
+ adds r3, r10, #0
movne r3, #1
cmn r4, #1
movne r3, #0
cmp r3, #0
- beq .L1531
+ beq .L1519
+ mov r3, r8
+ mov r2, r7
mov r1, r6
- mov r2, r8
- mov r3, r7
mov r0, r5
- blx ip
- mov r2, r5
+ blx r10
mov r3, r6
mov r4, r0
- ldr r0, .L1546+8
- mov r1, r4
+ mov r1, r0
+ mov r2, r5
+ ldr r0, .L1539+8
bl printk
cmn r4, #1
- bne .L1531
- ldr r3, .L1546
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ bne .L1519
+ ldr r3, .L1539
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L1531
+ beq .L1519
mov r0, r5
bl flash_enter_slc_mode
- ldr ip, [r9, #1696]
- mov r0, r5
+ ldr r4, [r9, #1704]
+ mov r3, r8
+ mov r2, r7
mov r1, r6
- mov r2, r8
- mov r3, r7
- blx ip
+ mov r0, r5
+ blx r4
mov r4, r0
mov r0, r5
bl flash_exit_slc_mode
-.L1531:
+.L1519:
mov r0, r4
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1547:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1540:
.align 2
-.L1546:
+.L1539:
.word .LANCHOR0
.word .LANCHOR2
.word .LC93
@@ -9140,587 +9628,601 @@
.size FlashReadPage, .-FlashReadPage
.align 2
.global FlashDdrParaScan
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashDdrParaScan, %function
FlashDdrParaScan:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
+ push {r0, r1, r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
.pad #8
- mov r7, r0
- ldr r5, .L1558
- mov r6, r1
+ mov r6, r0
+ ldr r5, .L1551
mov r4, #0
- ldrb r0, [r5, #2229] @ zero_extendqisi2
+ mov r7, r1
+ ldrb r0, [r5, #2233] @ zero_extendqisi2
bl FlashSetInterfaceMode
- ldrb r0, [r5, #2229] @ zero_extendqisi2
+ ldrb r0, [r5, #2233] @ zero_extendqisi2
bl NandcSetMode
- mov r1, r6
- mov r2, r4
mov r3, r4
- mov r0, r7
+ mov r2, r4
+ mov r1, r7
str r4, [sp]
+ mov r0, r6
bl FlashDdrTunningRead
mov r3, r4
- mov r1, r6
- mov r2, r4
mov r8, r0
- mov r0, r7
+ mov r2, r4
+ mov r1, r7
+ mov r0, r6
bl FlashReadRawPage
+ cmn r8, #1
+ cmnne r0, #1
mov r3, r5
- cmn r0, #1
- cmnne r8, #1
- bne .L1549
- ldrb r2, [r5, #2229] @ zero_extendqisi2
+ bne .L1542
+ ldrb r2, [r5, #2233] @ zero_extendqisi2
tst r2, #1
- beq .L1549
+ beq .L1542
mov r0, #1
bl FlashSetInterfaceMode
mov r0, #1
bl NandcSetMode
- strb r4, [r5, #2252]
- b .L1550
-.L1549:
- mov r2, #1
- strb r2, [r3, #2252]
-.L1550:
+ strb r4, [r5, #2256]
+.L1543:
mov r0, #0
add sp, sp, #8
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L1559:
+ pop {r4, r5, r6, r7, r8, pc}
+.L1542:
+ mov r2, #1
+ strb r2, [r3, #2256]
+ b .L1543
+.L1552:
.align 2
-.L1558:
+.L1551:
.word .LANCHOR0
.fnend
.size FlashDdrParaScan, .-FlashDdrParaScan
.align 2
.global FlashLoadPhyInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashLoadPhyInfo, %function
FlashLoadPhyInfo:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov r3, #60
.pad #20
sub sp, sp, #20
- ldr r3, .L1576
- mov r4, #0
- ldr r7, .L1576+4
- mov r9, #4
- ldr r5, .L1576+8
- mvn r8, #0
- ldr r0, [r3] @ unaligned
- ldr r3, [r7, #4]
- str r4, [r5, #1704]
- mov r6, r5
- str r0, [sp, #12] @ unaligned
- mov r0, r4
+ ldr r6, .L1568
+ mov r5, #0
+ mov r8, #4
+ strb r3, [sp, #12]
+ mov r3, #40
+ strb r3, [sp, #13]
+ mov r3, #24
+ strb r3, [sp, #14]
+ mov r3, #16
+ ldr r4, .L1568+4
+ mvn r7, #0
+ strb r3, [sp, #15]
+ mov r0, r5
+ ldr r3, [r6, #40]
+ str r5, [r4, #1712]
str r3, [sp, #4]
- ldr r3, [r5, #1688]
- str r3, [r5, #1700]
+ ldr r3, [r4, #1696]
+ str r3, [r4, #1708]
bl flash_enter_slc_mode
-.L1561:
- add fp, r4, #1
- mov r10, #0
-.L1563:
- add r3, sp, #12
- ldrb r0, [r3, r10] @ zero_extendqisi2
+.L1554:
+ add fp, r5, #1
+ mov r9, #0
+ add r10, sp, #12
+.L1556:
+ ldrb r0, [r10, r9] @ zero_extendqisi2
bl FlashBchSel
- mov r0, #0
- mov r1, r4
- ldr r2, [r5, #1688]
- mov r3, r0
+ mov r3, #0
+ ldr r2, [r4, #1696]
+ mov r1, r5
+ mov r0, r3
bl FlashReadRawPage
cmn r0, #1
- bne .L1562
- mov r0, #0
+ bne .L1555
+ mov r3, #0
+ ldr r2, [r4, #1696]
mov r1, fp
- ldr r2, [r6, #1688]
- mov r3, r0
+ mov r0, r3
bl FlashReadRawPage
cmn r0, #1
- bne .L1562
- add r10, r10, #1
- cmp r10, #4
- beq .L1564
- b .L1563
-.L1565:
- add r0, fp, #12
- movw r1, #2036
- bl js_hash
- ldr r3, [fp, #8]
- cmp r3, r0
- mvnne r8, #0
- bne .L1564
- ldr r8, .L1576+12
- add r1, fp, #160
- mov r2, #32
+ bne .L1555
+ add r9, r9, #1
+ cmp r9, #4
+ bne .L1556
+.L1557:
+ ldr r3, [sp, #4]
+ subs r8, r8, #1
+ add r5, r5, r3
+ bne .L1554
mov r0, r8
- bl ftl_memcpy
- ldr r1, [r6, #1700]
+ b .L1567
+.L1558:
+ movw r1, #2036
+ add r0, r9, #12
+ bl js_hash
+ ldr r3, [r9, #8]
+ cmp r3, r0
+ mvnne r7, #0
+ bne .L1557
mov r2, #32
- ldr r0, .L1576+16
+ add r1, r9, #160
+ ldr r0, .L1568+8
+ bl ftl_memcpy
+ ldr r1, [r4, #1708]
+ mov r2, #32
+ ldr r0, .L1568+12
add r1, r1, #192
bl ftl_memcpy
- ldr r1, [r6, #1700]
+ ldr r1, [r4, #1708]
mov r2, #852
- ldr r0, .L1576+20
+ ldr r0, .L1568+16
add r1, r1, #224
bl ftl_memcpy
- ldrh r0, [r8, #10]
+ ldr r3, .L1568+8
+ ldrh r0, [r3, #10]
bl FlashBlockAlignInit
- ldr r8, [r6, #1700]
- str r4, [r6, #1704]
- mov r0, r4
- ldr r1, [r7, #4]
- ldr r3, [r8, #1076]
- strb r3, [r7, #2252]
+ ldr r7, [r4, #1708]
+ mov r0, r5
+ str r5, [r4, #1712]
+ ldr r1, [r6, #40]
+ ldr r3, [r7, #1076]
+ strb r3, [r6, #2256]
bl __aeabi_uidiv
add r0, r0, #1
cmp r0, #1
- strhi r0, [r6, #1708]
movls r3, #2
- strls r3, [r6, #1708]
- ldrh r3, [r8, #14]
- mov r8, #0
- strb r3, [r5, #1712]
-.L1564:
- ldr r3, [sp, #4]
- subs r9, r9, #1
- add r4, r4, r3
- bne .L1561
- mov r0, r9
-.L1575:
+ strhi r0, [r4, #1716]
+ strls r3, [r4, #1716]
+ ldrh r3, [r7, #14]
+ mov r7, #0
+ strb r3, [r4, #1720]
+ b .L1557
+.L1555:
+ ldr r9, [r4, #1708]
+ ldr r2, .L1568+20
+ ldr r3, [r9]
+ cmp r3, r2
+ bne .L1557
+ cmp r7, #0
+ bne .L1558
+ ldr r1, [r6, #40]
+ mov r0, r5
+ bl __aeabi_uidiv
+ add r0, r0, #1
+ str r0, [r4, #1716]
+ mov r0, r7
+.L1567:
bl flash_exit_slc_mode
- mov r0, r8
+ mov r0, r7
add sp, sp, #20
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1562:
- ldr fp, [r5, #1700]
- ldr r2, .L1576+24
- ldr r3, [fp]
- cmp r3, r2
- bne .L1564
- cmp r8, #0
- bne .L1565
- mov r0, r4
- ldr r1, [r7, #4]
- bl __aeabi_uidiv
- ldr r3, .L1576+8
- add r0, r0, #1
- str r0, [r3, #1708]
- mov r0, r8
- b .L1575
-.L1577:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1569:
.align 2
-.L1576:
- .word .LANCHOR3+11
+.L1568:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR1+472
- .word .LANCHOR0+48
- .word .LANCHOR0+1210
+ .word .LANCHOR1+468
+ .word .LANCHOR0+52
+ .word .LANCHOR0+1216
.word 1312902724
.fnend
.size FlashLoadPhyInfo, .-FlashLoadPhyInfo
.align 2
.global ToshibaReadRetrial
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ToshibaReadRetrial, %function
ToshibaReadRetrial:
.fnstart
@ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov r8, r0
+ ldr r4, .L1598
.pad #28
sub sp, sp, #28
- mov r9, r0
mov fp, r3
+ str r1, [sp, #12]
str r2, [sp, #8]
- str r1, [sp, #16]
bl NandcWaitFlashReady
- ldr r4, .L1607
- add r3, r4, r9, asl #3
- ldrb r2, [r3, #16] @ zero_extendqisi2
- ldr r6, [r3, #12]
- ldrb r3, [r4, #1208] @ zero_extendqisi2
- add r7, r2, #8
+ add r3, r4, r8, lsl #3
+ ldr r6, [r4, r8, lsl #3]
+ ldrb r1, [r3, #4] @ zero_extendqisi2
+ ldrb r3, [r4, #84] @ zero_extendqisi2
+ add r7, r1, #8
sub r3, r3, #67
- add r7, r6, r7, asl #8
+ add r7, r6, r7, lsl #8
cmp r3, #1
- mov r3, r2, asl #8
- str r3, [sp, #12]
- movls r3, #0
- strls r3, [sp, #4]
- bls .L1579
- ldrb r5, [r4, #2252] @ zero_extendqisi2
+ lsl r3, r1, #8
+ movls r5, #0
+ str r3, [sp, #16]
+ bls .L1571
+ ldrb r5, [r4, #2256] @ zero_extendqisi2
cmp r5, #0
- streq r5, [sp, #4]
- beq .L1580
+ beq .L1572
+ mov r5, #1
mov r0, #0
- str r2, [sp, #20]
bl NandcSetDdrMode
- mov r3, #1
- ldr r2, [sp, #20]
- str r3, [sp, #4]
-.L1580:
- ldr r3, [sp, #12]
- mov r1, #92
+.L1572:
+ lsl r3, r1, #8
+ mov r2, #92
add r3, r6, r3
- str r1, [r3, #2056]
- mov r1, #197
- str r1, [r3, #2056]
-.L1579:
- mov r8, #1
- mvn r10, #0
- mov r3, r2, asl #8
+ str r2, [r3, #2056]
+ mov r2, #197
+ str r2, [r3, #2056]
+.L1571:
+ mvn r3, #0
+ mov r9, #1
+ str r3, [sp, #4]
+ lsl r3, r1, #8
str r3, [sp, #20]
-.L1581:
- ldr r3, .L1607+4
- ldrb r3, [r3, #1713] @ zero_extendqisi2
+.L1573:
+ ldr r3, .L1598+4
+ ldrb r3, [r3, #1721] @ zero_extendqisi2
add r3, r3, #1
- cmp r8, r3
- bcs .L1606
- ldrb r3, [r4, #1208] @ zero_extendqisi2
+ cmp r9, r3
+ bcc .L1582
+ ldr r10, [sp, #4]
+.L1581:
+ ldrb r2, [r4, #84] @ zero_extendqisi2
+ mov r1, #0
mov r0, r7
- uxtb r1, r8
+ sub r2, r2, #67
+ cmp r2, #1
+ bhi .L1583
+ bl SandiskSetRRPara
+.L1584:
+ ldr r3, [sp, #16]
+ mov r2, #255
+ add r6, r6, r3
+ str r2, [r6, #2056]
+ ldrb r2, [r4, #2316] @ zero_extendqisi2
+ add r2, r2, r2, lsl #1
+ cmp r10, r2, asr #2
+ bcc .L1585
+ cmn r10, #1
+ movne r10, #256
+.L1585:
+ mov r0, r8
+ bl NandcWaitFlashReady
+ cmp r5, #0
+ beq .L1570
+ mov r0, #4
+ bl NandcSetDdrMode
+.L1570:
+ mov r0, r10
+ add sp, sp, #28
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1582:
+ ldrb r3, [r4, #84] @ zero_extendqisi2
+ mov r0, r7
+ uxtb r1, r9
sub r3, r3, #67
cmp r3, #1
- bhi .L1582
+ bhi .L1574
bl SandiskSetRRPara
- b .L1583
-.L1582:
- bl ToshibaSetRRPara
-.L1583:
- ldrb r3, [r4, #1208] @ zero_extendqisi2
+.L1575:
+ ldrb r3, [r4, #84] @ zero_extendqisi2
cmp r3, #34
- bne .L1584
- ldr r3, .L1607+4
- ldrb r3, [r3, #1713] @ zero_extendqisi2
+ bne .L1576
+ ldr r3, .L1598+4
+ ldrb r3, [r3, #1721] @ zero_extendqisi2
sub r3, r3, #3
- cmp r8, r3
+ cmp r9, r3
ldreq r3, [sp, #20]
moveq r2, #179
addeq r3, r6, r3
streq r2, [r3, #2056]
-.L1584:
- ldr r3, [sp, #12]
+.L1576:
+ ldr r3, [sp, #16]
mov r2, #38
+ cmp r5, #0
add r3, r6, r3
str r2, [r3, #2056]
mov r2, #93
str r2, [r3, #2056]
- ldr r3, [sp, #4]
- cmp r3, #0
- beq .L1585
+ beq .L1577
mov r0, #4
bl NandcSetDdrMode
- mov r0, r9
mov r3, fp
- ldr r1, [sp, #16]
ldr r2, [sp, #8]
+ ldr r1, [sp, #12]
+ mov r0, r8
bl FlashReadRawPage
- mov r5, r0
+ mov r10, r0
mov r0, #0
bl NandcSetDdrMode
- b .L1586
-.L1585:
- mov r0, r9
- ldr r1, [sp, #16]
- ldr r2, [sp, #8]
- mov r3, fp
- bl FlashReadRawPage
- mov r5, r0
-.L1586:
- cmn r5, #1
- beq .L1587
- ldrb r2, [r4, #2312] @ zero_extendqisi2
+.L1578:
cmn r10, #1
- moveq r10, r5
- add r2, r2, r2, asl #1
- cmp r5, r2, asr #2
- bcc .L1589
+ beq .L1579
+ ldrb r2, [r4, #2316] @ zero_extendqisi2
+ ldr r3, [sp, #4]
+ add r2, r2, r2, lsl #1
+ cmn r3, #1
+ moveq r3, r10
+ cmp r10, r2, asr #2
+ str r3, [sp, #4]
+ bcc .L1581
mov fp, #0
str fp, [sp, #8]
-.L1587:
- add r8, r8, #1
- b .L1581
-.L1606:
- mov r5, r10
-.L1589:
- ldrb r2, [r4, #1208] @ zero_extendqisi2
- mov r0, r7
- mov r1, #0
- sub r2, r2, #67
- cmp r2, #1
- bhi .L1591
- bl SandiskSetRRPara
- b .L1592
-.L1591:
+.L1579:
+ add r9, r9, #1
+ b .L1573
+.L1574:
bl ToshibaSetRRPara
-.L1592:
- ldr r3, [sp, #12]
- mov r2, #255
- add r6, r6, r3
- str r2, [r6, #2056]
- ldrb r2, [r4, #2312] @ zero_extendqisi2
- add r2, r2, r2, asl #1
- cmp r5, r2, asr #2
- bcc .L1593
- cmn r5, #1
- movne r5, #256
-.L1593:
- mov r0, r9
- bl NandcWaitFlashReady
- ldr r3, [sp, #4]
- cmp r3, #0
- beq .L1594
- mov r0, #4
- bl NandcSetDdrMode
-.L1594:
- mov r0, r5
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1608:
+ b .L1575
+.L1577:
+ mov r3, fp
+ ldr r2, [sp, #8]
+ ldr r1, [sp, #12]
+ mov r0, r8
+ bl FlashReadRawPage
+ mov r10, r0
+ b .L1578
+.L1583:
+ bl ToshibaSetRRPara
+ b .L1584
+.L1599:
.align 2
-.L1607:
+.L1598:
.word .LANCHOR0
.word .LANCHOR2
.fnend
.size ToshibaReadRetrial, .-ToshibaReadRetrial
.align 2
.global SamsungReadRetrial
+ .syntax unified
+ .arm
+ .fpu softvfp
.type SamsungReadRetrial, %function
SamsungReadRetrial:
.fnstart
- @ args = 0, pretend = 0, frame = 8
+ @ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #12
- mov r9, r0
- ldr r5, .L1623
- mov r10, r2
- mov r8, r3
+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov r8, r0
+ ldr r5, .L1614
+ mov r9, r3
mov fp, r1
+ mov r10, r2
bl NandcWaitFlashReady
- add r2, r5, r9, asl #3
- ldr ip, .L1623+4
mov r7, #1
- ldrb r3, [r2, #16] @ zero_extendqisi2
mvn r4, #0
- ldr r6, [r2, #12]
- add r3, r3, #8
- add r6, r6, r3, asl #8
-.L1610:
- ldrb r3, [ip, #1713] @ zero_extendqisi2
+ add r3, r5, r8, lsl #3
+ ldrb r6, [r3, #4] @ zero_extendqisi2
+ add r3, r6, #8
+ ldr r6, [r5, r8, lsl #3]
+ add r6, r6, r3, lsl #8
+.L1601:
+ ldr r3, .L1614+4
+ ldrb r3, [r3, #1721] @ zero_extendqisi2
add r3, r3, #1
cmp r7, r3
- bcs .L1613
- mov r0, r6
- uxtb r1, r7
- str ip, [sp, #4]
- bl SamsungSetRRPara
- mov r0, r9
- mov r1, fp
- mov r2, r10
- mov r3, r8
- bl FlashReadRawPage
- cmn r0, #1
- ldr ip, [sp, #4]
- beq .L1611
- ldrb r3, [r5, #2312] @ zero_extendqisi2
- cmn r4, #1
- moveq r4, r0
- add r3, r3, r3, asl #1
- cmp r0, r3, asr #2
- bcc .L1616
- mov r8, #0
- mov r10, r8
-.L1611:
- add r7, r7, #1
- b .L1610
-.L1616:
- mov r4, r0
-.L1613:
- mov r0, r6
+ bcc .L1605
+.L1604:
mov r1, #0
+ mov r0, r6
bl SamsungSetRRPara
- ldrb r3, [r5, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
+ ldrb r3, [r5, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
cmp r4, r3, asr #2
- bcc .L1615
+ bcc .L1600
cmn r4, #1
movne r4, #256
-.L1615:
+.L1600:
mov r0, r4
- add sp, sp, #12
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1624:
+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1605:
+ uxtb r1, r7
+ mov r0, r6
+ bl SamsungSetRRPara
+ mov r3, r9
+ mov r2, r10
+ mov r1, fp
+ mov r0, r8
+ bl FlashReadRawPage
+ cmn r0, #1
+ beq .L1602
+ ldrb r3, [r5, #2316] @ zero_extendqisi2
+ cmn r4, #1
+ moveq r4, r0
+ add r3, r3, r3, lsl #1
+ cmp r0, r3, asr #2
+ bcc .L1608
+ mov r9, #0
+ mov r10, r9
+.L1602:
+ add r7, r7, #1
+ b .L1601
+.L1608:
+ mov r4, r0
+ b .L1604
+.L1615:
.align 2
-.L1623:
+.L1614:
.word .LANCHOR0
.word .LANCHOR2
.fnend
.size SamsungReadRetrial, .-SamsungReadRetrial
.align 2
.global MicronReadRetrial
+ .syntax unified
+ .arm
+ .fpu softvfp
.type MicronReadRetrial, %function
MicronReadRetrial:
.fnstart
- @ args = 0, pretend = 0, frame = 24
+ @ args = 0, pretend = 0, frame = 32
@ frame_needed = 0, uses_anonymous_args = 0
-.L1627:
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+.L1618:
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r8, r3
- ldr r3, .L1651
- mov fp, r2
- .pad #36
- sub sp, sp, #36
- mov r6, r0
- mov r10, #0
- ldrb r5, [r3, #2312] @ zero_extendqisi2
- ldrb r3, [r3, #144] @ zero_extendqisi2
- str r1, [sp, #20]
+ mov r7, r3
+ ldr r3, .L1642
+ mov r10, r2
+ .pad #44
+ sub sp, sp, #44
+ mov r5, r0
+ ldr fp, .L1642
+ ldrb r2, [r3, #2316] @ zero_extendqisi2
+ ldrb r3, [r3, #152] @ zero_extendqisi2
+ str r1, [sp, #28]
cmp r3, #0
- addeq r5, r5, r5, asl #1
- ldrne r2, .L1651+4
- ubfxeq r5, r5, #2, #8
- smullne r2, r3, r5, r2
- uxtbne r5, r3
- ldr r3, .L1651
- add r3, r3, r0, asl #3
- str r3, [sp, #24]
-.L1637:
- mov r0, r6
+ ldrne r3, .L1642+4
+ addeq r2, r2, r2, lsl #1
+ asreq r3, r2, #2
+ smullne r2, r3, r2, r3
+ str r3, [sp, #12]
+ mov r3, #0
+ str r3, [sp, #16]
+ add r3, fp, r0, lsl #3
+ str r3, [sp, #36]
+.L1628:
+ mov r0, r5
mov r9, #0
bl NandcWaitFlashReady
+ ldr r3, [fp, r5, lsl #3]
mvn r4, #0
- ldr r3, [sp, #24]
- ldr r3, [r3, #12]
- str r3, [sp, #12]
- ldr r3, [sp, #24]
- ldrb r3, [r3, #16] @ zero_extendqisi2
- str r3, [sp, #16]
- ldr r2, [sp, #16]
- ldr r3, [sp, #12]
- add r7, r3, r2, asl #8
-.L1628:
- ldr r3, .L1651+8
- ldrb r3, [r3, #1713] @ zero_extendqisi2
+ str r3, [sp, #20]
+ ldr r3, [sp, #36]
+ ldrb r3, [r3, #4] @ zero_extendqisi2
+ str r3, [sp, #24]
+ ldr r2, [sp, #24]
+ ldr r3, [sp, #20]
+ add r6, r3, r2, lsl #8
+.L1619:
+ ldr r3, .L1642+8
+ ldrb r3, [r3, #1721] @ zero_extendqisi2
cmp r9, r3
- bcs .L1631
+ bcc .L1623
+.L1622:
+ ldr r3, [sp, #20]
+ mov r0, #200
+ ldr r2, [sp, #24]
+ add r6, r3, r2, lsl #8
+ mov r3, #239
+ str r3, [r6, #2056]
+ mov r3, #137
+ str r3, [r6, #2052]
+ bl ndelay
+ mov r3, #0
+ str r3, [r6, #2048]
+ str r3, [r6, #2048]
+ str r3, [r6, #2048]
+ str r3, [r6, #2048]
+ ldr r3, [sp, #12]
+ cmp r4, r3
+ bcc .L1624
+ cmn r4, #1
+ movne r4, #256
+.L1624:
+ cmn r4, #1
+ movne r6, #0
+ moveq r6, #1
+ cmp r4, #256
+ movne r1, r6
+ orreq r1, r6, #1
+ cmp r1, #0
+ beq .L1625
+ mov r3, r9
+ str r4, [sp]
+ ldr r2, [sp, #28]
+ mov r1, r9
+ ldr r0, .L1642+12
+ bl printk
+ ldr r3, [sp, #16]
+ cmp r3, #0
+ bne .L1626
+ ldrb r3, [fp, #152] @ zero_extendqisi2
+ cmp r3, #0
+ moveq r6, #0
+ andne r6, r6, #1
+ cmp r6, #0
+ beq .L1616
+ mov r1, #3
+ mov r0, r5
+ bl micron_auto_read_calibration_config
+ mov r3, #1
+ str r3, [sp, #16]
+ b .L1628
+.L1623:
mov r3, #239
mov r0, #200
- str r3, [r7, #2056]
+ str r3, [r6, #2056]
mov r3, #137
- str r3, [r7, #2052]
- bl NandcDelayns
- mov ip, #0
+ str r3, [r6, #2052]
+ mov r8, #0
+ bl ndelay
add r3, r9, #1
- mov r0, r6
- str r3, [r7, #2048]
- mov r2, fp
- str ip, [r7, #2048]
- str ip, [r7, #2048]
- str ip, [r7, #2048]
- str r3, [sp, #8]
- mov r3, r8
- ldr r1, [sp, #20]
- str ip, [sp, #28]
+ mov r2, r10
+ str r3, [r6, #2048]
+ mov r0, r5
+ str r8, [r6, #2048]
+ str r3, [sp, #32]
+ mov r3, r7
+ str r8, [r6, #2048]
+ ldr r1, [sp, #28]
+ str r8, [r6, #2048]
bl FlashReadRawPage
cmn r0, #1
- beq .L1629
- cmn r4, #1
- ldr ip, [sp, #28]
- moveq r4, r0
- cmp r0, r5
- bcc .L1639
- mov r8, ip
- mov fp, ip
-.L1629:
- ldr r9, [sp, #8]
- b .L1628
-.L1639:
- mov r4, r0
- mov r8, ip
- mov fp, ip
-.L1631:
- ldr r2, [sp, #16]
- mov r0, #200
+ beq .L1620
ldr r3, [sp, #12]
- add r7, r3, r2, asl #8
- mov r3, #239
- str r3, [r7, #2056]
- mov r3, #137
- str r3, [r7, #2052]
- bl NandcDelayns
- cmp r4, r5
- mov r3, #0
- str r3, [r7, #2048]
- str r3, [r7, #2048]
- str r3, [r7, #2048]
- str r3, [r7, #2048]
- bcc .L1633
cmn r4, #1
- movne r4, #256
-.L1633:
- cmn r4, #1
- movne r7, #0
- moveq r7, #1
- cmp r4, #256
- movne r1, r7
- orreq r1, r7, #1
- cmp r1, #0
- beq .L1634
- str r4, [sp]
- mov r1, r9
- ldr r0, .L1651+12
- mov r3, r9
- ldr r2, [sp, #20]
- bl printk
- cmp r10, #0
- bne .L1635
- ldr r3, .L1651
- ldrb r3, [r3, #144] @ zero_extendqisi2
- cmp r3, #0
- moveq r7, #0
- andne r7, r7, #1
- cmp r7, #0
- beq .L1644
- mov r0, r6
- mov r1, #3
- bl micron_auto_read_calibration_config
- mov r10, #1
- b .L1637
-.L1635:
- mov r0, r6
+ moveq r4, r0
+ cmp r0, r3
+ bcc .L1630
+ mov r7, r8
+ mov r10, r8
+.L1620:
+ ldr r9, [sp, #32]
+ b .L1619
+.L1630:
+ mov r4, r0
+ mov r7, r8
+ mov r10, r8
+ b .L1622
+.L1626:
mov r1, #0
+ mov r0, r5
bl micron_auto_read_calibration_config
cmn r4, #1
movne r4, #256
- b .L1644
-.L1634:
- cmp r10, #0
- beq .L1644
- mov r0, r6
+.L1616:
+ mov r0, r4
+ add sp, sp, #44
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1625:
+ ldr r3, [sp, #16]
+ cmp r3, #0
+ beq .L1616
+ mov r0, r5
mov r4, #256
bl micron_auto_read_calibration_config
-.L1644:
- mov r0, r4
- add sp, sp, #36
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1652:
+ b .L1616
+.L1643:
.align 2
-.L1651:
+.L1642:
.word .LANCHOR0
.word 1431655766
.word .LANCHOR2
@@ -9729,296 +10231,299 @@
.size MicronReadRetrial, .-MicronReadRetrial
.align 2
.global HynixReadRetrial
+ .syntax unified
+ .arm
+ .fpu softvfp
.type HynixReadRetrial, %function
HynixReadRetrial:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- mov r8, r3
- ldr r5, .L1671
- mov r10, r2
- mov r7, r0
- mov fp, r1
- add r2, r5, r0
+ mov r9, r3
+ ldr r5, .L1662
+ mov r8, #0
mvn r6, #0
- ldr r3, [r5, #44]
- ldrb r4, [r2, #1222] @ zero_extendqisi2
- ldrb r9, [r5, #1212] @ zero_extendqisi2
+ mov fp, r2
+ mov r7, r0
+ str r1, [sp, #4]
+ ldr r3, [r5, #48]
+ add r2, r5, r0
+ ldrb r4, [r2, #1228] @ zero_extendqisi2
+ ldrb r10, [r5, #1218] @ zero_extendqisi2
ldrb r3, [r3, #19] @ zero_extendqisi2
sub r3, r3, #7
cmp r3, #1
- ldrlsb r4, [r2, #1230] @ zero_extendqisi2
+ ldrbls r4, [r2, #1236] @ zero_extendqisi2
bl NandcWaitFlashReady
- mov ip, #0
-.L1655:
- cmp ip, r9
- bcs .L1659
- add r4, r4, #1
- mov r0, r7
- ldrb r1, [r5, #1211] @ zero_extendqisi2
- uxtb r4, r4
- ldr r2, .L1671+4
- cmp r4, r9
- str ip, [sp, #4]
- movcs r4, #0
- mov r3, r4
- bl HynixSetRRPara
- mov r0, r7
- mov r1, fp
- mov r2, r10
- mov r3, r8
- bl FlashReadRawPage
- cmn r0, #1
- ldr ip, [sp, #4]
- beq .L1657
- ldrb r3, [r5, #2312] @ zero_extendqisi2
- cmn r6, #1
- moveq r6, r0
- add r3, r3, r3, asl #1
- cmp r0, r3, asr #2
- bcc .L1664
- mov r8, #0
- mov r10, r8
-.L1657:
- add ip, ip, #1
- b .L1655
-.L1664:
- mov r6, r0
-.L1659:
- ldr r3, [r5, #44]
+.L1646:
+ cmp r8, r10
+ bcc .L1651
+.L1650:
+ ldr r3, [r5, #48]
add r7, r5, r7
ldrb r3, [r3, #19] @ zero_extendqisi2
sub r3, r3, #7
cmp r3, #1
- ldrb r3, [r5, #2312] @ zero_extendqisi2
- strlsb r4, [r7, #1230]
- strhib r4, [r7, #1222]
- add r3, r3, r3, asl #1
+ ldrb r3, [r5, #2316] @ zero_extendqisi2
+ strbls r4, [r7, #1236]
+ strbhi r4, [r7, #1228]
+ add r3, r3, r3, lsl #1
cmp r6, r3, asr #2
- bcc .L1663
+ bcc .L1644
cmn r6, #1
movne r6, #256
-.L1663:
+.L1644:
mov r0, r6
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1672:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1651:
+ add r4, r4, #1
+ ldr r2, .L1662+4
+ uxtb r4, r4
+ ldrb r1, [r5, #1217] @ zero_extendqisi2
+ mov r0, r7
+ cmp r10, r4
+ movls r4, #0
+ mov r3, r4
+ bl HynixSetRRPara
+ mov r3, r9
+ mov r2, fp
+ ldr r1, [sp, #4]
+ mov r0, r7
+ bl FlashReadRawPage
+ cmn r0, #1
+ beq .L1648
+ ldrb r3, [r5, #2316] @ zero_extendqisi2
+ cmn r6, #1
+ moveq r6, r0
+ add r3, r3, r3, lsl #1
+ cmp r0, r3, asr #2
+ bcc .L1655
+ mov r9, #0
+ mov fp, r9
+.L1648:
+ add r8, r8, #1
+ b .L1646
+.L1655:
+ mov r6, r0
+ b .L1650
+.L1663:
.align 2
-.L1671:
+.L1662:
.word .LANCHOR0
- .word .LANCHOR0+1214
+ .word .LANCHOR0+1220
.fnend
.size HynixReadRetrial, .-HynixReadRetrial
.align 2
+ .syntax unified
+ .arm
+ .fpu softvfp
.type samsung_read_retrial, %function
samsung_read_retrial:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #28
sub sp, sp, #28
mov r10, r0
mov fp, r2
- mov r8, r3
- str r1, [sp, #12]
+ mov r9, r3
+ str r1, [sp, #16]
bl NandcWaitFlashReady
- ldr r3, .L1703
- add r2, r3, r10, asl #3
- ldr r4, [r2, #12]
- ldrb r2, [r2, #16] @ zero_extendqisi2
- str r2, [sp, #8]
- ldrb r2, [r3, #2228] @ zero_extendqisi2
- str r3, [sp, #16]
+ ldr r3, .L1694
+ ldr r2, [r3, r10, lsl #3]
+ str r3, [sp, #20]
+ str r2, [sp, #12]
+ add r2, r3, r10, lsl #3
+ ldrb r6, [r2, #4] @ zero_extendqisi2
+ ldrb r2, [r3, #2232] @ zero_extendqisi2
cmp r2, #0
- bne .L1674
- ldr r3, [sp, #8]
- mvn r5, #0
- mov r6, #1
- mov r9, r3, asl #8
- add r7, r4, r9
-.L1678:
+ bne .L1665
+ ldr r3, [sp, #12]
+ lsl r8, r6, #8
+ mvn r4, #0
+ mov r7, #1
+ add r5, r3, r8
+.L1669:
mov r3, #239
- str r3, [r7, #2056]
+ mov r6, #0
+ str r3, [r5, #2056]
mov r3, #141
- str r3, [r7, #2052]
- ldr r3, .L1703+4
- mov ip, #0
- mov r0, r10
- ldr r1, [sp, #12]
+ str r3, [r5, #2052]
mov r2, fp
- str ip, [sp, #20]
- ldrsb r3, [r6, r3]
- str r3, [r7, #2048]
- mov r3, r8
- str ip, [r7, #2048]
- str ip, [r7, #2048]
- str ip, [r7, #2048]
+ ldr r3, .L1694+4
+ mov r0, r10
+ ldr r1, [sp, #16]
+ ldrsb r3, [r7, r3]
+ str r3, [r5, #2048]
+ mov r3, r9
+ str r6, [r5, #2048]
+ str r6, [r5, #2048]
+ str r6, [r5, #2048]
bl FlashReadRawPage
cmn r0, #1
- beq .L1675
- ldr r3, [sp, #16]
- cmn r5, #1
- moveq r5, r0
- ldrb r3, [r3, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
+ beq .L1666
+ ldr r3, [sp, #20]
+ cmn r4, #1
+ moveq r4, r0
+ ldrb r3, [r3, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
cmp r0, r3, asr #2
- bcc .L1686
- ldr ip, [sp, #20]
- mov r8, ip
- mov fp, ip
-.L1675:
- add r6, r6, #1
- cmp r6, #26
- bne .L1678
- b .L1677
-.L1686:
- mov r5, r0
-.L1677:
- add r9, r4, r9
+ bcc .L1677
+ mov r9, r6
+ mov fp, r6
+.L1666:
+ add r7, r7, #1
+ cmp r7, #26
+ bne .L1669
+.L1668:
+ ldr r3, [sp, #12]
+ add r8, r3, r8
mov r3, #239
- str r3, [r9, #2056]
- ldr r3, [sp, #8]
- add r4, r4, r3, asl #8
+ str r3, [r8, #2056]
mov r3, #141
- b .L1702
-.L1674:
- ldr r3, [sp, #8]
- mvn r5, #0
- ldr r7, .L1703+8
- mov r6, #1
- mov ip, r3, asl #8
- add r9, r4, ip
-.L1683:
- mov r3, #239
- str r3, [r9, #2056]
- mov r3, #137
- str r3, [r9, #2052]
- ldrb r3, [r7, #4] @ zero_extendqisi2
- mov r0, r10
- ldr r1, [sp, #12]
- mov r2, fp
- str ip, [sp, #20]
- str r3, [r9, #2048]
- ldrb r3, [r7, #5] @ zero_extendqisi2
- str r3, [r9, #2048]
- ldrb r3, [r7, #6] @ zero_extendqisi2
- str r3, [r9, #2048]
- ldrb r3, [r7, #7] @ zero_extendqisi2
- str r3, [r9, #2048]
- mov r3, r8
- bl FlashReadRawPage
- cmn r0, #1
- ldr ip, [sp, #20]
- beq .L1680
- ldr r3, [sp, #16]
- cmn r5, #1
- moveq r5, r0
- ldrb r3, [r3, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
- cmp r0, r3, asr #2
- bcc .L1687
- mov r8, #0
- mov fp, r8
-.L1680:
- add r6, r6, #1
- add r7, r7, #4
- cmp r6, #26
- bne .L1683
- b .L1682
-.L1687:
- mov r5, r0
-.L1682:
- add ip, r4, ip
- mov r3, #239
- str r3, [ip, #2056]
- ldr r3, [sp, #8]
- add r4, r4, r3, asl #8
- mov r3, #137
-.L1702:
- str r3, [r4, #2052]
+.L1693:
+ str r3, [r5, #2052]
mov r3, #0
- str r3, [r4, #2048]
- str r3, [r4, #2048]
- str r3, [r4, #2048]
- str r3, [r4, #2048]
- ldr r3, [sp, #16]
- ldrb r3, [r3, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
- cmp r5, r3, asr #2
- bcc .L1684
- cmn r5, #1
- movne r5, #256
-.L1684:
- cmn r5, #1
- cmpne r5, #256
- bne .L1685
- str r5, [sp]
- mov r1, r6
- ldr r0, .L1703+12
- mov r3, r6
- ldr r2, [sp, #12]
+ str r3, [r5, #2048]
+ str r3, [r5, #2048]
+ str r3, [r5, #2048]
+ str r3, [r5, #2048]
+ ldr r3, .L1694
+ ldrb r3, [r3, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
+ cmp r4, r3, asr #2
+ bcc .L1675
+ cmn r4, #1
+ movne r4, #256
+.L1675:
+ cmn r4, #1
+ cmpne r4, #256
+ bne .L1676
+ str r4, [sp]
+ mov r3, r7
+ ldr r2, [sp, #16]
+ mov r1, r7
+ ldr r0, .L1694+8
bl printk
-.L1685:
+.L1676:
mov r0, r10
bl NandcWaitFlashReady
- mov r0, r5
+ mov r0, r4
add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1704:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1677:
+ mov r4, r0
+ b .L1668
+.L1665:
+ ldr r3, [sp, #12]
+ lsl r6, r6, #8
+ ldr r8, .L1694+12
+ mvn r4, #0
+ mov r7, #1
+ add r5, r3, r6
+.L1674:
+ mov r3, #239
+ mov r2, fp
+ str r3, [r5, #2056]
+ mov r3, #137
+ str r3, [r5, #2052]
+ mov r0, r10
+ ldrb r3, [r8, #4] @ zero_extendqisi2
+ ldr r1, [sp, #16]
+ str r3, [r5, #2048]
+ ldrb r3, [r8, #5] @ zero_extendqisi2
+ str r3, [r5, #2048]
+ ldrb r3, [r8, #6] @ zero_extendqisi2
+ str r3, [r5, #2048]
+ ldrb r3, [r8, #7] @ zero_extendqisi2
+ str r3, [r5, #2048]
+ mov r3, r9
+ bl FlashReadRawPage
+ cmn r0, #1
+ beq .L1671
+ ldr r3, .L1694
+ cmn r4, #1
+ moveq r4, r0
+ ldrb r3, [r3, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
+ cmp r0, r3, asr #2
+ bcc .L1678
+ mov r9, #0
+ mov fp, r9
+.L1671:
+ add r7, r7, #1
+ add r8, r8, #4
+ cmp r7, #26
+ bne .L1674
+.L1673:
+ ldr r3, [sp, #12]
+ add r6, r3, r6
+ mov r3, #239
+ str r3, [r6, #2056]
+ mov r3, #137
+ b .L1693
+.L1678:
+ mov r4, r0
+ b .L1673
+.L1695:
.align 2
-.L1703:
+.L1694:
.word .LANCHOR0
- .word .LANCHOR3+16
- .word .LANCHOR3+44
+ .word .LANCHOR3+11
.word .LC95
+ .word .LANCHOR3+37
.fnend
.size samsung_read_retrial, .-samsung_read_retrial
.align 2
.global FlashProgPage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgPage, %function
FlashProgPage:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
+ push {r0, r1, r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
.pad #8
mov r8, r3
- ldr r3, .L1709
+ ldr r3, .L1700
subs r4, r0, #0
mov r5, r1
mov r7, r2
- ldrb r6, [r3, #481] @ zero_extendqisi2
- bne .L1706
- ldr r2, .L1709+4
- ldrb r3, [r2, #1] @ zero_extendqisi2
- ldr r1, [r2, #4]
- mul r1, r1, r3
- cmp r5, r1
- bcs .L1706
- ldrb r3, [r2] @ zero_extendqisi2
+ ldrb r6, [r3, #477] @ zero_extendqisi2
+ bne .L1697
+ ldr r1, .L1700+4
+ ldrb r3, [r1, #37] @ zero_extendqisi2
+ ldr r0, [r1, #40]
+ mul r0, r0, r3
+ cmp r0, r5
+ bls .L1697
+ ldrb r3, [r1, #36] @ zero_extendqisi2
cmp r3, #0
movne r6, #4
-.L1706:
+.L1697:
mov r0, r4
bl NandcWaitFlashReady
mov r0, r4
bl NandcFlashCs
- mov r0, r4
mov r1, r5
- bl FlashProgFirstCmd
- mov r2, r6
- mov r3, r7
mov r0, r4
- mov r1, #1
+ bl FlashProgFirstCmd
+ mov r3, r7
+ mov r2, r6
str r8, [sp]
+ mov r1, #1
+ mov r0, r4
bl NandcXferData
mov r1, r5
mov r0, r4
@@ -10028,287 +10533,288 @@
mov r1, r5
mov r0, r4
bl FlashReadStatus
- mov r5, r0
+ mov r1, r0
mov r0, r4
bl NandcFlashDeCs
- and r0, r5, #1
+ and r0, r1, #1
add sp, sp, #8
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L1710:
+ pop {r4, r5, r6, r7, r8, pc}
+.L1701:
.align 2
-.L1709:
+.L1700:
.word .LANCHOR1
.word .LANCHOR0
.fnend
.size FlashProgPage, .-FlashProgPage
.align 2
.global FlashSavePhyInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashSavePhyInfo, %function
FlashSavePhyInfo:
.fnstart
- @ args = 0, pretend = 0, frame = 8
+ @ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #12
- ldr r4, .L1725
- ldr r5, .L1725+4
- ldr r8, .L1725+8
- ldr r3, [r4, #1688]
- mov fp, r4
- ldrb r0, [r4, #1714] @ zero_extendqisi2
- mov r10, r5
- str r3, [r4, #1700]
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ ldr r4, .L1716
+ ldr r5, .L1716+4
+ ldr r3, [r4, #1696]
+ ldrb r0, [r4, #1722] @ zero_extendqisi2
+ ldr r8, .L1716+8
+ str r3, [r4, #1708]
bl FlashBchSel
- mov r1, #0
mov r2, #2048
- ldr r0, [r4, #1688]
+ mov r1, #0
+ ldr r0, [r4, #1696]
bl ftl_memset
- ldr r3, [r4, #1700]
- ldr r1, .L1725+12
+ ldr r3, [r4, #1708]
mov r2, #32
+ ldr r1, .L1716+12
str r8, [r3]
- ldr r0, [r4, #1700]
- ldrb r3, [r5, #2230] @ zero_extendqisi2
+ ldr r0, [r4, #1708]
+ ldrb r3, [r5, #2234] @ zero_extendqisi2
add r0, r0, #16
strh r3, [r0, #-4] @ movhi
- ldrb r3, [r5, #1] @ zero_extendqisi2
+ ldrb r3, [r5, #37] @ zero_extendqisi2
strh r3, [r0, #-2] @ movhi
- ldrb r3, [r5, #2252] @ zero_extendqisi2
+ ldrb r3, [r5, #2256] @ zero_extendqisi2
str r3, [r0, #1060]
bl ftl_memcpy
- ldr r0, [r4, #1700]
- ldr r1, .L1725+16
+ ldr r0, [r4, #1708]
mov r2, #8
+ ldr r1, .L1716+16
add r0, r0, #80
bl ftl_memcpy
- ldr r0, [r4, #1700]
- ldr r1, .L1725+20
+ ldr r0, [r4, #1708]
mov r2, #32
+ ldr r1, .L1716+20
add r0, r0, #96
bl ftl_memcpy
- ldr r0, [r4, #1700]
- ldr r1, .L1725+24
+ ldr r0, [r4, #1708]
mov r2, #32
+ ldr r1, .L1716+24
add r0, r0, #160
bl ftl_memcpy
- ldr r0, [r4, #1700]
- add r1, r5, #48
+ ldr r0, [r4, #1708]
mov r2, #32
+ add r1, r5, #52
add r0, r0, #192
bl ftl_memcpy
- ldr r0, [r4, #1700]
+ ldr r0, [r4, #1708]
mov r2, #852
- ldr r1, .L1725+28
+ add r1, r5, #1216
add r0, r0, #224
bl ftl_memcpy
- ldr r6, [r4, #1700]
+ ldr r6, [r4, #1708]
movw r1, #2036
add r0, r6, #12
bl js_hash
movw r3, #1592
- str r3, [r6, #4]
- ldr r3, [r4, #1716]
- str r3, [r4, #1700]
str r0, [r6, #8]
- mov r0, #0
- bl flash_enter_slc_mode
+ str r3, [r6, #4]
mov r6, #0
+ ldr r3, [r4, #1724]
mov r7, r6
-.L1717:
- ldr r1, [r5, #4]
mov r0, #0
- mov r2, r0
+ str r3, [r4, #1708]
+ bl flash_enter_slc_mode
+.L1708:
+ ldr r1, [r5, #40]
+ mov r2, #0
+ mov r0, r2
mul r1, r1, r7
bl FlashEraseBlock
- ldrb r9, [r5, #144] @ zero_extendqisi2
+ ldrb r9, [r5, #152] @ zero_extendqisi2
cmp r9, #0
- beq .L1712
+ beq .L1703
mov r9, #0
-.L1713:
- ldr r1, [r5, #4]
- mov r0, #0
- ldr r2, [r4, #1688]
- mov r3, r0
+.L1704:
+ ldr r1, [r5, #40]
+ mov r3, #0
+ ldr r2, [r4, #1696]
+ mov r0, r3
mla r1, r1, r7, r9
add r9, r9, #1
bl FlashProgPage
cmp r9, #10
- bne .L1713
- b .L1714
-.L1712:
- ldr r1, [r10, #4]
- mov r3, r9
- ldr r2, [r4, #1688]
- mov r0, r9
- mul r1, r1, r7
- bl FlashProgPage
- ldr r1, [r10, #4]
- mov r0, r9
- ldr r2, [r4, #1688]
- mov r3, r9
- mul r1, r1, r7
- add r1, r1, #1
- bl FlashProgPage
-.L1714:
- ldr r1, [r5, #4]
- mov r0, #0
- ldr r2, [r4, #1716]
- mov r3, r0
+ bne .L1704
+.L1705:
+ ldr r1, [r5, #40]
+ mov r3, #0
+ ldr r2, [r4, #1724]
+ mov r0, r3
+ add r10, r7, #1
mul r1, r1, r7
bl FlashReadRawPage
- add r2, r7, #1
cmn r0, #1
- beq .L1715
- ldr r9, [fp, #1700]
+ beq .L1706
+ ldr r9, [r4, #1708]
ldr r3, [r9]
cmp r3, r8
- bne .L1715
- add r0, r9, #12
+ bne .L1706
movw r1, #2036
- str r2, [sp, #4]
+ add r0, r9, #12
bl js_hash
ldr r3, [r9, #8]
cmp r3, r0
- ldr r2, [sp, #4]
- bne .L1715
- ldr r3, [r10, #4]
+ bne .L1706
+ ldr r3, [r5, #40]
cmp r6, #1
- str r2, [fp, #1708]
- mul r7, r3, r7
- str r7, [fp, #1704]
- beq .L1718
+ str r10, [r4, #1716]
+ mul r7, r7, r3
+ str r7, [r4, #1712]
+ beq .L1709
mov r6, #1
-.L1715:
- cmp r2, #4
- mov r7, r2
- bne .L1717
- b .L1716
-.L1718:
- mov r6, #2
-.L1716:
+.L1706:
+ cmp r10, #4
+ mov r7, r10
+ bne .L1708
+.L1707:
mov r0, #0
bl flash_exit_slc_mode
clz r0, r6
- mov r0, r0, lsr #5
+ lsr r0, r0, #5
rsb r0, r0, #0
- add sp, sp, #12
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1726:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1703:
+ ldr r1, [r5, #40]
+ mov r3, r9
+ ldr r2, [r4, #1696]
+ mov r0, r9
+ mul r1, r1, r7
+ bl FlashProgPage
+ ldr r1, [r5, #40]
+ mov r3, r9
+ ldr r2, [r4, #1696]
+ mov r0, r9
+ mul r1, r1, r7
+ add r1, r1, #1
+ bl FlashProgPage
+ b .L1705
+.L1709:
+ mov r6, #2
+ b .L1707
+.L1717:
.align 2
-.L1725:
+.L1716:
.word .LANCHOR2
.word .LANCHOR0
.word 1312902724
- .word .LANCHOR0+2068
- .word .LANCHOR0+2232
- .word .LANCHOR0+1172
- .word .LANCHOR1+472
- .word .LANCHOR0+1210
+ .word .LANCHOR0+2072
+ .word .LANCHOR0+2236
+ .word .LANCHOR0+1180
+ .word .LANCHOR1+468
.fnend
.size FlashSavePhyInfo, .-FlashSavePhyInfo
.align 2
.global FlashReadIdbDataRaw
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadIdbDataRaw, %function
FlashReadIdbDataRaw:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r9, r0
- ldr r3, .L1747
+ mov r3, #60
.pad #20
sub sp, sp, #20
- ldr r4, .L1747+4
- ldr r0, [r3] @ unaligned
- ldr r3, [r4, #2248]
- ldrb r10, [r4, #2312] @ zero_extendqisi2
+ ldr r4, .L1737
+ mov r10, r0
+ strb r3, [sp, #12]
+ mov r3, #40
+ strb r3, [sp, #13]
+ mov r3, #24
+ strb r3, [sp, #14]
+ mov r3, #16
+ strb r3, [sp, #15]
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
+ str r3, [sp, #4]
+ ldr r3, [r4, #2252]
cmp r3, #0
- str r0, [sp, #12] @ unaligned
- beq .L1728
+ beq .L1719
mov r0, #0
bl flash_enter_slc_mode
-.L1728:
- mov r0, r9
- mov r1, #0
- mov r2, #2048
+.L1719:
+ ldr r6, .L1737+4
mvn r8, #0
- bl ftl_memset
mov r5, #2
-.L1729:
- ldrb r3, [r4, #1] @ zero_extendqisi2
- cmp r5, r3
- bcs .L1733
- ldr fp, .L1747+8
- mov r7, #0
-.L1731:
- add r3, sp, #12
- ldr r6, .L1747+8
- ldrb ip, [r7, r3] @ zero_extendqisi2
- mov r0, ip
- str ip, [sp, #4]
- bl FlashBchSel
- ldr r1, [r4, #4]
- mov r0, #0
- ldr r2, [fp, #1688]
- mov r3, r0
- mul r1, r1, r5
- bl FlashReadRawPage
- cmn r0, #1
- ldr ip, [sp, #4]
- bne .L1730
- add r7, r7, #1
- cmp r7, #4
- bne .L1731
- b .L1732
-.L1730:
- ldr r3, [r6, #1688]
- ldr r2, .L1747+12
- ldr r3, [r3]
- cmp r3, r2
- bne .L1732
- mov r1, ip
- ldr r0, .L1747+16
- bl printk
mov r2, #2048
- mov r0, r9
- ldr r1, [r6, #1688]
- bl ftl_memcpy
- ldr r3, [r6, #1688]
- ldr r2, .L1747+4
- ldr r3, [r3, #512]
- strb r3, [r2, #1]
- ldr r3, [r6, #1708]
- cmp r3, r5
- bls .L1736
- str r5, [r6, #1708]
- bl FlashSavePhyInfo
- mov r8, #0
-.L1732:
- add r5, r5, #1
- b .L1729
-.L1736:
- mov r8, #0
-.L1733:
+ mov r1, #0
mov r0, r10
+ bl ftl_memset
+.L1720:
+ ldrb r3, [r4, #37] @ zero_extendqisi2
+ cmp r5, r3
+ bcc .L1725
+.L1724:
+ ldr r0, [sp, #4]
bl FlashBchSel
- ldr r3, [r4, #2248]
+ ldr r3, [r4, #2252]
cmp r3, #0
- beq .L1740
+ beq .L1718
mov r0, #0
bl flash_exit_slc_mode
-.L1740:
+.L1718:
mov r0, r8
add sp, sp, #20
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1748:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1725:
+ mov r7, #0
+ add fp, sp, #12
+.L1722:
+ ldrb r9, [r7, fp] @ zero_extendqisi2
+ mov r0, r9
+ bl FlashBchSel
+ ldr r1, [r4, #40]
+ mov r3, #0
+ ldr r2, [r6, #1696]
+ mov r0, r3
+ mul r1, r1, r5
+ bl FlashReadRawPage
+ cmn r0, #1
+ bne .L1721
+ add r7, r7, #1
+ cmp r7, #4
+ bne .L1722
+.L1723:
+ add r5, r5, #1
+ b .L1720
+.L1728:
+ mov r8, #0
+ b .L1724
+.L1721:
+ ldr r3, [r6, #1696]
+ ldr r2, .L1737+8
+ ldr r3, [r3]
+ cmp r3, r2
+ bne .L1723
+ mov r1, r9
+ ldr r0, .L1737+12
+ bl printk
+ mov r2, #2048
+ ldr r1, [r6, #1696]
+ mov r0, r10
+ bl ftl_memcpy
+ ldr r3, [r6, #1696]
+ ldr r3, [r3, #512]
+ strb r3, [r4, #37]
+ ldr r3, [r6, #1716]
+ cmp r5, r3
+ bcs .L1728
+ str r5, [r6, #1716]
+ mov r8, #0
+ bl FlashSavePhyInfo
+ b .L1723
+.L1738:
.align 2
-.L1747:
- .word .LANCHOR3+11
+.L1737:
.word .LANCHOR0
.word .LANCHOR2
.word -52655045
@@ -10317,846 +10823,823 @@
.size FlashReadIdbDataRaw, .-FlashReadIdbDataRaw
.align 2
.global FlashInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashInit, %function
FlashInit:
.fnstart
- @ args = 0, pretend = 0, frame = 0
+ @ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r5, r0
- .pad #20
- sub sp, sp, #20
+ mov r7, r0
+ ldr r5, .L1837
+ .pad #28
+ sub sp, sp, #28
+ mov r0, #32768
+ mov r6, #0
+ bl ftl_malloc
+ str r0, [r5, #1696]
mov r0, #32768
bl ftl_malloc
- ldr r8, .L1848
- ldr r4, .L1848+4
- mov r7, #0
- add r9, r4, #12
- str r0, [r8, #1688]
- mov r0, #32768
- bl ftl_malloc
- str r0, [r8, #1716]
+ str r0, [r5, #1724]
mov r0, #4096
- bl ftl_malloc
- str r0, [r8, #1720]
+ bl ftl_dma32_malloc
+ str r0, [r5, #1728]
mov r0, #32768
bl ftl_malloc
- str r0, [r8, #1724]
+ ldr r4, .L1837+4
+ mov r8, r6
+ str r0, [r5, #1732]
mov r0, #4096
- bl ftl_malloc
+ bl ftl_dma32_malloc
+ ldr fp, .L1837+8
mov r3, #50
- str r7, [r8, #1708]
- strb r3, [r4, #1]
- strb r3, [r8, #1712]
+ str r0, [r5, #1736]
+ mov r0, r7
+ ldr r7, .L1837+12
+ strb r3, [r4, #37]
+ strb r3, [r5, #1720]
mov r3, #128
- strb r7, [r4, #2252]
- str r3, [r4, #4]
+ str r3, [r4, #40]
mov r3, #60
- str r7, [r8, #1692]
- strb r7, [r4]
- strb r7, [r8, #1732]
- strb r3, [r8, #1714]
- str r0, [r8, #1728]
- mov r0, r5
+ str r6, [r5, #1716]
+ strb r6, [r4, #2256]
+ str r6, [r5, #1700]
+ strb r6, [r4, #36]
+ strb r6, [r5, #1740]
+ strb r3, [r5, #1722]
bl NandcInit
- ldr r5, .L1848+8
-.L1755:
- add r3, r9, r7, asl #3
- uxtb fp, r7
- ldr r6, [r9, r7, asl #3]
- ldrb r10, [r3, #4] @ zero_extendqisi2
- mov r0, fp
+.L1745:
+ add r2, r4, r6, lsl #3
+ uxtb r9, r6
+ ldr r10, [r4, r6, lsl #3]
+ ldrb r2, [r2, #4] @ zero_extendqisi2
+ mov r0, r9
+ str r2, [sp, #20]
bl FlashReset
- mov r0, fp
+ mov r0, r9
bl NandcFlashCs
+ ldr r2, [sp, #20]
mov r3, #144
- add r6, r6, r10, asl #8
mov r0, #200
- mov r10, #0
- str r3, [r6, #2056]
- str r10, [r6, #2052]
- bl NandcDelayns
- ldr r2, [r6, #2048]
+ add r10, r10, r2, lsl #8
+ str r3, [r10, #2056]
+ str r8, [r10, #2052]
+ bl ndelay
+ ldr r2, [r10, #2048]
uxtb r2, r2
- strb r2, [r5]
- ldr r1, [r6, #2048]
+ strb r2, [r7]
cmp r2, #44
- strb r1, [r5, #1]
- ldr r1, [r6, #2048]
- strb r1, [r5, #2]
- ldr r1, [r6, #2048]
- strb r1, [r5, #3]
- ldr r1, [r6, #2048]
- strb r1, [r5, #4]
- ldr r1, [r6, #2048]
- strb r1, [r5, #5]
- bne .L1750
+ ldr r1, [r10, #2048]
+ strb r1, [r7, #1]
+ ldr r1, [r10, #2048]
+ strb r1, [r7, #2]
+ ldr r1, [r10, #2048]
+ strb r1, [r7, #3]
+ ldr r1, [r10, #2048]
+ strb r1, [r7, #4]
+ ldr r1, [r10, #2048]
+ strb r1, [r7, #5]
+ bne .L1740
mov r2, #239
mov r0, #200
- str r2, [r6, #2056]
+ str r2, [r10, #2056]
mov r2, #1
- str r2, [r6, #2052]
- bl NandcDelayns
+ str r2, [r10, #2052]
+ bl ndelay
mov r2, #4
- str r2, [r6, #2048]
- str r10, [r6, #2048]
- str r10, [r6, #2048]
- str r10, [r6, #2048]
-.L1750:
- mov r0, fp
+ str r2, [r10, #2048]
+ str r8, [r10, #2048]
+ str r8, [r10, #2048]
+ str r8, [r10, #2048]
+.L1740:
+ mov r0, r9
bl NandcFlashDeCs
- ldrb r2, [r5] @ zero_extendqisi2
+ ldrb r2, [r7] @ zero_extendqisi2
sub r3, r2, #1
uxtb r3, r3
cmp r3, #253
- bhi .L1751
- ldrb r1, [r5, #2] @ zero_extendqisi2
- ldrb r3, [r5, #1] @ zero_extendqisi2
- ldr r0, .L1848+12
- str r1, [sp]
- ldrb r1, [r5, #3] @ zero_extendqisi2
- str r1, [sp, #4]
- ldrb r1, [r5, #4] @ zero_extendqisi2
- str r1, [sp, #8]
- ldrb r1, [r5, #5] @ zero_extendqisi2
+ bhi .L1741
+ ldrb r1, [r7, #5] @ zero_extendqisi2
+ mov r0, fp
+ ldrb r3, [r7, #1] @ zero_extendqisi2
str r1, [sp, #12]
- add r1, r7, #1
+ ldrb r1, [r7, #4] @ zero_extendqisi2
+ str r1, [sp, #8]
+ ldrb r1, [r7, #3] @ zero_extendqisi2
+ str r1, [sp, #4]
+ ldrb r1, [r7, #2] @ zero_extendqisi2
+ str r1, [sp]
+ add r1, r6, #1
bl printk
-.L1751:
- cmp r7, #0
- bne .L1752
- ldrb r3, [r4, #2068] @ zero_extendqisi2
+.L1741:
+ cmp r6, #0
+ bne .L1742
+ ldrb r3, [r4, #2072] @ zero_extendqisi2
sub r3, r3, #1
uxtb r3, r3
cmp r3, #253
- bhi .L1802
- ldr r3, .L1848+4
- ldrb r3, [r3, #2069] @ zero_extendqisi2
+ bhi .L1792
+ ldrb r3, [r4, #2073] @ zero_extendqisi2
cmp r3, #255
- beq .L1802
-.L1752:
- ldrb r3, [r5] @ zero_extendqisi2
- add r7, r7, #1
- add r5, r5, #8
+ beq .L1792
+.L1742:
+ ldrb r3, [r7] @ zero_extendqisi2
+ add r6, r6, #1
+ add r7, r7, #8
cmp r3, #181
moveq r3, #44
- streqb r3, [r5, #-8]
- cmp r7, #4
- bne .L1755
- ldrb r3, [r4, #2068] @ zero_extendqisi2
+ strbeq r3, [r7, #-8]
+ cmp r6, #4
+ bne .L1745
+ ldrb r3, [r4, #2072] @ zero_extendqisi2
cmp r3, #173
- beq .L1756
- ldr r3, .L1848+4
- ldr r0, [r3, #2256]
+ beq .L1746
+ ldr r0, [r4, #2260]
bl NandcSetDdrMode
-.L1756:
+.L1746:
mov r2, #852
- ldr r0, .L1848+16
mov r1, #0
- ldr r5, .L1848+20
+ ldr r0, .L1837+16
bl ftl_memset
- ldr r2, [r4, #2264]
- ldr r0, .L1848+24
- cmp r2, r5
- add r3, r0, #472
- str r3, [r4, #44]
+ ldr r6, .L1837+20
+ ldr r2, .L1837+24
+ ldr r0, [r4, #2268]
+ add r3, r2, #468
+ cmp r0, r6
+ str r3, [r4, #48]
mov r3, #0
- strb r3, [r4, #8]
- bne .L1757
- ldrb r3, [r0, #491] @ zero_extendqisi2
+ strb r3, [r4, #44]
+ bne .L1747
+ ldrb r3, [r2, #487] @ zero_extendqisi2
cmp r3, #50
- ldrne r3, .L1848+4
- movne r1, #1
- strne r1, [r3, #2248]
-.L1757:
- ldrb r6, [r4, #2069] @ zero_extendqisi2
- sub ip, r6, #218
- cmp r6, #161
- cmpne r6, #241
- clz ip, ip
- and r1, r6, #253
- moveq r3, #1
- movne r3, #0
- mov ip, ip, lsr #5
- orr r3, ip, r3
- cmp r1, #209
- orreq r3, r3, #1
- cmp r3, #0
- bne .L1758
- cmp r6, #220
- bne .L1759
- ldr r3, .L1848+4
- ldrb r3, [r3, #2071] @ zero_extendqisi2
- cmp r3, #149
- bne .L1759
-.L1758:
- mov lr, #16
- strb lr, [r4, #1]
- strb lr, [r8, #1714]
+ movne r3, #1
+ strne r3, [r4, #2252]
+.L1747:
+ ldrb r3, [r4, #2073] @ zero_extendqisi2
+ cmp r3, #241
+ cmpne r3, #161
+ and ip, r3, #253
+ moveq r1, #1
+ movne r1, #0
+ cmp r3, #218
+ orreq r1, r1, #1
+ cmp ip, #209
+ orreq r1, r1, #1
+ cmp r1, #0
+ bne .L1748
+ cmp r3, #220
+ bne .L1749
+ ldrb r1, [r4, #2075] @ zero_extendqisi2
+ cmp r1, #149
+ bne .L1749
+.L1748:
+ mov ip, #16
mov r1, #1
- ldrb lr, [r4, #2068] @ zero_extendqisi2
- strb r1, [r4]
- cmp lr, #152
- ldr r3, .L1848
- strb lr, [r0, #3417]
- strb r6, [r0, #3418]
- bne .L1761
- ldr r7, .L1848+4
- movw lr, #2072
- ldrsb lr, [r7, lr]
- cmp lr, #0
- strltb r1, [r3, #1732]
- movge r1, #24
- strgeb r1, [r3, #1714]
-.L1761:
- movw r3, #2049
- cmp r2, r5
- cmpne r2, r3
- moveq r3, #16
- streqb r3, [r8, #1714]
- cmp ip, #0
- ldrne r3, .L1848+28
- movne r2, #2048
- strneh r2, [r3, #14] @ movhi
- mvnne r3, #37
- bne .L1842
-.L1765:
- cmp r6, #220
- bne .L1767
- ldr r3, .L1848+28
- mov r2, #4096
- strh r2, [r3, #14] @ movhi
- mvn r3, #35
-.L1842:
- strb r3, [r0, #3418]
- b .L1766
-.L1767:
- cmp r6, #211
- ldreq r3, .L1848+28
- moveq r2, #4096
- streqh r2, [r3, #14] @ movhi
- moveq r3, #2
- streqb r3, [r0, #3429]
-.L1766:
- ldr r1, .L1848+32
+ strb ip, [r4, #37]
+ strb ip, [r5, #1722]
+ ldrb ip, [r4, #2072] @ zero_extendqisi2
+ strb r1, [r4, #36]
+ strb r3, [r2, #3414]
+ cmp ip, #152
+ strb ip, [r2, #3413]
+ bne .L1751
+ ldrb ip, [r4, #2076] @ zero_extendqisi2
+ lsrs ip, ip, #7
+ moveq r1, #24
+ strbne r1, [r5, #1740]
+ strbeq r1, [r5, #1722]
+.L1751:
+ movw r1, #2049
+ cmp r0, r1
+ cmpne r0, r6
+ moveq r1, #16
+ strbeq r1, [r5, #1722]
+ cmp r3, #218
+ bne .L1755
+ ldr r3, .L1837+28
+ mov r1, #2048
+ strh r1, [r3, #14] @ movhi
+ mvn r3, #37
+.L1831:
+ strb r3, [r2, #3414]
+.L1756:
mov r2, #32
- ldr r0, .L1848+36
+ ldr r1, .L1837+32
+ ldr r0, .L1837+36
bl ftl_memcpy
- ldr r0, .L1848+40
+ ldr r1, .L1837+28
mov r2, #32
- add r1, r0, #2944
+ sub r0, r1, #2944
bl ftl_memcpy
-.L1759:
- ldrb r3, [r4] @ zero_extendqisi2
- ldr r6, .L1848+4
+.L1749:
+ ldrb r3, [r4, #36] @ zero_extendqisi2
cmp r3, #0
- bne .L1768
+ bne .L1759
bl FlashLoadPhyInfoInRam
cmp r0, #0
- bne .L1770
- ldr r3, [r6, #44]
+ bne .L1761
+ ldr r3, [r4, #48]
ldrh r3, [r3, #16]
- mov r3, r3, lsr #8
+ lsr r3, r3, #8
tst r3, #1
and r0, r3, #7
- strb r0, [r6, #2229]
- bne .L1770
+ strb r0, [r4, #2233]
+ bne .L1761
mov r3, #1
- strb r3, [r6, #2252]
+ strb r3, [r4, #2256]
bl FlashSetInterfaceMode
- ldrb r0, [r6, #2229] @ zero_extendqisi2
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
bl NandcSetMode
-.L1770:
- ldr r3, [r4, #44]
- ldr r6, .L1848+4
+.L1761:
+ ldr r3, [r4, #48]
ldrb r3, [r3, #26] @ zero_extendqisi2
- strb r3, [r4, #144]
+ strb r3, [r4, #152]
bl FlashLoadPhyInfo
cmp r0, #0
- beq .L1768
- ldr r3, [r6, #2256]
+ beq .L1759
+ ldr r3, [r4, #2260]
cmp r3, #0
- beq .L1773
+ beq .L1764
mov r0, #1
bl FlashSetInterfaceMode
mov r0, #1
- b .L1843
-.L1773:
- ldrb r0, [r6, #2229] @ zero_extendqisi2
- bl FlashSetInterfaceMode
- ldrb r0, [r6, #2229] @ zero_extendqisi2
-.L1843:
+.L1832:
bl NandcSetMode
bl FlashLoadPhyInfo
cmp r0, #0
- beq .L1768
+ beq .L1759
mov r0, #1
- ldr r6, .L1848+4
bl FlashSetInterfaceMode
mov r0, #1
bl NandcSetMode
- ldr r3, [r4, #44]
- ldr r0, .L1848+44
+ ldr r3, [r4, #48]
+ ldr r0, .L1837+40
ldrh r1, [r3, #14]
bl printk
bl FlashLoadPhyInfoInRam
cmn r0, #1
- beq .L1816
+ beq .L1739
bl FlashDieInfoInit
- ldr r3, [r6, #44]
+ ldr r3, [r4, #48]
ldrb r0, [r3, #19] @ zero_extendqisi2
bl FlashGetReadRetryDefault
- ldr r3, .L1848+48
- ldr r2, [r6, #44]
+ ldr r3, .L1837+44
+ ldr r2, [r4, #48]
ldrh r3, [r3, #-2]
ldrb r1, [r2, #9] @ zero_extendqisi2
add r3, r3, #4080
add r3, r3, #15
cmp r1, r3, asr #12
ldrh r3, [r2, #14]
- blt .L1775
+ blt .L1766
add r0, r3, #255
cmp r1, r0, asr #8
- bge .L1776
-.L1775:
+ bge .L1767
+.L1766:
bic r3, r3, #255
strh r3, [r2, #14] @ movhi
-.L1776:
- ldrb r3, [r4, #2229] @ zero_extendqisi2
+.L1767:
+ ldrb r3, [r4, #2233] @ zero_extendqisi2
tst r3, #6
- beq .L1777
+ beq .L1768
bl FlashSavePhyInfo
mov r0, #0
bl flash_enter_slc_mode
+ ldr r1, [r5, #1712]
mov r0, #0
- ldr r1, [r8, #1704]
bl FlashDdrParaScan
mov r0, #0
bl flash_exit_slc_mode
-.L1777:
- bl FlashSavePhyInfo
.L1768:
- ldr r2, [r4, #44]
- ldr r7, .L1848+4
- ldr r6, .L1848
- ldrb r3, [r2, #26] @ zero_extendqisi2
- ldrh r0, [r2, #10]
- ldrb r9, [r2, #18] @ zero_extendqisi2
- strb r3, [r4, #144]
- ldrh r3, [r2, #16]
- ubfx r1, r3, #7, #1
- strb r1, [r4, #8]
- ubfx r1, r3, #3, #1
- strb r1, [r8, #1733]
- ubfx r1, r3, #4, #1
+ bl FlashSavePhyInfo
+.L1759:
+ ldr r7, [r4, #48]
+ ldrb r3, [r7, #26] @ zero_extendqisi2
+ ldrb r1, [r7, #12] @ zero_extendqisi2
+ ldrh r0, [r7, #10]
+ strb r3, [r4, #152]
+ ldrh r3, [r7, #16]
+ ubfx r2, r3, #7, #1
+ strb r2, [r4, #44]
+ ubfx r2, r3, #3, #1
+ strb r2, [r5, #1741]
+ ubfx r2, r3, #4, #1
ubfx r3, r3, #8, #3
- strb r1, [r4, #2240]
- strb r3, [r4, #2229]
+ strb r2, [r4, #2244]
+ strb r3, [r4, #2233]
mov r3, #0
- ldrb r1, [r2, #12] @ zero_extendqisi2
- str r3, [r8, #1696]
+ str r3, [r5, #1704]
bl __aeabi_idiv
mov r1, r0
- mov r0, r9
+ ldrb r0, [r7, #18] @ zero_extendqisi2
bl BuildFlashLsbPageTable
bl FlashDieInfoInit
- ldr r3, [r4, #44]
+ ldr r3, [r4, #48]
ldrh r2, [r3, #16]
tst r2, #64
- beq .L1779
+ beq .L1770
ldrb r0, [r3, #19] @ zero_extendqisi2
- ldrb r3, [r7, #1211] @ zero_extendqisi2
- strb r0, [r7, #1208]
- strb r3, [r7, #1209]
- ldrb r3, [r7, #1212] @ zero_extendqisi2
- strb r3, [r6, #1713]
+ ldrb r3, [r4, #1217] @ zero_extendqisi2
+ strb r0, [r4, #84]
+ strb r3, [r4, #85]
+ ldrb r3, [r4, #1218] @ zero_extendqisi2
+ strb r3, [r5, #1721]
sub r3, r0, #1
cmp r3, #7
- bhi .L1780
- ldr r3, .L1848+52
- str r3, [r6, #1696]
+ bhi .L1771
+ ldr r3, .L1837+48
+ str r3, [r5, #1704]
sub r3, r0, #5
cmp r0, #8
cmpne r3, #1
- sub r6, r0, #8
- clz r6, r6
movls r3, #1
- strls r3, [r7, #2304]
+ strls r3, [r4, #2308]
cmp r0, #7
- mov r6, r6, lsr #5
- ldreq r6, .L1848+56
- beq .L1783
- ldr r3, .L1848+56
- cmp r6, #0
- sub r2, r3, #8
- movne r6, r3
- moveq r6, r2
-.L1783:
- sub r2, r6, #1
- add r6, r6, #31
- mov r3, #0
-.L1784:
- ldrsb r1, [r2, #1]!
- cmp r1, #0
- addeq r3, r3, #1
- cmp r2, r6
- bne .L1784
- cmp r3, #27
- bls .L1779
+ ldr r3, .L1837+16
+ beq .L1793
+ cmp r0, #8
+ addne r3, r3, #20
+ bne .L1773
+.L1793:
+ add r3, r3, #28
+.L1773:
+ sub r1, r3, #1
+ mov r2, #0
+ add r3, r3, #31
+.L1775:
+ ldrsb ip, [r1, #1]!
+ cmp ip, #0
+ addeq r2, r2, #1
+ cmp r3, r1
+ bne .L1775
+ cmp r2, #27
+ bls .L1770
bl FlashGetReadRetryDefault
bl FlashSavePhyInfo
- b .L1779
-.L1780:
- sub r3, r0, #17
- cmp r3, #2
- bhi .L1786
- ldr r3, .L1848+60
- cmp r0, #19
- str r3, [r6, #1696]
- moveq r3, #15
- bne .L1847
- b .L1845
-.L1786:
- sub r3, r0, #65
- cmp r0, #33
- cmpne r3, #1
- bhi .L1788
- ldr r3, .L1848+64
- str r3, [r6, #1696]
- mov r3, #4
- strb r3, [r7, #1209]
-.L1847:
- mov r3, #7
-.L1845:
- strb r3, [r6, #1713]
- b .L1779
-.L1788:
- sub r2, r0, #67
- sub r3, r0, #34
- cmp r2, #1
- movhi r2, #0
- movls r2, #1
- cmp r3, #1
- movhi r3, r2
- orrls r3, r2, #1
- cmp r3, #0
- beq .L1789
- ldr r3, .L1848+64
- cmp r0, #68
- cmpne r0, #35
- str r3, [r6, #1696]
- movne r3, #7
- moveq r3, #17
+.L1770:
+ ldr r3, [r4, #2268]
+ cmp r3, r6
+ bne .L1785
+ ldrb r2, [r4, #152] @ zero_extendqisi2
cmp r2, #0
- strb r3, [r6, #1713]
- movne r3, #4
- moveq r3, #5
- strb r3, [r4, #1209]
- b .L1779
-.L1789:
- cmp r0, #49
- ldreq r3, .L1848+68
- streq r3, [r6, #1696]
- beq .L1779
- cmp r0, #50
- streq r3, [r7, #2248]
- ldreq r2, .L1848+72
- streq r2, [r6, #1696]
-.L1779:
- ldr r2, [r4, #2264]
- ldr r3, .L1848+4
- cmp r2, r5
- bne .L1794
- ldrb r1, [r3, #144] @ zero_extendqisi2
- cmp r1, #0
- ldrne r3, [r3, #44]
+ ldrne r2, [r4, #48]
movne r1, #0
- strneb r1, [r3, #18]
-.L1794:
- ldrb r1, [r4, #2068] @ zero_extendqisi2
- ldr r3, .L1848+4
- cmp r1, #44
- bne .L1795
- ldrb r1, [r3, #2252] @ zero_extendqisi2
- cmp r1, #0
- beq .L1795
- cmp r2, r5
- bne .L1796
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ strbne r1, [r2, #18]
+.L1785:
+ ldrb r2, [r4, #2072] @ zero_extendqisi2
+ cmp r2, #44
+ bne .L1786
+ ldrb r2, [r4, #2256] @ zero_extendqisi2
+ cmp r2, #0
+ beq .L1786
+ cmp r3, r6
+ bne .L1787
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L1795
-.L1796:
- mov r0, #1
+ bne .L1786
+.L1787:
mov r3, #0
- strb r3, [r4, #2252]
+ mov r0, #1
+ strb r3, [r4, #2256]
bl FlashSetInterfaceMode
mov r0, #1
bl NandcSetMode
-.L1795:
- ldrb r3, [r4, #2229] @ zero_extendqisi2
+.L1786:
+ ldrb r3, [r4, #2233] @ zero_extendqisi2
tst r3, #6
- beq .L1797
- ldr r2, .L1848+4
- ldrb r2, [r2, #2252] @ zero_extendqisi2
+ beq .L1788
+ ldrb r2, [r4, #2256] @ zero_extendqisi2
cmp r2, #0
- bne .L1798
+ bne .L1789
tst r3, #1
- bne .L1797
-.L1798:
+ bne .L1788
+.L1789:
mov r0, #0
bl flash_enter_slc_mode
+ ldr r1, [r5, #1712]
mov r0, #0
- ldr r1, [r8, #1704]
bl FlashDdrParaScan
mov r0, #0
bl flash_exit_slc_mode
-.L1797:
- ldr r3, [r4, #44]
- mov r7, #16
- ldr r6, .L1848+4
+.L1788:
+ ldr r3, [r4, #48]
+ mov r6, #16
ldrb r0, [r3, #20] @ zero_extendqisi2
bl FlashBchSel
- ldr r0, .L1848+76
+ ldr r0, .L1837+52
bl FlashReadIdbDataRaw
- ldr r0, .L1848+80
- strb r7, [r4, #1]
+ ldr r0, .L1837+56
+ strb r6, [r4, #37]
bl FlashTimingCfg
- ldr r5, [r4, #44]
- ldrb r2, [r4, #2069] @ zero_extendqisi2
+ ldr r5, [r4, #48]
+ ldrb r2, [r4, #2073] @ zero_extendqisi2
ldrb r3, [r5, #12] @ zero_extendqisi2
- ldrh r8, [r5, #14]
- strh r3, [r4, #124] @ movhi
- ldrb r3, [r5, #7] @ zero_extendqisi2
- str r3, [r4, #120]
- mov r3, r2, asl r7
- orr r2, r3, r2, asl #8
- ldrb r3, [r4, #2068] @ zero_extendqisi2
- orr r3, r2, r3
- ldrb r2, [r4, #2071] @ zero_extendqisi2
- orr r3, r3, r2, asl #24
- str r3, [r4, #116]
- ldrb r3, [r4, #2230] @ zero_extendqisi2
- strh r3, [r4, #126] @ movhi
- ldrb r3, [r5, #13] @ zero_extendqisi2
- strh r8, [r4, #130] @ movhi
- strh r3, [r4, #128] @ movhi
- ldrh r3, [r5, #10]
+ ldrh r7, [r5, #14]
strh r3, [r4, #132] @ movhi
+ ldrb r3, [r5, #7] @ zero_extendqisi2
+ str r3, [r4, #128]
+ lsl r3, r2, r6
+ orr r3, r3, r2, lsl #8
+ ldrb r2, [r4, #2072] @ zero_extendqisi2
+ orr r3, r3, r2
+ ldrb r2, [r4, #2075] @ zero_extendqisi2
+ orr r3, r3, r2, lsl #24
+ str r3, [r4, #124]
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ strh r3, [r4, #134] @ movhi
+ ldrb r3, [r5, #13] @ zero_extendqisi2
+ strh r7, [r4, #138] @ movhi
+ strh r3, [r4, #136] @ movhi
+ ldrh r3, [r5, #10]
+ strh r3, [r4, #140] @ movhi
ldrb r1, [r5, #12] @ zero_extendqisi2
ldrh r0, [r5, #10]
bl __aeabi_idiv
- strh r0, [r4, #134] @ movhi
+ strh r0, [r4, #142] @ movhi
ldrb r2, [r5, #9] @ zero_extendqisi2
- strh r2, [r4, #136] @ movhi
- ldrb r1, [r5, #9] @ zero_extendqisi2
- ldrh r3, [r5, #10]
- smulbb r3, r1, r3
+ strh r2, [r4, #144] @ movhi
+ ldrh r1, [r5, #10]
+ ldrb r3, [r5, #9] @ zero_extendqisi2
+ smulbb r3, r3, r1
mov r1, #512
- strh r1, [r4, #140] @ movhi
- ldrb r1, [r4, #1] @ zero_extendqisi2
- strh r1, [r4, #142] @ movhi
+ strh r1, [r4, #148] @ movhi
+ ldrb r1, [r4, #37] @ zero_extendqisi2
uxth r3, r3
- ldrb r1, [r4] @ zero_extendqisi2
- strh r3, [r4, #138] @ movhi
+ strh r1, [r4, #150] @ movhi
+ ldrb r1, [r4, #36] @ zero_extendqisi2
+ strh r3, [r4, #146] @ movhi
cmp r1, #1
- bne .L1800
- mov r3, r3, asl #1
- mov r8, r8, lsr #1
- mov r2, r2, asl #1
- strh r3, [r6, #138] @ movhi
- strb r7, [r6, #1]
+ bne .L1790
+ lsl r3, r3, #1
+ lsr r1, r7, #1
+ lsl r2, r2, #1
+ strb r6, [r4, #37]
+ strh r3, [r4, #146] @ movhi
mov r3, #8
- strh r8, [r6, #130] @ movhi
- strh r2, [r6, #136] @ movhi
- strh r3, [r6, #142] @ movhi
-.L1800:
+ strh r1, [r4, #138] @ movhi
+ strh r2, [r4, #144] @ movhi
+ strh r3, [r4, #150] @ movhi
+.L1790:
ldrb r0, [r5, #20] @ zero_extendqisi2
bl FlashBchSel
bl ftl_flash_suspend
mov r0, #0
- b .L1816
-.L1802:
- mvn r0, #1
-.L1816:
- add sp, sp, #20
+.L1739:
+ add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1849:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1755:
+ cmp r3, #220
+ ldreq r3, .L1837+28
+ moveq r1, #4096
+ strheq r1, [r3, #14] @ movhi
+ mvneq r3, #35
+ beq .L1831
+.L1757:
+ cmp r3, #211
+ ldreq r3, .L1837+28
+ moveq r1, #4096
+ strheq r1, [r3, #14] @ movhi
+ moveq r3, #2
+ strbeq r3, [r2, #3425]
+ b .L1756
+.L1764:
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
+ bl FlashSetInterfaceMode
+ ldrb r0, [r4, #2233] @ zero_extendqisi2
+ b .L1832
+.L1771:
+ sub r3, r0, #17
+ cmp r3, #2
+ bhi .L1777
+ ldr r3, .L1837+60
+ cmp r0, #19
+ str r3, [r5, #1704]
+ moveq r3, #15
+ beq .L1834
+.L1836:
+ mov r3, #7
+.L1834:
+ strb r3, [r5, #1721]
+ b .L1770
+.L1777:
+ sub r3, r0, #65
+ cmp r0, #33
+ cmpne r3, #1
+ ldrls r3, .L1837+64
+ strls r3, [r5, #1704]
+ movls r3, #4
+ strbls r3, [r4, #85]
+ bls .L1836
+.L1779:
+ sub r3, r0, #67
+ sub r2, r0, #34
+ uxtb r3, r3
+ cmp r3, #1
+ cmphi r2, #1
+ movls r2, #1
+ movhi r2, #0
+ bhi .L1780
+ ldr r2, .L1837+64
+ cmp r0, #68
+ cmpne r0, #35
+ str r2, [r5, #1704]
+ movne r2, #7
+ moveq r2, #17
+ cmp r3, #1
+ movls r3, #4
+ movhi r3, #5
+ strb r2, [r5, #1721]
+ strb r3, [r4, #85]
+ b .L1770
+.L1780:
+ cmp r0, #49
+ ldreq r3, .L1837+68
+ streq r3, [r5, #1704]
+ beq .L1770
+ cmp r0, #50
+ ldreq r3, .L1837+72
+ streq r2, [r4, #2252]
+ streq r3, [r5, #1704]
+ b .L1770
+.L1792:
+ mvn r0, #1
+ b .L1739
+.L1838:
.align 2
-.L1848:
+.L1837:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR0+2068
.word .LC97
- .word .LANCHOR0+1210
+ .word .LANCHOR0+2072
+ .word .LANCHOR0+1216
.word 1446522928
.word .LANCHOR1
- .word .LANCHOR1+3416
- .word .LANCHOR1+3292
- .word .LANCHOR0+48
- .word .LANCHOR1+472
+ .word .LANCHOR1+3412
+ .word .LANCHOR1+3288
+ .word .LANCHOR0+52
.word .LC98
.word .LANCHOR2-568
.word HynixReadRetrial
- .word .LANCHOR0+1238
+ .word .LANCHOR2-364
+ .word 150000
.word MicronReadRetrial
.word ToshibaReadRetrial
.word SamsungReadRetrial
.word samsung_read_retrial
- .word .LANCHOR2-364
- .word 150000
.fnend
.size FlashInit, .-FlashInit
.align 2
.global FlashPageProgMsbFFData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashPageProgMsbFFData, %function
FlashPageProgMsbFFData:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
- mov r7, r1
- ldr r1, .L1867
+ mov r8, r0
+ ldr r5, .L1855
+ mov r9, r1
mov r4, r2
- mov r6, r0
- ldrb r2, [r1, #144] @ zero_extendqisi2
- mov r5, r1
- ldr r3, [r1, #44]
- cmp r2, #0
+ ldrb r3, [r5, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L1840
+ ldr r3, [r5, #2252]
+ cmp r3, #0
+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1840:
+ ldr r3, [r5, #48]
ldrb r3, [r3, #19] @ zero_extendqisi2
- beq .L1851
- ldr r2, [r1, #2248]
- cmp r2, #0
- ldmnefd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L1851:
sub r2, r3, #5
cmp r3, #50
cmpne r2, #2
- bls .L1852
+ bls .L1841
sub r2, r3, #19
- tst r2, #239
- moveq r2, #1
- movne r2, #0
- cmp r3, #68
- movne r3, r2
- orreq r3, r2, #1
- cmp r3, #0
- ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L1852:
- ldr r8, .L1867+4
- movw r10, #65535
- ldr r9, .L1867+8
-.L1854:
- ldr r3, [r5, #44]
+ and r2, r2, #239
+ cmp r2, #0
+ cmpne r3, #68
+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1841:
+ ldr r6, .L1855+4
+ sub r7, r6, #2608
+ sub r7, r7, #12
+.L1843:
+ ldr r3, [r5, #48]
ldrh r3, [r3, #10]
cmp r3, r4
- bls .L1866
- mov r3, r4, asl #1
- ldrh r3, [r9, r3]
- cmp r3, r10
- ldmnefd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
- mov r1, #255
+ bhi .L1844
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L1844:
+ lsl r3, r4, #1
+ ldrh r2, [r7, r3]
+ movw r3, #65535
+ cmp r2, r3
+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
mov r2, #32768
- ldr r0, [r8, #1716]
+ mov r1, #255
+ ldr r0, [r6, #1724]
bl ftl_memset
- ldr r2, [r8, #1716]
- add r1, r4, r7
+ ldr r3, [r6, #1724]
+ add r1, r4, r9
+ mov r0, r8
add r4, r4, #1
- mov r0, r6
- mov r3, r2
uxth r4, r4
+ mov r2, r3
bl FlashProgPage
- b .L1854
-.L1866:
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L1868:
+ b .L1843
+.L1856:
.align 2
-.L1867:
+.L1855:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR2-2620
.fnend
.size FlashPageProgMsbFFData, .-FlashPageProgMsbFFData
.align 2
.global FlashReadSlc2KPages
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadSlc2KPages, %function
FlashReadSlc2KPages:
.fnstart
@ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L1920
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L1906
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov r4, r0
+ ldr r8, .L1906+4
+ mov r9, #0
.pad #36
sub sp, sp, #36
- ldrb r3, [r3, #481] @ zero_extendqisi2
- mov r4, r0
- mov r8, #0
+ ldr fp, .L1906+8
+ ldrb r3, [r3, #477] @ zero_extendqisi2
str r1, [sp, #16]
str r2, [sp, #20]
str r3, [sp, #12]
-.L1870:
+.L1858:
ldr r3, [sp, #16]
- cmp r8, r3
- beq .L1919
+ cmp r9, r3
+ bne .L1878
+ mov r0, #0
+ add sp, sp, #36
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1878:
ldr r3, [sp, #16]
add r2, sp, #28
- mov r0, r4
ldr r1, [sp, #20]
- rsb r3, r8, r3
- ldr r9, .L1920+4
+ mov r0, r4
+ sub r3, r3, r9
uxtb r3, r3
str r3, [sp]
add r3, sp, #24
- mov fp, r9
bl LogAddr2PhyAddr
- ldrb r2, [r9, #2230] @ zero_extendqisi2
+ ldrb r2, [r8, #2234] @ zero_extendqisi2
ldr r3, [sp, #24]
- cmp r3, r2
- mvncs r3, #0
- strcs r3, [r4]
- bcs .L1872
- add r3, r9, r3
+ cmp r2, r3
+ mvnls r3, #0
+ strls r3, [r4]
+ bls .L1860
+ add r3, r8, r3
mov r7, #0
- ldrb r5, [r3, #2232] @ zero_extendqisi2
- mov r0, r5
+ ldrb r6, [r3, #2236] @ zero_extendqisi2
+ mov r0, r6
bl NandcWaitFlashReady
- mov r0, r5
+ mov r0, r6
bl NandcFlashCs
-.L1873:
+.L1861:
ldr r1, [sp, #28]
- mov r0, r5
+ mov r0, r6
bl FlashReadCmd
- mov r0, r5
+ mov r0, r6
bl NandcWaitFlashReady
ldr r3, [r4, #12]
- mov r0, r5
mov r1, #0
- str r3, [sp]
ldr r2, [sp, #12]
+ mov r0, r6
+ str r3, [sp]
ldr r3, [r4, #8]
bl NandcXferData
- ldr r3, .L1920+8
- ldrb r3, [r3, #1732] @ zero_extendqisi2
+ ldrb r3, [fp, #1740] @ zero_extendqisi2
+ mov r5, r0
cmp r3, #0
- mov r6, r0
- beq .L1874
- mov r0, r5
+ beq .L1862
+ mov r0, r6
bl flash_read_ecc
cmp r0, #5
- movhi r6, #256
-.L1874:
+ movhi r5, #256
+.L1862:
cmp r7, #9
- cmnls r6, #1
+ cmnls r5, #1
moveq r3, #1
movne r3, #0
addeq r7, r7, #1
- beq .L1873
-.L1875:
+ beq .L1861
+.L1863:
cmp r7, #0
mov r7, r3
- movne r6, #256
-.L1877:
- ldr r3, [sp, #28]
- mov r0, r5
- ldr r1, [fp, #4]
+ movne r5, #256
+.L1865:
+ ldr r3, [r8, #40]
+ mov r0, r6
+ ldr r1, [sp, #28]
add r1, r1, r3
bl FlashReadCmd
- mov r0, r5
+ mov r0, r6
bl NandcWaitFlashReady
ldr r3, [r4, #8]
- ldr r2, [r4, #12]
- mov r0, r5
- cmp r3, #0
mov r1, #0
+ ldr r2, [r4, #12]
+ mov r0, r6
+ cmp r3, #0
addne r3, r3, #2048
cmp r2, #0
addne r2, r2, #8
str r2, [sp]
ldr r2, [sp, #12]
bl NandcXferData
- ldr r3, .L1920+8
- ldrb r2, [r3, #1732] @ zero_extendqisi2
- cmp r2, #0
+ ldrb r2, [fp, #1740] @ zero_extendqisi2
mov r10, r0
- beq .L1880
- mov r0, r5
+ cmp r2, #0
+ beq .L1868
+ mov r0, r6
bl flash_read_ecc
cmp r0, #5
movhi r10, #256
-.L1880:
+.L1868:
cmp r7, #9
cmnls r10, #1
addeq r7, r7, #1
- beq .L1877
-.L1881:
+ beq .L1865
+.L1869:
cmp r7, #0
- mov r0, r5
+ mov r0, r6
movne r10, #256
bl NandcFlashDeCs
- ldrb r2, [r9, #2312] @ zero_extendqisi2
- cmp r10, r6
- movcs r3, r10
- movcc r3, r6
- add r2, r2, r2, asl #1
- cmp r3, r2, asr #2
- bls .L1883
- cmn r3, #1
- movne r3, #256
-.L1883:
- cmp r3, #256
- cmnne r3, #1
+ ldrb r3, [r8, #2316] @ zero_extendqisi2
+ cmp r5, r10
+ movcc r5, r10
+ add r3, r3, r3, lsl #1
+ cmp r5, r3, asr #2
+ bls .L1871
+ cmn r5, #1
+ movne r5, #256
+.L1871:
+ cmp r5, #256
+ cmnne r5, #1
movne r3, #0
- str r3, [r4]
+ streq r5, [r4]
+ strne r3, [r4]
ldr r3, [r4, #12]
cmp r3, #0
- beq .L1886
+ beq .L1874
ldr r2, [r3, #12]
cmn r2, #1
- bne .L1886
+ bne .L1874
ldr r2, [r3, #8]
cmn r2, #1
- bne .L1886
+ bne .L1874
ldr r3, [r3]
cmn r3, #1
strne r2, [r4]
-.L1886:
+.L1874:
ldr r3, [r4]
cmn r3, #1
- bne .L1872
+ bne .L1860
ldr r1, [r4, #4]
- ldr r0, .L1920+12
- ldrb r2, [r9, #2312] @ zero_extendqisi2
+ ldrb r2, [r8, #2316] @ zero_extendqisi2
+ ldr r0, .L1906+12
bl printk
ldr r1, [r4, #8]
cmp r1, #0
- beq .L1888
- ldr r0, .L1920+16
- mov r2, #4
+ beq .L1876
mov r3, #8
+ mov r2, #4
+ ldr r0, .L1906+16
bl rknand_print_hex
-.L1888:
+.L1876:
ldr r1, [r4, #12]
cmp r1, #0
- beq .L1872
- mov r2, #4
- ldr r0, .L1920+20
- mov r3, r2
+ beq .L1860
+ mov r3, #4
+ ldr r0, .L1906+20
+ mov r2, r3
bl rknand_print_hex
-.L1872:
- add r8, r8, #1
+.L1860:
+ add r9, r9, #1
add r4, r4, #36
- b .L1870
-.L1919:
- mov r0, #0
- add sp, sp, #36
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1921:
+ b .L1858
+.L1907:
.align 2
-.L1920:
+.L1906:
.word .LANCHOR1
.word .LANCHOR0
.word .LANCHOR2
@@ -11167,2042 +11650,2030 @@
.size FlashReadSlc2KPages, .-FlashReadSlc2KPages
.align 2
.global FlashReadPages
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadPages, %function
FlashReadPages:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L1997
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #52
sub sp, sp, #52
- ldr r6, .L1997+4
- ldrb r3, [r3, #481] @ zero_extendqisi2
- str r1, [sp, #20]
- ldrb r8, [r6] @ zero_extendqisi2
- str r3, [sp, #16]
- ldrb r3, [r6, #8] @ zero_extendqisi2
- cmp r8, #0
- str r2, [sp, #24]
- str r3, [sp, #28]
- beq .L1959
+ ldr r4, .L1979
+ str r1, [sp, #24]
+ ldrb r9, [r4, #36] @ zero_extendqisi2
+ str r2, [sp, #28]
+ cmp r9, #0
+ bne .L1909
+ ldr r3, .L1979+4
+ mov fp, r0
+ ldr r10, .L1979+8
+ str r9, [sp, #8]
+ ldrb r3, [r3, #477] @ zero_extendqisi2
+ str r3, [sp, #20]
+ ldrb r3, [r4, #44] @ zero_extendqisi2
+ str r3, [sp, #36]
+.L1910:
+ ldr r3, [sp, #8]
+ ldr r2, [sp, #24]
+ cmp r3, r2
+ bcc .L1943
+ mov r0, #0
+ b .L1908
+.L1909:
bl FlashReadSlc2KPages
- b .L1992
-.L1959:
- ldr r10, .L1997+8
- mov r9, r0
- mov fp, r8
-.L1923:
- ldr r3, [sp, #20]
- cmp fp, r3
- bcs .L1995
+.L1908:
+ add sp, sp, #52
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1943:
+ ldr r2, [sp, #8]
mov r3, #36
- add r2, sp, #44
- mul r3, r3, fp
- ldr r1, [sp, #24]
- add r7, r9, r3
- str r3, [sp, #8]
- mov r0, r7
- ldr r3, [r7, #4]
+ ldr r1, [sp, #28]
+ mul r3, r3, r2
+ add r8, fp, r3
str r3, [sp, #12]
- ldr r3, [sp, #20]
- rsb r3, fp, r3
+ ldr r3, [sp, #24]
+ mov r0, r8
+ ldr r7, [r8, #4]
+ sub r3, r3, r2
+ add r2, sp, #44
uxtb r3, r3
str r3, [sp]
add r3, sp, #40
bl LogAddr2PhyAddr
- ldrb r2, [r6, #2230] @ zero_extendqisi2
+ ldrb r2, [r4, #2234] @ zero_extendqisi2
+ mov r6, r0
ldr r3, [sp, #40]
- mov r5, r0
- cmp r3, r2
- ldrcs r2, [sp, #8]
- mvncs r3, #0
- strcs r3, [r9, r2]
- bcs .L1926
- add r3, r6, r3
- ldrb r4, [r3, #2232] @ zero_extendqisi2
- ldrb r3, [r10, #1733] @ zero_extendqisi2
+ cmp r2, r3
+ ldrls r2, [sp, #12]
+ mvnls r3, #0
+ strls r3, [fp, r2]
+ bls .L1913
+ add r3, r4, r3
+ ldrb r5, [r3, #2236] @ zero_extendqisi2
+ ldrb r3, [r10, #1741] @ zero_extendqisi2
+ mov r0, r5
cmp r3, #0
- mov r0, r4
- moveq r5, #0
+ moveq r6, #0
bl NandcWaitFlashReady
- ldr r3, .L1997+4
- ldr r3, [r3, #44]
+ ldr r3, [r4, #48]
ldrb r2, [r3, #19] @ zero_extendqisi2
sub r3, r2, #1
cmp r3, #7
- bhi .L1928
+ bhi .L1915
sub r2, r2, #7
- add r1, r6, r4
+ add r1, r4, r5
cmp r2, #1
- ldr r2, .L1997+4
- ldrb r3, [r1, #1222] @ zero_extendqisi2
- add r2, r2, r4
- ldrlsb r3, [r1, #1230] @ zero_extendqisi2
- ldrb r2, [r2, #2064] @ zero_extendqisi2
+ add r2, r4, r5
+ ldrb r3, [r1, #1228] @ zero_extendqisi2
+ ldrb r2, [r2, #2068] @ zero_extendqisi2
+ ldrbls r3, [r1, #1236] @ zero_extendqisi2
cmp r2, r3
- beq .L1928
- mov r0, r4
- ldrb r1, [r6, #1211] @ zero_extendqisi2
- ldr r2, .L1997+12
+ beq .L1915
+ ldr r2, .L1979+12
+ mov r0, r5
+ ldrb r1, [r4, #1217] @ zero_extendqisi2
bl HynixSetRRPara
-.L1928:
- mov r0, r4
+.L1915:
+ mov r0, r5
+ lsr r7, r7, #31
bl NandcFlashCs
- mov r0, r4
- ldr r3, [sp, #12]
- ldr r2, [sp, #24]
- mov r3, r3, lsr #31
- cmp r2, #1
- orreq r3, r3, #1
- str r3, [sp, #12]
+ ldr r3, [sp, #28]
+ mov r0, r5
+ cmp r3, #1
+ orreq r7, r7, #1
+ cmp r7, #0
+ str r7, [sp, #16]
+ beq .L1917
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L1930
- ldr r3, .L1997+4
- ldrb r3, [r3, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L1930
+ beq .L1917
bl flash_enter_slc_mode
- b .L1931
-.L1930:
- bl flash_exit_slc_mode
-.L1931:
+.L1923:
ldr r1, [sp, #44]
cmn r1, #1
- cmpeq r4, #255
+ cmpeq r5, #255
moveq r3, #0
movne r3, #1
- moveq r5, r3
- beq .L1933
- cmp r5, #0
- beq .L1934
- ldr r2, [r6, #4]
- mov r0, r4
+ moveq r6, r3
+ beq .L1919
+ cmp r6, #0
+ beq .L1920
+ ldr r2, [r4, #40]
+ mov r0, r5
add r2, r1, r2
bl FlashReadDpCmd
- b .L1935
-.L1934:
- mov r0, r4
- bl FlashReadCmd
-.L1935:
- mov r0, r4
+.L1921:
+ mov r0, r5
bl NandcWaitFlashReady
- cmp r5, #0
- beq .L1933
- mov r0, r4
+ cmp r6, #0
+ beq .L1919
ldr r1, [sp, #44]
+ mov r0, r5
bl FlashReadDpDataOutCmd
-.L1933:
- ldr r3, [r7, #12]
- mov r0, r4
- ldr r2, [sp, #16]
+.L1919:
+ ldr r3, [r8, #12]
mov r1, #0
+ ldr r2, [sp, #20]
+ mov r0, r5
str r3, [sp]
- ldr r3, [r7, #8]
+ ldr r3, [r8, #8]
bl NandcXferData
- ldrb r2, [r6, #8] @ zero_extendqisi2
- adds r2, r2, #0
+ ldrb r3, [r4, #44] @ zero_extendqisi2
+ mov r7, r0
+ adds r2, r3, #0
movne r2, #1
cmn r0, #1
- mov ip, r0
movne r2, #0
cmp r2, #0
- movne r3, #0
- strneb r3, [r6, #8]
- movne r5, r3
- bne .L1931
-.L1936:
- cmp r5, #0
- beq .L1937
- ldr r3, .L1997+4
- str r0, [sp, #32]
- mov r0, r4
- str r2, [sp, #36]
- ldr r1, [r3, #4]
- ldr r3, [sp, #44]
+ str r2, [sp, #32]
+ beq .L1922
+ mov r3, #0
+ mov r6, #0
+ strb r3, [r4, #44]
+ b .L1923
+.L1917:
+ bl flash_exit_slc_mode
+ b .L1923
+.L1920:
+ mov r0, r5
+ bl FlashReadCmd
+ b .L1921
+.L1922:
+ cmp r6, #0
+ beq .L1924
+ ldr r3, [r4, #40]
+ mov r0, r5
+ ldr r1, [sp, #44]
add r1, r1, r3
bl FlashReadDpDataOutCmd
- mov r0, r4
- ldr r3, [sp, #8]
- ldr r2, [sp, #36]
+ ldr r3, [sp, #12]
+ mov r0, r5
+ ldr r1, [sp, #32]
add r3, r3, #36
- add r3, r9, r3
- ldr r1, [r3, #12]
- str r1, [sp]
- mov r1, r2
+ add r3, fp, r3
+ ldr r2, [r3, #12]
+ str r2, [sp]
+ ldr r2, [sp, #20]
ldr r3, [r3, #8]
- ldr r2, [sp, #16]
bl NandcXferData
cmn r0, #1
- ldr ip, [sp, #32]
- mov r8, r0
- moveq r5, #0
-.L1937:
- mov r0, r4
- str ip, [sp, #32]
+ mov r9, r0
+ moveq r6, #0
+.L1924:
+ mov r0, r5
bl NandcFlashDeCs
- ldr ip, [sp, #32]
- ldrb r3, [sp, #28] @ zero_extendqisi2
- cmn ip, #1
- strb r3, [r6, #8]
- bne .L1944
- ldrb r3, [r6, #2252] @ zero_extendqisi2
+ ldrb r3, [sp, #36] @ zero_extendqisi2
+ cmn r7, #1
+ strb r3, [r4, #44]
+ bne .L1925
+ ldrb r3, [r4, #2256] @ zero_extendqisi2
cmp r3, #0
- bne .L1939
-.L1943:
- ldr r5, [r10, #1696]
- cmp r5, #0
- bne .L1940
- b .L1996
-.L1939:
- ldr r3, [r6, #80]
- mov r0, r4
+ bne .L1926
+.L1930:
+ ldr r6, [r10, #1704]
+ cmp r6, #0
+ bne .L1927
+ ldr r3, [r8, #12]
+ mov r0, r5
+ ldr r2, [r8, #8]
ldr r1, [sp, #44]
- ldr r5, [r3, #304]
+ bl FlashReadRawPage
+ mov r7, r0
+.L1931:
+ cmp r7, #256
+ cmnne r7, #1
+ ldreq r3, [sp, #12]
+ movne r3, #0
+ ldrne r2, [sp, #12]
+ streq r7, [fp, r3]
+ strne r3, [fp, r2]
+ ldr r3, [sp, #12]
+ ldr r3, [fp, r3]
+ cmn r3, #1
+ bne .L1938
+ ldr r1, [r8, #4]
+ ldrb r2, [r4, #2316] @ zero_extendqisi2
+ ldr r0, .L1979+16
+ bl printk
+ ldr r1, [r8, #12]
+ cmp r1, #0
+ beq .L1938
+ mov r3, #4
+ ldr r0, .L1979+20
+ mov r2, r3
+ bl rknand_print_hex
+.L1938:
+ cmp r6, #0
+ beq .L1940
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
+ cmp r9, r3, asr #2
+ bls .L1941
+ ldr r3, [r10, #1704]
+ cmp r3, #0
+ moveq r9, #256
+.L1941:
+ ldr r3, [sp, #12]
+ cmp r9, #256
+ cmnne r9, #1
+ movne r2, #0
+ add r3, r3, #36
+ streq r9, [fp, r3]
+ strne r2, [fp, r3]
+.L1940:
+ ldr r3, [sp, #8]
+ add r3, r3, r6
+ str r3, [sp, #8]
+ ldr r3, [sp, #16]
+ cmp r3, #0
+ beq .L1913
+ ldrb r3, [r4, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L1913
+ mov r0, r5
+ bl flash_exit_slc_mode
+.L1913:
+ ldr r3, [sp, #8]
+ add r3, r3, #1
+ str r3, [sp, #8]
+ b .L1910
+.L1926:
+ ldr r3, [r4, #88]
+ mov r0, r5
+ ldr r1, [sp, #44]
+ ldr r6, [r3, #304]
mov r3, #1
str r3, [sp]
- ldr r2, [r7, #8]
- ldr r3, [r7, #12]
+ ldr r3, [r8, #12]
+ ldr r2, [r8, #8]
bl FlashDdrTunningRead
cmn r0, #1
- mov ip, r0
- beq .L1942
- ldrb r3, [r6, #2312] @ zero_extendqisi2
+ mov r7, r0
+ beq .L1929
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
cmp r0, r3, lsr #1
- bls .L1962
-.L1942:
- ubfx r0, r5, #8, #8
- str ip, [sp, #32]
+ bls .L1946
+.L1929:
+ ubfx r0, r6, #8, #8
bl NandcSetDdrPara
- ldr ip, [sp, #32]
- cmn ip, #1
- beq .L1943
- b .L1962
-.L1940:
- mov r0, r4
+ cmn r7, #1
+ beq .L1930
+.L1946:
+ mov r6, #0
+.L1925:
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
+ add r3, r3, r3, lsl #1
+ cmp r7, r3, asr #2
+ bls .L1931
+ ldr r3, [r10, #1704]
+ cmp r3, #0
+ moveq r7, #256
+ b .L1931
+.L1927:
+ ldr r3, [r8, #12]
+ mov r0, r5
+ ldr r2, [r8, #8]
ldr r1, [sp, #44]
- ldr r2, [r7, #8]
- ldr r3, [r7, #12]
- blx r5
+ blx r6
cmn r0, #1
- mov ip, r0
- bne .L1964
- ldr r3, [r6, #44]
+ mov r7, r0
+ bne .L1948
+ ldr r3, [r4, #48]
ldrb r3, [r3, #19] @ zero_extendqisi2
sub r3, r3, #1
cmp r3, #7
- bhi .L1946
- mov r0, r4
- ldrb r1, [r6, #1211] @ zero_extendqisi2
- ldr r2, .L1997+12
+ bhi .L1932
mov r3, #0
+ ldr r2, .L1979+12
+ ldrb r1, [r4, #1217] @ zero_extendqisi2
+ mov r0, r5
bl HynixSetRRPara
-.L1946:
+.L1932:
+ ldr r3, [r8, #12]
+ mov r0, r5
+ ldr r2, [r8, #8]
ldr r1, [sp, #44]
- mov r0, r4
- ldr r2, [r7, #8]
- ldr r3, [r7, #12]
bl FlashReadRawPage
- ldr r1, [r7, #4]
- ldrb r2, [r6, #2312] @ zero_extendqisi2
- mov ip, r0
- ldr r0, .L1997+16
- mov r3, ip
- str ip, [sp, #32]
+ ldrb r2, [r4, #2316] @ zero_extendqisi2
+ mov r7, r0
+ mov r3, r0
+ ldr r1, [r8, #4]
+ ldr r0, .L1979+24
bl printk
- ldr ip, [sp, #32]
- cmn ip, #1
- bne .L1964
- ldrb r5, [r6, #144] @ zero_extendqisi2
- cmp r5, #0
- beq .L1945
- ldr r3, [sp, #12]
- mov r0, r4
+ cmn r7, #1
+ bne .L1948
+ ldrb r6, [r4, #152] @ zero_extendqisi2
+ cmp r6, #0
+ beq .L1931
+ ldr r3, [sp, #16]
+ mov r0, r5
cmp r3, #0
- beq .L1947
+ beq .L1933
bl flash_enter_slc_mode
- b .L1948
-.L1947:
- bl flash_exit_slc_mode
+.L1934:
+ ldr r6, [r10, #1704]
+ mov r0, r5
+ ldr r3, [r8, #12]
+ ldr r2, [r8, #8]
+ ldr r1, [sp, #44]
+ blx r6
+ mov r7, r0
.L1948:
- ldr ip, [r10, #1696]
- mov r0, r4
- ldr r1, [sp, #44]
- ldr r2, [r7, #8]
- ldr r3, [r7, #12]
- blx ip
- mov ip, r0
- b .L1964
-.L1996:
- mov r0, r4
- ldr r1, [sp, #44]
- ldr r2, [r7, #8]
- ldr r3, [r7, #12]
- bl FlashReadRawPage
- mov ip, r0
- b .L1945
-.L1962:
- mov r5, #0
-.L1944:
- ldrb r3, [r6, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
- cmp ip, r3, asr #2
- bls .L1945
- ldr r3, [r10, #1696]
- cmp r3, #0
- moveq ip, #256
- b .L1945
-.L1964:
- mov r5, #0
-.L1945:
- cmp ip, #256
- cmnne ip, #1
- ldreq r3, [sp, #8]
- movne r3, #0
- ldrne r2, [sp, #8]
- streq ip, [r9, r3]
- strne r3, [r9, r2]
- ldr r3, [sp, #8]
- ldr r3, [r9, r3]
- cmn r3, #1
- bne .L1952
- ldr r1, [r7, #4]
- ldr r0, .L1997+20
- ldrb r2, [r6, #2312] @ zero_extendqisi2
- bl printk
- ldr r1, [r7, #12]
- cmp r1, #0
- beq .L1952
- mov r2, #4
- ldr r0, .L1997+24
- mov r3, r2
- bl rknand_print_hex
-.L1952:
- cmp r5, #0
- beq .L1954
- ldrb r3, [r6, #2312] @ zero_extendqisi2
- add r3, r3, r3, asl #1
- cmp r8, r3, asr #2
- bls .L1955
- ldr r3, [r10, #1696]
- cmp r3, #0
- moveq r8, #256
-.L1955:
- ldr r3, [sp, #8]
- cmp r8, #256
- cmnne r8, #1
- add r3, r3, #36
- movne r2, #0
- streq r8, [r9, r3]
- strne r2, [r9, r3]
-.L1954:
- ldr r3, [sp, #12]
- add fp, fp, r5
- cmp r3, #0
- beq .L1926
- ldrb r3, [r6, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L1926
- mov r0, r4
+ mov r6, #0
+ b .L1931
+.L1933:
bl flash_exit_slc_mode
-.L1926:
- add fp, fp, #1
- b .L1923
-.L1995:
- mov r0, #0
-.L1992:
- add sp, sp, #52
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L1998:
+ b .L1934
+.L1980:
.align 2
-.L1997:
- .word .LANCHOR1
+.L1979:
.word .LANCHOR0
+ .word .LANCHOR1
.word .LANCHOR2
- .word .LANCHOR0+1214
- .word .LC102
+ .word .LANCHOR0+1220
.word .LC99
.word .LC101
+ .word .LC102
.fnend
.size FlashReadPages, .-FlashReadPages
.align 2
.global FlashLoadFactorBbt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashLoadFactorBbt, %function
FlashLoadFactorBbt:
.fnstart
@ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r2, #16
- ldr r4, .L2012
+ ldr r8, .L1993
.pad #60
sub sp, sp, #60
- ldr r0, .L2012+4
mov r1, #0
- ldr r10, .L2012+8
- mov r5, #0
- ldrh r3, [r4, #130]
mvn fp, #0
- ldrh r6, [r4, #128]
+ ldr r10, .L1993+4
+ mov r5, #0
+ ldrh r3, [r8, #136]
mov r9, r5
- mov r8, r4
+ ldrh r6, [r8, #138]
+ ldr r0, .L1993+8
smulbb r6, r6, r3
bl ftl_memset
- ldr r3, [r10, #1720]
+ ldr r3, [r10, #1728]
uxth r6, r6
- add r2, r6, fp
- str r3, [sp, #32]
- uxth r3, r2
str r5, [sp, #28]
- str r3, [sp, #4]
-.L2000:
- ldrb r3, [r8, #2230] @ zero_extendqisi2
+ str r3, [sp, #32]
+ add r3, r6, fp
+ uxth r3, r3
+ str r3, [sp, #8]
+.L1982:
+ ldrb r3, [r8, #2234] @ zero_extendqisi2
uxtb r7, r5
cmp r3, r7
- bls .L2011
- mul ip, r6, r7
- ldr r4, [sp, #4]
- sub r3, r6, #12
-.L2001:
- cmp r4, r3
- ble .L2003
- add r2, ip, r4
- mov r1, #1
- add r0, sp, #20
- str r3, [sp, #12]
- mov r2, r2, asl #10
- str r2, [sp, #24]
- mov r2, r1
- str ip, [sp, #8]
- bl FlashReadPages
- ldr r2, [sp, #20]
- ldr ip, [sp, #8]
- cmn r2, #1
- ldr r3, [sp, #12]
- beq .L2002
- ldr r2, [r10, #1720]
- ldrh r1, [r2]
- movw r2, #61664
- cmp r1, r2
- bne .L2002
- mov r1, r7
- ldr r0, .L2012+12
- mov r2, r4
- mov r7, r7, asl #1
- bl printk
- ldr r3, .L2012+4
- add r9, r9, #1
- strh r4, [r3, r7] @ movhi
- uxth r9, r9
- b .L2003
-.L2002:
- sub r4, r4, #1
- uxth r4, r4
- b .L2001
-.L2003:
- ldrb r3, [r8, #2230] @ zero_extendqisi2
- add r5, r5, #1
- cmp r3, r9
- moveq fp, #0
- b .L2000
-.L2011:
+ bhi .L1988
mov r0, fp
add sp, sp, #60
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2013:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L1988:
+ ldr r4, [sp, #8]
+ mul r3, r7, r6
+ sub r2, r6, #12
+ str r2, [sp, #4]
+.L1983:
+ ldr r2, [sp, #4]
+ cmp r4, r2
+ ble .L1985
+ add r2, r4, r3
+ add r0, sp, #20
+ lsl r2, r2, #10
+ str r3, [sp, #12]
+ str r2, [sp, #24]
+ mov r2, #1
+ mov r1, r2
+ bl FlashReadPages
+ ldr r2, [sp, #20]
+ ldr r3, [sp, #12]
+ cmn r2, #1
+ beq .L1984
+ ldr r2, [r10, #1728]
+ ldrh r1, [r2]
+ movw r2, #61664
+ cmp r1, r2
+ bne .L1984
+ mov r1, r7
+ mov r2, r4
+ ldr r0, .L1993+12
+ add r9, r9, #1
+ bl printk
+ uxth r9, r9
+ ldr r3, .L1993+8
+ lsl r7, r7, #1
+ strh r4, [r3, r7] @ movhi
+.L1985:
+ ldrb r3, [r8, #2234] @ zero_extendqisi2
+ add r5, r5, #1
+ cmp r3, r9
+ moveq fp, #0
+ b .L1982
+.L1984:
+ sub r4, r4, #1
+ uxth r4, r4
+ b .L1983
+.L1994:
.align 2
-.L2012:
+.L1993:
.word .LANCHOR0
- .word .LANCHOR2+1736
.word .LANCHOR2
+ .word .LANCHOR2+1742
.word .LC103
.fnend
.size FlashLoadFactorBbt, .-FlashLoadFactorBbt
.align 2
.global FlashProgSlc2KPages
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgSlc2KPages, %function
FlashProgSlc2KPages:
.fnstart
- @ args = 0, pretend = 0, frame = 56
+ @ args = 0, pretend = 0, frame = 48
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L2044
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L2023
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #68
- sub sp, sp, #68
- ldr r8, .L2044+4
- mov r6, r1
- ldrb r3, [r3, #481] @ zero_extendqisi2
- mov r9, r2
+ mov r10, r1
+ ldr r9, .L2023+4
+ .pad #60
+ sub sp, sp, #60
+ mov r8, r2
mov r4, r0
- mov r10, r0
+ ldrb fp, [r3, #477] @ zero_extendqisi2
+ mov r6, r0
mov r7, #0
- mov fp, r8
- str r3, [sp, #12]
-.L2015:
+.L1996:
+ cmp r7, r10
+ bne .L2002
+ ldr r5, .L2023+8
+ mov r6, #0
+ ldr r9, .L2023+12
+.L2003:
cmp r7, r6
- beq .L2042
- rsb r3, r7, r6
- add r2, sp, #20
- mov r0, r10
- mov r1, r9
+ bne .L2010
+ mov r0, #0
+ add sp, sp, #60
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2002:
+ sub r3, r10, r7
+ add r2, sp, #12
uxtb r3, r3
+ mov r1, r8
+ mov r0, r6
str r3, [sp]
- add r3, sp, #24
+ add r3, sp, #16
bl LogAddr2PhyAddr
- ldrb r2, [r8, #2230] @ zero_extendqisi2
- ldr r3, [sp, #24]
- cmp r3, r2
- mvncs r3, #0
- strcs r3, [r10]
- bcs .L2017
- add r3, r8, r3
- ldrb r5, [r3, #2232] @ zero_extendqisi2
+ ldrb r2, [r9, #2234] @ zero_extendqisi2
+ ldr r3, [sp, #16]
+ cmp r2, r3
+ mvnls r3, #0
+ strls r3, [r6]
+ bls .L1998
+ add r3, r9, r3
+ ldrb r5, [r3, #2236] @ zero_extendqisi2
mov r0, r5
bl NandcWaitFlashReady
mov r0, r5
bl NandcFlashCs
mov r0, r5
- ldr r1, [sp, #20]
+ ldr r1, [sp, #12]
bl FlashProgFirstCmd
- ldr r3, [r10, #12]
+ ldr r3, [r6, #12]
+ mov r2, fp
mov r1, #1
mov r0, r5
- ldr r2, [sp, #12]
str r3, [sp]
- ldr r3, [r10, #8]
+ ldr r3, [r6, #8]
bl NandcXferData
mov r0, r5
- ldr r1, [sp, #20]
+ ldr r1, [sp, #12]
bl FlashProgSecondCmd
mov r0, r5
bl NandcWaitFlashReady
mov r0, r5
- ldr r1, [sp, #20]
+ ldr r1, [sp, #12]
bl FlashReadStatus
- ldr r3, [sp, #20]
sbfx r0, r0, #0, #1
- str r0, [r10]
+ ldr r1, [sp, #12]
+ str r0, [r6]
mov r0, r5
- ldr r1, [r8, #4]
+ ldr r3, [r9, #40]
add r1, r1, r3
bl FlashProgFirstCmd
- ldr r3, [r10, #8]
- ldr r2, [r10, #12]
+ ldr r3, [r6, #8]
mov r1, #1
- cmp r3, #0
+ ldr r2, [r6, #12]
mov r0, r5
+ cmp r3, #0
addne r3, r3, #2048
cmp r2, #0
addne r2, r2, #8
str r2, [sp]
- ldr r2, [sp, #12]
+ mov r2, fp
bl NandcXferData
- ldr r1, [fp, #4]
+ ldr r3, [r9, #40]
mov r0, r5
- ldr r3, [sp, #20]
+ ldr r1, [sp, #12]
add r1, r1, r3
bl FlashProgSecondCmd
mov r0, r5
bl NandcWaitFlashReady
mov r0, r5
- ldr r1, [sp, #20]
+ ldr r1, [sp, #12]
bl FlashReadStatus
tst r0, #1
mov r0, r5
mvnne r3, #0
- strne r3, [r10]
+ strne r3, [r6]
bl NandcFlashDeCs
-.L2017:
+.L1998:
add r7, r7, #1
- add r10, r10, #36
- b .L2015
-.L2042:
- ldr r5, .L2044+8
- mov r7, #0
- mov r8, r5
-.L2022:
- cmp r7, r6
- beq .L2043
+ add r6, r6, #36
+ b .L1996
+.L2010:
ldr r3, [r4]
cmn r3, #1
- bne .L2023
+ bne .L2004
ldr r1, [r4, #4]
- ldr r0, .L2044+12
+ ldr r0, .L2023+16
bl printk
- b .L2024
-.L2023:
- rsb r3, r7, r6
- mov r1, r9
- add r2, sp, #20
- mov r0, r4
+.L2005:
+ add r6, r6, #1
+ add r4, r4, #36
+ b .L2003
+.L2004:
+ sub r3, r7, r6
+ add r2, sp, #12
uxtb r3, r3
+ mov r1, r8
+ mov r0, r4
str r3, [sp]
- add r3, sp, #24
+ add r3, sp, #16
bl LogAddr2PhyAddr
- ldr r2, [r5, #1724]
+ ldr r2, [r5, #1732]
mov r3, #0
mov lr, r4
+ add ip, sp, #20
str r3, [r2]
- ldr r2, [r5, #1728]
+ ldr r2, [r5, #1736]
str r3, [r2]
ldmia lr!, {r0, r1, r2, r3}
- add ip, sp, #28
stmia ip!, {r0, r1, r2, r3}
ldmia lr!, {r0, r1, r2, r3}
stmia ip!, {r0, r1, r2, r3}
- add r0, sp, #28
+ mov r2, r8
ldr r3, [lr]
mov r1, #1
- mov r2, r9
+ add r0, sp, #20
str r3, [ip]
- ldr r3, [r5, #1724]
- str r3, [sp, #36]
- ldr r3, [r5, #1728]
- str r3, [sp, #40]
+ ldr r3, [r5, #1732]
+ str r3, [sp, #28]
+ ldr r3, [r5, #1736]
+ str r3, [sp, #32]
bl FlashReadPages
- ldr r10, [sp, #28]
+ ldr r10, [sp, #20]
cmn r10, #1
- bne .L2025
- ldr r0, .L2044+16
+ bne .L2006
ldr r1, [r4, #4]
+ ldr r0, .L2023+20
bl printk
str r10, [r4]
-.L2025:
- ldr r10, [sp, #28]
+.L2006:
+ ldr r10, [sp, #20]
cmp r10, #256
- bne .L2026
- ldr r0, .L2044+20
+ bne .L2007
ldr r1, [r4, #4]
+ ldr r0, .L2023+24
bl printk
str r10, [r4]
-.L2026:
+.L2007:
ldr r3, [r4, #12]
cmp r3, #0
- beq .L2027
+ beq .L2008
ldr r2, [r3]
- ldr r3, [r8, #1728]
+ ldr r3, [r5, #1736]
ldr r3, [r3]
cmp r2, r3
- beq .L2027
- ldr r0, .L2044+24
+ beq .L2008
ldr r1, [r4, #4]
+ ldr r0, .L2023+28
bl printk
mvn r3, #0
str r3, [r4]
-.L2027:
+.L2008:
ldr r3, [r4, #8]
cmp r3, #0
- beq .L2024
+ beq .L2005
ldr r2, [r3]
- ldr r3, [r8, #1724]
+ ldr r3, [r5, #1732]
ldr r3, [r3]
cmp r2, r3
- beq .L2024
- ldr r0, .L2044+28
+ beq .L2005
ldr r1, [r4, #4]
+ mov r0, r9
bl printk
mvn r3, #0
str r3, [r4]
+ b .L2005
.L2024:
- add r7, r7, #1
- add r4, r4, #36
- b .L2022
-.L2043:
- mov r0, #0
- add sp, sp, #68
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2045:
.align 2
-.L2044:
+.L2023:
.word .LANCHOR1
.word .LANCHOR0
.word .LANCHOR2
+ .word .LC108
.word .LC104
.word .LC105
.word .LC106
.word .LC107
- .word .LC108
.fnend
.size FlashProgSlc2KPages, .-FlashProgSlc2KPages
.align 2
.global FtlLoadFactoryBbt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadFactoryBbt, %function
FtlLoadFactoryBbt:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
mov r7, #0
- ldr r5, .L2058
- ldr r6, .L2058+4
+ ldr r5, .L2036
+ ldr r6, .L2036+4
ldr r3, [r5, #-524]
- sub r9, r6, #76
ldr r8, [r5, #-500]
sub r10, r6, #120
- mov fp, r9
- str r3, [r5, #1760]
- str r8, [r5, #1764]
-.L2047:
+ sub r9, r6, #78
+ str r3, [r5, #1768]
+ str r8, [r5, #1772]
+.L2026:
ldrh r3, [r10]
cmp r7, r3
- bcs .L2057
- ldrh r4, [r9]
- mvn r3, #0
- movw ip, #61664
- strh r3, [r6, #2]! @ movhi
- add r4, r4, r3
- uxth r4, r4
-.L2048:
- ldrh r3, [fp]
- sub r2, r3, #16
- cmp r4, r2
- ble .L2050
- mla r3, r3, r7, r4
- mov r1, #1
- ldr r0, .L2058+8
- mov r2, r1
- str ip, [sp, #4]
- mov r3, r3, asl #10
- str r3, [r5, #1756]
- bl FlashReadPages
- ldr r3, [r5, #1752]
- cmn r3, #1
- ldr ip, [sp, #4]
- beq .L2049
- ldrh r3, [r8]
- cmp r3, ip
- streqh r4, [r6] @ movhi
- beq .L2050
-.L2049:
- sub r4, r4, #1
- uxth r4, r4
- b .L2048
-.L2050:
- add r7, r7, #1
- b .L2047
-.L2057:
+ bcc .L2031
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2059:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2031:
+ ldrh r4, [r9]
+ mvn r3, #0
+ ldr fp, .L2036+8
+ strh r3, [r6, #2]! @ movhi
+ add r4, r4, r3
+ movw r3, #61664
+ uxth r4, r4
+.L2027:
+ ldrh r2, [r9]
+ sub r1, r2, #16
+ cmp r4, r1
+ ble .L2029
+ mla r2, r7, r2, r4
+ str r3, [sp, #4]
+ mov r0, fp
+ lsl r2, r2, #10
+ str r2, [r5, #1764]
+ mov r2, #1
+ mov r1, r2
+ bl FlashReadPages
+ ldr r2, [r5, #1760]
+ ldr r3, [sp, #4]
+ cmn r2, #1
+ beq .L2028
+ ldrh r2, [r8]
+ cmp r2, r3
+ bne .L2028
+ strh r4, [r6] @ movhi
+.L2029:
+ add r7, r7, #1
+ b .L2026
+.L2028:
+ sub r4, r4, #1
+ uxth r4, r4
+ b .L2027
+.L2037:
.align 2
-.L2058:
+.L2036:
.word .LANCHOR2
- .word .LANCHOR0+2462
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2466
+ .word .LANCHOR2+1760
.fnend
.size FtlLoadFactoryBbt, .-FtlLoadFactoryBbt
.align 2
.global FtlGetLastWrittenPage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGetLastWrittenPage, %function
FtlGetLastWrittenPage:
.fnstart
@ args = 0, pretend = 0, frame = 104
@ frame_needed = 0, uses_anonymous_args = 0
+ ldr r3, .L2051
cmp r1, #1
- ldr r3, .L2073
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ movweq r2, #2392
+ movwne r2, #2390
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
- movweq r2, #2390
- movwne r2, #2388
+ lsl r8, r0, #10
+ ldrh r5, [r3, r2]
.pad #104
sub sp, sp, #104
- ldrh r4, [r3, r2]
- mov r8, r1
add r3, sp, #40
- mov r6, r0, asl #10
- sub r5, r4, #1
+ mov r2, r1
str r3, [sp, #16]
- add r0, sp, #4
+ mov r7, r1
+ sub r5, r5, #1
+ mov r6, #0
+ sxth r5, r5
mov r1, #1
- uxth r5, r5
- mov r2, r8
- mov r7, #0
- str r7, [sp, #12]
- sxth r3, r5
- orr r3, r3, r6
+ add r0, sp, #4
+ str r6, [sp, #12]
+ orr r3, r5, r8
str r3, [sp, #8]
bl FlashReadPages
ldr r3, [sp, #40]
cmn r3, #1
- bne .L2063
-.L2064:
- sxth r4, r7
- sxth r3, r5
- cmp r4, r3
- bgt .L2063
- add r4, r4, r3
- add r0, sp, #4
+ bne .L2041
+.L2042:
+ cmp r6, r5
+ ble .L2045
+.L2041:
+ mov r0, r5
+ add sp, sp, #104
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, pc}
+.L2045:
+ add r3, r6, r5
+ mov r2, r7
+ add r3, r3, r3, lsr #31
mov r1, #1
- mov r2, r8
- add r4, r4, r4, lsr #31
- mov r4, r4, asr #1
+ add r0, sp, #4
+ asr r4, r3, #1
sxth r3, r4
- orr r3, r3, r6
+ orr r3, r3, r8
str r3, [sp, #8]
bl FlashReadPages
ldr r3, [sp, #40]
cmn r3, #1
- bne .L2065
+ bne .L2043
ldr r3, [sp, #44]
cmn r3, #1
- bne .L2065
+ bne .L2043
ldr r3, [sp, #4]
cmn r3, #1
subne r4, r4, #1
- uxthne r5, r4
- bne .L2064
-.L2065:
- add r3, r4, #1
- uxth r7, r3
- b .L2064
-.L2063:
- sxth r0, r5
- add sp, sp, #104
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L2074:
+ sxthne r5, r4
+ bne .L2042
+.L2043:
+ add r4, r4, #1
+ sxth r6, r4
+ b .L2042
+.L2052:
.align 2
-.L2073:
+.L2051:
.word .LANCHOR0
.fnend
.size FtlGetLastWrittenPage, .-FtlGetLastWrittenPage
.align 2
.global FtlLoadBbt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadBbt, %function
FtlLoadBbt:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
- ldr r4, .L2108
- ldr r7, .L2108+4
- ldr r8, .L2108+8
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ ldr r4, .L2085
+ ldr r5, .L2085+4
ldr r3, [r4, #-524]
- mov r9, r4
- ldr r6, [r4, #-500]
- str r3, [r4, #1760]
- str r6, [r4, #1764]
+ add r8, r4, #1760
+ ldr r7, [r4, #-500]
+ ldr r9, .L2085+8
+ str r3, [r4, #1768]
+ str r7, [r4, #1772]
bl FtlBbtMemInit
- movw r3, #2386
- ldrh r5, [r7, r3]
- sub r5, r5, #1
- uxth r5, r5
-.L2076:
- ldrh r3, [r8]
+ movw r3, #2388
+ ldrh r6, [r5, r3]
+ sub r6, r6, #1
+ uxth r6, r6
+.L2054:
+ ldrh r3, [r9]
sub r3, r3, #48
- cmp r5, r3
- ble .L2079
- mov r1, #1
- ldr r0, .L2108+12
- mov r2, r1
- mov r3, r5, asl #10
- str r3, [r4, #1756]
+ cmp r6, r3
+ ble .L2057
+ lsl r3, r6, #10
+ mov r2, #1
+ mov r1, r2
+ mov r0, r8
+ str r3, [r4, #1764]
bl FlashReadPages
- ldr r3, [r4, #1752]
+ ldr r3, [r4, #1760]
cmn r3, #1
- bne .L2077
- ldr r3, [r9, #1756]
- mov r1, #1
- ldr r0, .L2108+12
- mov r2, r1
+ bne .L2055
+ ldr r3, [r4, #1764]
+ mov r2, #1
+ mov r1, r2
+ mov r0, r8
add r3, r3, #1
- str r3, [r9, #1756]
+ str r3, [r4, #1764]
bl FlashReadPages
-.L2077:
- ldr r3, [r4, #1752]
+.L2055:
+ ldr r3, [r4, #1760]
cmn r3, #1
- beq .L2078
- ldrh r2, [r6]
+ beq .L2056
+ ldrh r2, [r7]
movw r3, #61649
cmp r2, r3
- bne .L2078
- movw r3, #2452
- strh r5, [r7, r3] @ movhi
- ldr r3, [r6, #4]
- str r3, [r7, #2460]
- ldr r3, .L2108+16
- ldrh r2, [r6, #8]
+ bne .L2056
+ movw r3, #2456
+ strh r6, [r5, r3] @ movhi
+ ldr r3, [r7, #4]
+ str r3, [r5, #2464]
+ ldr r3, .L2085+12
+ ldrh r2, [r7, #8]
strh r2, [r3, #4] @ movhi
- b .L2079
-.L2078:
- sub r5, r5, #1
- uxth r5, r5
- b .L2076
-.L2079:
- movw r9, #2452
+.L2057:
+ movw r8, #2456
movw r2, #65535
- ldrh r3, [r7, r9]
- ldr r8, .L2108+4
+ ldrh r3, [r5, r8]
+ ldr r6, .L2085+12
cmp r3, r2
- ldr r5, .L2108+16
- beq .L2093
- ldrh r3, [r5, #4]
+ beq .L2071
+ ldrh r3, [r6, #4]
cmp r3, r2
- beq .L2083
- mov r1, #1
- ldr r0, .L2108+12
- mov r2, r1
- mov r3, r3, asl #10
- str r3, [r4, #1756]
+ beq .L2061
+ lsl r3, r3, #10
+ mov r2, #1
+ mov r1, r2
+ ldr r0, .L2085+16
+ str r3, [r4, #1764]
bl FlashReadPages
- ldr r3, [r4, #1752]
+ ldr r3, [r4, #1760]
cmn r3, #1
- beq .L2083
- ldrh r2, [r6]
+ beq .L2061
+ ldrh r2, [r7]
movw r3, #61649
cmp r2, r3
- bne .L2083
- ldr r3, [r6, #4]
- ldr r2, [r8, #2460]
+ bne .L2061
+ ldr r3, [r7, #4]
+ ldr r2, [r5, #2464]
cmp r3, r2
- strhi r3, [r8, #2460]
- ldrhih r2, [r5, #4]
- ldrhih r3, [r6, #8]
- strhih r2, [r8, r9] @ movhi
- strhih r3, [r5, #4] @ movhi
-.L2083:
- movw r3, #2452
+ ldrhhi r2, [r6, #4]
+ strhi r3, [r5, #2464]
+ ldrhhi r3, [r7, #8]
+ strhhi r2, [r5, r8] @ movhi
+ strhhi r3, [r6, #4] @ movhi
+.L2061:
+ ldr r9, .L2085+16
+ movw r3, #2456
mov r1, #1
- ldrh r0, [r7, r3]
- movw r8, #61649
+ ldrh r0, [r5, r3]
+ movw r10, #61649
bl FtlGetLastWrittenPage
- uxth r7, r0
+ sxth r8, r0
add r0, r0, #1
- strh r0, [r5, #2] @ movhi
-.L2085:
- sxth r3, r7
- cmp r3, #0
- blt .L2090
- ldrh r2, [r5]
- mov r1, #1
- ldr r0, .L2108+12
- orr r3, r3, r2, asl #10
- str r3, [r4, #1756]
- ldr r3, [r4, #-524]
- mov r2, r1
- str r3, [r4, #1760]
- bl FlashReadPages
- ldr r3, [r4, #1752]
- cmn r3, #1
- beq .L2086
+ strh r0, [r6, #2] @ movhi
+.L2063:
+ cmp r8, #0
+ blt .L2068
ldrh r3, [r6]
- cmp r3, r8
- bne .L2086
-.L2090:
- ldrh r2, [r6, #10]
- ldrh r0, [r6, #12]
- ldr r3, .L2108+4
- strh r2, [r5, #6] @ movhi
- movw r2, #65535
- cmp r0, r2
- bne .L2087
- b .L2088
-.L2086:
- sub r7, r7, #1
- uxth r7, r7
- b .L2085
-.L2087:
- ldr r2, [r3, #2316]
- cmp r0, r2
- beq .L2088
- movw r1, #2330
- ldrh r3, [r3, r1]
- mov r3, r3, lsr #2
+ mov r2, #1
+ mov r1, r2
+ mov r0, r9
+ orr r3, r8, r3, lsl #10
+ str r3, [r4, #1764]
+ ldr r3, [r4, #-524]
+ str r3, [r4, #1768]
+ bl FlashReadPages
+ ldr r3, [r4, #1760]
+ cmn r3, #1
+ beq .L2064
+ ldrh r3, [r7]
+ cmp r3, r10
+ bne .L2064
+.L2068:
+ ldrh r3, [r7, #10]
+ ldrh r0, [r7, #12]
+ strh r3, [r6, #6] @ movhi
+ movw r3, #65535
cmp r0, r3
- cmpcc r2, r3
- bcs .L2088
- bl FtlSysBlkNumInit
-.L2088:
- ldr r6, .L2108+20
+ bne .L2065
+.L2066:
+ ldr r6, .L2085+20
mov r5, #0
- ldr r8, .L2108+24
+ ldr r8, .L2085+24
sub r7, r6, #134
-.L2091:
+.L2069:
ldrh r3, [r7]
cmp r5, r3
- bcs .L2107
- ldrh r2, [r8]
- ldr r1, [r4, #1760]
- ldr r0, [r6, #4]!
- mov r2, r2, asl #2
- mla r1, r5, r2, r1
- bl ftl_memcpy
- add r5, r5, #1
- b .L2091
-.L2107:
+ bcc .L2070
mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L2093:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L2056:
+ sub r6, r6, #1
+ uxth r6, r6
+ b .L2054
+.L2064:
+ sub r8, r8, #1
+ sxth r8, r8
+ b .L2063
+.L2065:
+ ldr r2, [r5, #2320]
+ cmp r0, r2
+ beq .L2066
+ movw r3, #2334
+ ldrh r3, [r5, r3]
+ lsr r3, r3, #2
+ cmp r2, r3
+ cmpcc r0, r3
+ bcs .L2066
+ bl FtlSysBlkNumInit
+ b .L2066
+.L2070:
+ ldrh r2, [r8]
+ ldr r1, [r4, #1768]
+ ldr r0, [r6, #4]!
+ lsl r2, r2, #2
+ mla r1, r5, r2, r1
+ add r5, r5, #1
+ bl ftl_memcpy
+ b .L2069
+.L2071:
mvn r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L2109:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L2086:
.align 2
-.L2108:
+.L2085:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR0+2386
- .word .LANCHOR2+1752
- .word .LANCHOR0+2452
- .word .LANCHOR0+2476
+ .word .LANCHOR0+2388
+ .word .LANCHOR0+2456
+ .word .LANCHOR2+1760
+ .word .LANCHOR0+2480
.word .LANCHOR2-436
.fnend
.size FtlLoadBbt, .-FtlLoadBbt
.align 2
.global FtlScanSysBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlScanSysBlk, %function
FtlScanSysBlk:
.fnstart
- @ args = 0, pretend = 0, frame = 32
+ @ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r5, #0
- ldr r7, .L2196
- mov r1, r5
- ldr r4, .L2196+4
- .pad #36
- sub sp, sp, #36
- movw r6, #2408
- ldr r2, [r7, #2416]
- sub r3, r4, #388
+ mov r6, #0
+ ldr r5, .L2166
+ movw r3, #2438
+ mov r1, r6
+ .pad #28
+ sub sp, sp, #28
+ ldr r4, .L2166+4
+ movw r8, #2412
+ ldr r2, [r5, #2420]
+ strh r6, [r5, r3] @ movhi
+ sub r7, r4, #388
ldr r0, [r4, #-444]
- mov r8, r4
- strh r5, [r3] @ movhi
- movw r3, #2434
- mov r2, r2, asl #2
- strh r5, [r7, r3] @ movhi
+ strh r6, [r7] @ movhi
+ lsl r2, r2, #2
bl ftl_memset
- ldr r2, [r7, #2416]
- mov r1, r5
+ ldr r2, [r5, #2420]
+ mov r1, r6
ldr r0, [r4, #-472]
- mov r2, r2, asl #1
+ lsl r2, r2, #1
bl ftl_memset
- ldrh r2, [r7, r6]
- mov r1, r5
+ ldrh r2, [r5, r8]
+ mov r1, r6
ldr r0, [r4, #-460]
- mov r2, r2, asl #2
+ lsl r2, r2, #2
bl ftl_memset
- ldrh r2, [r7, r6]
- ldr r0, [r7, #2436]
- mov r1, r5
- mov r2, r2, asl #1
+ ldrh r2, [r5, r8]
+ mov r1, r6
+ ldr r0, [r5, #2440]
+ lsl r2, r2, #1
bl ftl_memset
- ldr r0, .L2196+8
- mov r1, #255
+ sub r0, r4, #3296
mov r2, #16
+ mov r1, #255
+ sub r0, r0, #4
bl ftl_memset
- movw r3, #2328
- ldrh r3, [r7, r3]
- str r7, [sp, #16]
- mov r7, r4
- str r3, [sp, #4]
-.L2111:
- ldr r3, .L2196+12
- ldr r2, [sp, #4]
- ldr r1, .L2196
+ movw r3, #2332
+ str r7, [sp]
+ ldrh fp, [r5, r3]
+ str r5, [sp, #4]
+.L2088:
+ ldr r3, .L2166+8
+ ldr r2, .L2166
ldrh r3, [r3]
- cmp r3, r2
- mov r0, r1
- bls .L2152
- add r3, r1, #2320
- add r1, r1, #2400
- ldr r0, [r4, #-2692]
- mov r5, #0
- ldrh ip, [r3]
- sub r6, r1, #52
- ldr r3, [r4, #-536]
- mov fp, r5
- ldr r2, [r4, #-2696]
- mov r9, #36
+ cmp r3, fp
+ bls .L2128
+ ldr r1, [r4, #-2692]
+ mov r6, #0
+ ldr r3, .L2166+12
+ mov r5, r6
+ ldr r7, [r4, #-536]
+ mov r8, #36
+ str r1, [sp, #8]
+ ldr r1, .L2166+16
+ ldrh r2, [r3]
+ ldr r3, [r4, #-2696]
ldrh r10, [r1]
- str r0, [sp, #8]
-.L2153:
- uxth r1, r5
- cmp r1, ip
- bcs .L2191
- ldr r1, [sp, #4]
- ldrb r0, [r6, r5] @ zero_extendqisi2
- str r2, [sp, #28]
- str r3, [sp, #24]
- str ip, [sp, #20]
+ sub r9, r1, #52
+ b .L2129
+.L2090:
+ mov r1, fp
+ ldrb r0, [r9, r6] @ zero_extendqisi2
+ str r3, [sp, #20]
+ str r2, [sp, #16]
bl V2P_block
str r0, [sp, #12]
bl FtlBbmIsBadBlock
cmp r0, #0
+ ldr r2, [sp, #16]
+ ldr r3, [sp, #20]
+ bne .L2089
ldr r1, [sp, #12]
- ldr ip, [sp, #20]
- ldr r3, [sp, #24]
- ldr r2, [sp, #28]
- bne .L2112
- mla r0, r9, fp, r3
- mov r1, r1, asl #10
- stmib r0, {r1, r2}
- mul r1, r10, fp
- add lr, r1, #3
- cmp r1, #0
- movlt r1, lr
- ldr lr, [sp, #8]
- bic r1, r1, #3
- add r1, lr, r1
- str r1, [r0, #12]
- add r0, fp, #1
- uxth fp, r0
-.L2112:
+ mla r0, r8, r5, r7
+ lsl r1, r1, #10
+ stmib r0, {r1, r3}
+ mul r1, r10, r5
add r5, r5, #1
- b .L2153
-.L2191:
- cmp fp, #0
- beq .L2115
- ldr r0, [r4, #-536]
- mov r1, fp
+ uxth r5, r5
+ add ip, r1, #3
+ cmp r1, #0
+ movlt r1, ip
+ ldr ip, [sp, #8]
+ bic r1, r1, #3
+ add r1, ip, r1
+ str r1, [r0, #12]
+.L2089:
+ add r6, r6, #1
+.L2129:
+ uxth r1, r6
+ cmp r2, r1
+ bhi .L2090
+ cmp r5, #0
+ bne .L2091
+.L2127:
+ add r3, fp, #1
+ uxth fp, r3
+ b .L2088
+.L2091:
+ mov r8, #0
mov r2, #1
+ mov r1, r5
+ mov r0, r7
bl FlashReadPages
- mov r3, #0
-.L2189:
- str r3, [sp, #8]
- ldrh r3, [sp, #8]
- cmp r3, fp
- bcs .L2115
- ldr r3, [sp, #8]
+.L2092:
+ uxth r3, r8
+ cmp r5, r3
+ bls .L2127
mov r9, #36
- mul r9, r9, r3
ldr r3, [r4, #-536]
+ mul r9, r9, r8
add r2, r3, r9
ldr r3, [r3, r9]
- ldr r5, [r2, #4]
+ ldr r6, [r2, #4]
+ ldr r7, [r2, #12]
cmn r3, #1
- ldr r6, [r2, #12]
- ubfx r5, r5, #10, #16
- bne .L2118
+ ubfx r6, r6, #10, #16
+ bne .L2095
mov r10, #16
- movw ip, #65535
-.L2117:
+.L2097:
ldr r0, [r4, #-536]
- mov r1, #1
- mov r2, r1
- str ip, [sp, #12]
+ mov r2, #1
+ mov r1, r2
add r0, r0, r9
ldr r3, [r0, #4]
add r3, r3, #1
str r3, [r0, #4]
bl FlashReadPages
- ldrh r3, [r6]
- ldr ip, [sp, #12]
- cmp r3, ip
- ldreq r3, [r8, #-536]
- mvneq r2, #0
- streq r2, [r3, r9]
- beq .L2118
-.L2119:
- ldr r3, [r7, #-536]
+ ldrh r3, [r7]
+ movw r2, #65535
+ cmp r3, r2
+ ldr r3, [r4, #-536]
+ bne .L2094
+ mvn r2, #0
+ str r2, [r3, r9]
+ ldr r3, [r4, #-536]
+ ldr r3, [r3, r9]
+ cmp r3, r2
+ beq .L2096
+.L2095:
+ ldr r2, [r4, #-3332]
+ ldr r3, [r7, #4]
+ cmn r2, #1
+ beq .L2098
+ cmp r2, r3
+ bhi .L2099
+.L2098:
+ cmn r3, #1
+ addne r2, r3, #1
+ strne r2, [r4, #-3332]
+.L2099:
+ ldrh r2, [r7]
+ movw r1, #61604
+ cmp r2, r1
+ beq .L2101
+ bhi .L2102
+ movw r3, #61574
+ cmp r2, r3
+ beq .L2103
+.L2100:
+ add r8, r8, #1
+ b .L2092
+.L2094:
ldr r3, [r3, r9]
cmn r3, #1
- bne .L2118
+ bne .L2095
sub r10, r10, #1
uxth r10, r10
cmp r10, #0
- bne .L2117
-.L2118:
- ldr r3, [r7, #-536]
- ldr r3, [r3, r9]
- cmn r3, #1
- beq .L2121
- ldr r2, [r7, #-3332]
- ldr r3, [r6, #4]
- cmn r2, #1
- beq .L2122
- cmp r2, r3
- bhi .L2123
-.L2122:
- cmn r3, #1
- addne r2, r3, #1
- strne r2, [r8, #-3332]
-.L2123:
- ldrh r2, [r6]
- movw r1, #61604
- cmp r2, r1
- beq .L2125
- bhi .L2126
- movw r3, #61574
- cmp r2, r3
- bne .L2124
- ldr r2, .L2196+16
- ldr lr, [r8, #-460]
- ldrh ip, [r2]
- ldrh r1, [r2, #26]
- sub r0, ip, #1
- rsb r2, r1, r0
- str r2, [sp, #12]
- uxth r3, r0
- b .L2139
-.L2126:
+ bne .L2097
+.L2096:
+ ldr r3, .L2166
+ ldrb r1, [r3, #152] @ zero_extendqisi2
+ cmp r1, #0
+ bne .L2165
+.L2125:
+ mov r0, r6
+ bl FtlFreeSysBlkQueueIn
+ b .L2100
+.L2102:
movw r3, #61634
cmp r2, r3
- beq .L2128
+ beq .L2104
movw r3, #65535
cmp r2, r3
- moveq r0, r5
- beq .L2190
- b .L2124
-.L2128:
- ldr r3, [sp, #16]
- ldr ip, .L2196+20
- ldr r9, [r4, #-444]
- ldr lr, [r3, #2416]
- ldrh r2, [ip]
- uxth r1, lr
- sub r3, r1, #1
- rsb r1, r2, r1
- sub r1, r1, #1
- uxth r3, r3
- sxth r1, r1
- str r1, [sp, #20]
-.L2130:
- ldr r1, [sp, #20]
- sxth r0, r3
- cmp r0, r1
- ble .L2192
- mov r10, r0, asl #2
- ldr r1, [r6, #4]
- str r10, [sp, #12]
- ldr r10, [r9, r0, asl #2]
- cmp r1, r10
- bls .L2131
- ldr r1, [r9]
- cmp r1, #0
- bne .L2132
- cmp r2, lr
- addne r2, r2, #1
- strneh r2, [ip] @ movhi
-.L2132:
- uxth r9, r3
+ bne .L2100
+.L2165:
mov r1, #0
-.L2133:
- uxth r2, r1
- cmp r2, r9
- bcs .L2193
- ldr lr, [r7, #-444]
- sxth r2, r2
- add r1, r1, #1
- add r10, lr, r2, asl #2
- ldr r10, [r10, #4]
- str r10, [lr, r2, asl #2]
- mov r2, r2, asl #1
- ldr lr, [r7, #-472]
- add r10, lr, r2
- ldrh r10, [r10, #2]
- strh r10, [lr, r2] @ movhi
- b .L2133
-.L2193:
+ b .L2125
+.L2104:
+ ldr r3, [sp, #4]
+ ldr r2, [sp]
+ ldr ip, [r4, #-444]
+ ldr r0, [r3, #2420]
+ ldrh r2, [r2]
+ uxth r1, r0
+ sub r3, r1, #1
+ sub r1, r1, r2
+ sub r1, r1, #1
+ sxth r3, r3
+ sxth r1, r1
+.L2106:
+ cmp r3, r1
+ bgt .L2112
+ cmp r3, #0
+ bge .L2142
+ b .L2100
+.L2112:
+ ldr r10, [r7, #4]
+ lsl lr, r3, #2
+ ldr r9, [ip, r3, lsl #2]
+ cmp r10, r9
+ bls .L2107
+ ldr r1, [ip]
+ cmp r1, #0
+ bne .L2108
+ cmp r0, r2
+ ldrne r1, .L2166+20
+ addne r2, r2, #1
+ strhne r2, [r1] @ movhi
+.L2108:
+ uxth ip, r3
+ mov r1, #0
+.L2109:
+ uxth r0, r1
+ sxth r2, r1
+ cmp r0, ip
+ bcc .L2110
+ ldr r1, [r7, #4]
+ cmp r3, #0
ldr r2, [r4, #-444]
- mov r0, r0, asl #1
- ldr r1, [r6, #4]
- ldr lr, [sp, #12]
str r1, [r2, lr]
- ldr r2, [r4, #-472]
- strh r5, [r2, r0] @ movhi
- sxth r0, r3
- cmp r0, #0
- bge .L2135
- b .L2124
-.L2131:
- sub r3, r3, #1
- uxth r3, r3
- b .L2130
-.L2192:
- cmp r0, #0
- bge .L2166
- b .L2124
-.L2135:
- ldr r1, .L2196
- ldrh r2, [ip]
- ldr r1, [r1, #2416]
- rsb r1, r2, r1
+ lsl r2, r3, #1
+ ldr r1, [r4, #-472]
+ strh r6, [r1, r2] @ movhi
+ blt .L2100
+ ldr r2, [sp]
+ ldr r1, .L2166
+ ldrh r2, [r2]
+ ldr r1, [r1, #2420]
+ sub r1, r1, r2
sub r1, r1, #1
sxth r1, r1
- cmp r0, r1
- bgt .L2124
-.L2166:
- add r2, r2, #1
- ldr r1, [r6, #4]
- strh r2, [ip] @ movhi
- sxth r3, r3
- ldr r2, [r4, #-444]
- str r1, [r2, r3, asl #2]
- mov r3, r3, asl #1
- ldr r2, [r4, #-472]
- b .L2187
-.L2145:
- ldr r9, [lr, r2, asl #2]
- mov r10, r2, asl #2
- ldr r0, [r6, #4]
- cmp r0, r9
- bhi .L2194
- sub r3, r3, #1
- uxth r3, r3
-.L2139:
- ldr r0, [sp, #12]
- sxth r2, r3
- cmp r2, r0
- bgt .L2145
- b .L2144
-.L2194:
- ldr r0, [lr]
- cmp r0, #0
- bne .L2141
- cmp r1, ip
- addne r1, r1, #1
- ldrne r0, .L2196+24
- strneh r1, [r0] @ movhi
-.L2141:
- uxth lr, r3
- mov r0, #0
+ cmp r3, r1
+ bgt .L2100
.L2142:
- uxth r1, r0
- cmp r1, lr
- bcs .L2195
- ldr ip, [r4, #-460]
- sxth r1, r1
- add r0, r0, #1
- add r9, ip, r1, asl #2
+ ldr r1, [sp]
+ add r2, r2, #1
+ strh r2, [r1] @ movhi
+ ldr r2, [r4, #-444]
+ ldr r1, [r7, #4]
+ str r1, [r2, r3, lsl #2]
+ lsl r3, r3, #1
+ ldr r2, [r4, #-472]
+.L2163:
+ strh r6, [r2, r3] @ movhi
+ b .L2100
+.L2110:
+ ldr r0, [r4, #-444]
+ add r1, r1, #1
+ add r9, r0, r2, lsl #2
ldr r9, [r9, #4]
- str r9, [ip, r1, asl #2]
- mov r1, r1, asl #1
- ldr ip, .L2196
- ldr ip, [ip, #2436]
- add r9, ip, r1
+ str r9, [r0, r2, lsl #2]
+ lsl r2, r2, #1
+ ldr r0, [r4, #-472]
+ add r9, r0, r2
ldrh r9, [r9, #2]
- strh r9, [ip, r1] @ movhi
- b .L2142
-.L2195:
- ldr r1, [r8, #-460]
- mov r2, r2, asl #1
- ldr r0, [r6, #4]
- str r0, [r1, r10]
- ldr r1, .L2196
- ldr r1, [r1, #2436]
- strh r5, [r1, r2] @ movhi
-.L2144:
+ strh r9, [r0, r2] @ movhi
+ b .L2109
+.L2107:
+ sub r3, r3, #1
sxth r3, r3
+ b .L2106
+.L2103:
+ ldr r3, .L2166+24
+ ldr r1, .L2166+28
+ ldr lr, [r4, #-460]
+ ldrh r2, [r3]
+ ldrh r1, [r1]
+ sub r0, r2, #1
+ sxth r3, r0
+ sub r0, r0, r1
+.L2115:
+ cmp r3, r0
+ ble .L2120
+ ldr r10, [r7, #4]
+ lsl ip, r3, #2
+ ldr r9, [lr, r3, lsl #2]
+ cmp r10, r9
+ bls .L2116
+ sub r2, r2, r1
+ ldr r0, [lr]
+ clz r2, r2
+ uxth r9, r3
+ lsr r2, r2, #5
+ cmp r0, #0
+ orrne r2, r2, #1
+ ldr r0, .L2166
+ cmp r2, #0
+ ldreq r2, .L2166+28
+ addeq r1, r1, #1
+ strheq r1, [r2] @ movhi
+ mov r1, #0
+.L2118:
+ uxth lr, r1
+ sxth r2, r1
+ cmp lr, r9
+ bcc .L2119
+ ldr r1, [r7, #4]
+ ldr r2, [r4, #-460]
+ str r1, [r2, ip]
+ lsl r2, r3, #1
+ ldr r1, [r0, #2440]
+ strh r6, [r1, r2] @ movhi
+.L2120:
cmp r3, #0
- blt .L2124
- ldr r0, .L2196+24
+ blt .L2100
+ ldr r0, .L2166+28
ldrh r2, [r0, #-26]
ldrh r1, [r0]
sub r2, r2, #1
- rsb r2, r1, r2
+ sub r2, r2, r1
sxth r2, r2
cmp r3, r2
- bgt .L2124
+ bgt .L2100
add r1, r1, #1
- ldr r2, [r8, #-460]
+ ldr r2, [r4, #-460]
strh r1, [r0] @ movhi
- ldr r1, [r6, #4]
- str r1, [r2, r3, asl #2]
- mov r3, r3, asl #1
- ldr r2, .L2196
- ldr r2, [r2, #2436]
-.L2187:
- strh r5, [r2, r3] @ movhi
- b .L2124
-.L2125:
- ldr r2, .L2196+8
+ ldr r1, [r7, #4]
+ str r1, [r2, r3, lsl #2]
+ lsl r3, r3, #1
+ ldr r2, [sp, #4]
+ ldr r2, [r2, #2440]
+ b .L2163
+.L2119:
+ ldr lr, [r4, #-460]
+ add r1, r1, #1
+ add r10, lr, r2, lsl #2
+ ldr r10, [r10, #4]
+ str r10, [lr, r2, lsl #2]
+ lsl r2, r2, #1
+ ldr lr, [r0, #2440]
+ add r10, lr, r2
+ ldrh r10, [r10, #2]
+ strh r10, [lr, r2] @ movhi
+ b .L2118
+.L2116:
+ sub r3, r3, #1
+ sxth r3, r3
+ b .L2115
+.L2101:
+ ldr r2, .L2166+32
movw r1, #65535
- ldrh r0, [r2]
+ mov r9, r2
+ ldrh r0, [r9], #4
cmp r0, r1
- streqh r5, [r2] @ movhi
- beq .L2188
+ strheq r6, [r2] @ movhi
+ beq .L2164
ldrh r0, [r2, #4]
cmp r0, r1
- beq .L2147
+ beq .L2123
mov r1, #1
bl FtlFreeSysBlkQueueIn
-.L2147:
- ldr r3, [r6, #4]
- ldr r2, [r8, #-3292]
+.L2123:
+ ldr r3, [r7, #4]
+ ldr r2, [r4, #-3292]
cmp r2, r3
- ldr r3, .L2196+8
- strcsh r5, [r3, #4] @ movhi
- bcs .L2124
- ldrh r2, [r3]
- strh r5, [r3] @ movhi
- strh r2, [r3, #4] @ movhi
- ldr r3, [r6, #4]
-.L2188:
- str r3, [r7, #-3292]
- b .L2124
-.L2121:
- ldr r3, .L2196
- mov r0, r5
- ldrb r1, [r3, #144] @ zero_extendqisi2
- cmp r1, #0
- beq .L2149
-.L2190:
- mov r1, #0
-.L2149:
- bl FtlFreeSysBlkQueueIn
-.L2124:
- ldr r3, [sp, #8]
- add r3, r3, #1
- b .L2189
-.L2115:
- ldr r3, [sp, #4]
- add r5, r3, #1
- uxth r3, r5
- str r3, [sp, #4]
- b .L2111
-.L2152:
- ldr r3, .L2196+4
- ldr ip, [r3, #-472]
- ldrh r2, [ip]
- cmp r2, #0
- beq .L2154
-.L2157:
- ldr r0, [r0, #2436]
- ldr r3, .L2196
- ldrh r2, [r0]
- cmp r2, #0
- beq .L2155
- b .L2178
-.L2154:
- sub r3, r3, #388
- ldrh r3, [r3]
+ strhcs r6, [r9] @ movhi
+ bcs .L2100
+ ldrh r3, [r9, #-4]
+ strh r6, [r9, #-4] @ movhi
+ strh r3, [r9] @ movhi
+ ldr r3, [r7, #4]
+.L2164:
+ str r3, [r4, #-3292]
+ b .L2100
+.L2128:
+ ldr r0, [r4, #-472]
+ ldrh r3, [r0]
cmp r3, #0
- ldrne lr, [r1, #2416]
- beq .L2157
-.L2158:
- uxth r3, r2
- sxth r1, r3
- cmp r1, lr
- bcs .L2157
- mov r5, r1, asl #1
- add r2, r2, #1
- ldrh r5, [ip, r5]
- cmp r5, #0
- beq .L2158
- mov r6, #0
-.L2159:
- ldr ip, [r0, #2416]
- sxth r2, r3
- cmp r2, ip
- bcs .L2157
- ldr lr, [r4, #-472]
- mov ip, r2, asl #1
- rsb r5, r1, r2
- add r3, r3, #1
- ldrh r8, [lr, ip]
- mov r7, r5, asl #1
- uxth r3, r3
- strh r8, [lr, r7] @ movhi
- ldr lr, [r4, #-444]
- ldr r2, [lr, r2, asl #2]
- str r2, [lr, r5, asl #2]
- ldr r2, [r4, #-472]
- strh r6, [r2, ip] @ movhi
- b .L2159
-.L2155:
- movw r1, #2434
- ldrh r1, [r3, r1]
+ beq .L2130
+.L2133:
+ ldr r0, [r2, #2440]
+ ldrh r1, [r0]
cmp r1, #0
- movwne r1, #2408
- ldrneh ip, [r3, r1]
- beq .L2178
-.L2162:
- uxth r3, r2
+ beq .L2131
+.L2153:
+ mov r0, #0
+ add sp, sp, #28
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2130:
+ ldr r1, .L2166+20
+ ldrh r1, [r1]
+ cmp r1, #0
+ ldrne ip, [r2, #2420]
+ beq .L2133
+.L2134:
sxth r1, r3
cmp r1, ip
- bge .L2178
- mov lr, r1, asl #1
- add r2, r2, #1
+ bcs .L2133
+ lsl lr, r1, #1
+ add r3, r3, #1
ldrh lr, [r0, lr]
cmp lr, #0
- beq .L2162
- ldr r0, .L2196
- mov r7, #0
- ldr r6, .L2196+16
-.L2163:
- ldrh ip, [r6]
- sxth r2, r3
- cmp r2, ip
- bge .L2178
- ldr lr, [r0, #2436]
- mov ip, r2, asl #1
- rsb r5, r1, r2
+ beq .L2134
+ mov r3, r1
+ mov r5, #0
+.L2135:
+ ldr r0, [r2, #2420]
+ cmp r3, r0
+ bcs .L2133
+ ldr ip, [r4, #-472]
+ lsl r0, r3, #1
+ sub lr, r3, r1
+ lsl r6, lr, #1
+ ldrh r7, [ip, r0]
+ strh r7, [ip, r6] @ movhi
+ ldr ip, [r4, #-444]
+ ldr r6, [ip, r3, lsl #2]
add r3, r3, #1
- ldrh r9, [lr, ip]
- mov r8, r5, asl #1
- uxth r3, r3
- strh r9, [lr, r8] @ movhi
- ldr lr, [r4, #-460]
- ldr r2, [lr, r2, asl #2]
- str r2, [lr, r5, asl #2]
- ldr r2, [r0, #2436]
- strh r7, [r2, ip] @ movhi
- b .L2163
-.L2178:
- mov r0, #0
- add sp, sp, #36
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2197:
+ sxth r3, r3
+ str r6, [ip, lr, lsl #2]
+ ldr ip, [r4, #-472]
+ strh r5, [ip, r0] @ movhi
+ b .L2135
+.L2131:
+ movw r3, #2438
+ ldrh r3, [r2, r3]
+ cmp r3, #0
+ movwne r3, #2412
+ ldrhne ip, [r2, r3]
+ beq .L2153
+.L2138:
+ sxth r3, r1
+ cmp r3, ip
+ mov lr, r3
+ bge .L2153
+ lsl r5, r3, #1
+ add r1, r1, #1
+ ldrh r5, [r0, r5]
+ cmp r5, #0
+ beq .L2138
+ ldr r5, .L2166+24
+ mov r6, #0
+.L2139:
+ ldrh r1, [r5]
+ cmp r3, r1
+ bge .L2153
+ ldr r0, [r2, #2440]
+ lsl r1, r3, #1
+ sub ip, r3, lr
+ lsl r7, ip, #1
+ ldrh r8, [r0, r1]
+ strh r8, [r0, r7] @ movhi
+ ldr r0, [r4, #-460]
+ ldr r7, [r0, r3, lsl #2]
+ add r3, r3, #1
+ sxth r3, r3
+ str r7, [r0, ip, lsl #2]
+ ldr r0, [r2, #2440]
+ strh r6, [r0, r1] @ movhi
+ b .L2139
+.L2167:
.align 2
-.L2196:
+.L2166:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR2-3300
- .word .LANCHOR0+2330
- .word .LANCHOR0+2408
+ .word .LANCHOR0+2334
+ .word .LANCHOR0+2324
+ .word .LANCHOR0+2402
.word .LANCHOR2-388
- .word .LANCHOR0+2434
+ .word .LANCHOR0+2412
+ .word .LANCHOR0+2438
+ .word .LANCHOR2-3300
.fnend
.size FtlScanSysBlk, .-FtlScanSysBlk
.align 2
.global FtlLoadSysInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadSysInfo, %function
FtlLoadSysInfo:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r1, #0
- ldr r4, .L2227
+ ldr r4, .L2197
.pad #36
sub sp, sp, #36
- ldr r6, .L2227+4
- sub r7, r4, #3296
+ ldr r5, .L2197+4
ldr r3, [r4, #-524]
- ldr r0, [r4, #-3544]
- str r3, [r4, #1760]
+ sub r7, r4, #3296
+ ldr r0, [r4, #-3540]
+ str r3, [r4, #1768]
ldr r3, [r4, #-500]
- str r3, [r4, #1764]
- movw r3, #2328
- ldrh r2, [r6, r3]
- mov r2, r2, asl #1
+ str r3, [r4, #1772]
+ movw r3, #2332
+ ldrh r2, [r5, r3]
+ lsl r2, r2, #1
bl ftl_memset
ldrh r0, [r7, #-4]
movw r3, #65535
cmp r0, r3
- bne .L2199
-.L2210:
+ bne .L2169
+.L2180:
mvn r0, #0
- b .L2200
-.L2199:
+.L2168:
+ add sp, sp, #36
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2169:
mov r1, #1
+ add fp, r5, #2400
bl FtlGetLastWrittenPage
- ldr r3, .L2227+8
- ldrh r9, [r7, #-4]
- mov r7, r4
- uxth r5, r0
+ ldrsh r9, [r7, #-4]
+ sub r8, r7, #4
+ sxth r6, r0
add r0, r0, #1
- strh r0, [r3, #2] @ movhi
-.L2201:
- sxth r3, r5
- cmp r3, #0
- blt .L2209
- sxth fp, r9
- mov r1, #1
- ldr r0, .L2227+12
- mov r2, r1
- orr r3, r3, fp, asl #10
- str r3, [r4, #1756]
+ strh r0, [r8, #2] @ movhi
+.L2171:
+ cmp r6, #0
+ blt .L2179
+ orr r3, r6, r9, lsl #10
+ mov r2, #1
+ mov r1, r2
+ ldr r0, .L2197+8
+ str r3, [r4, #1764]
ldr r3, [r4, #-524]
- str r3, [r4, #1760]
+ str r3, [r4, #1768]
bl FlashReadPages
- ldrb r3, [r6] @ zero_extendqisi2
+ ldrb r3, [r5, #36] @ zero_extendqisi2
cmp r3, #0
- beq .L2202
- ldr r8, [r7, #1764]
+ beq .L2172
+ ldr r8, [r4, #1772]
ldr r3, [r8, #12]
cmp r3, #0
- beq .L2202
- ldr r2, [r7, #1760]
- ldr r10, .L2227+16
str r3, [sp, #28]
+ beq .L2172
+ ldr r2, [r4, #1768]
+ ldrh r1, [fp]
mov r0, r2
str r2, [sp, #24]
- ldrh r1, [r10]
bl js_hash
ldr r3, [sp, #28]
cmp r3, r0
- beq .L2202
- cmp r5, #0
+ beq .L2172
+ cmp r6, #0
+ bne .L2173
+ mov r10, r7
ldr r2, [sp, #24]
- bne .L2203
- ldr ip, .L2227+8
- ldrh r1, [ip, #4]
- cmp fp, r1
- beq .L2203
- ldr r0, [r8]
- ldrh r1, [ip]
- str ip, [sp, #24]
- str r0, [sp]
- ldr r0, [r8, #4]
- str r0, [sp, #4]
- ldr r0, [r8, #8]
+ ldrh r1, [r10], #-4
+ cmp r9, r1
+ beq .L2173
+ ldr r2, [r2]
+ ldrh r1, [r7, #-4]
str r3, [sp, #12]
- str r0, [sp, #8]
- ldr r3, [r2]
- ldr r0, .L2227+20
- str r3, [sp, #16]
- ldr r2, [r7, #1752]
- ldr r3, [r7, #1756]
+ str r2, [sp, #16]
+ ldr r3, [r8, #8]
+ ldr r2, [r4, #1760]
+ ldr r0, .L2197+12
+ str r3, [sp, #8]
+ ldr r3, [r8, #4]
+ str r3, [sp, #4]
+ ldr r3, [r8]
+ str r3, [sp]
+ ldr r3, [r4, #1764]
bl printk
- ldrh r5, [r10, #-8]
- ldr ip, [sp, #24]
- ldrh r9, [ip, #4]
- b .L2205
-.L2203:
+ ldr r3, .L2197+16
+ ldrsh r9, [r10, #4]
+ ldrh r6, [r3]
+.L2175:
+ sub r6, r6, #1
+ sxth r6, r6
+ b .L2171
+.L2173:
mvn r3, #0
- str r3, [r4, #1752]
-.L2202:
- ldr r3, [r4, #1752]
+ str r3, [r4, #1760]
+.L2172:
+ ldr r3, [r4, #1760]
cmn r3, #1
- beq .L2205
- ldr r3, [r7, #-524]
- ldr r2, .L2227+24
+ beq .L2175
+ ldr r3, [r4, #-524]
+ ldr r2, .L2197+20
ldr r3, [r3]
cmp r3, r2
- bne .L2205
- ldr r3, [r7, #-500]
+ bne .L2175
+ ldr r3, [r4, #-500]
ldrh r2, [r3]
movw r3, #61604
cmp r2, r3
- bne .L2205
-.L2209:
- ldr r5, .L2227
+ bne .L2175
+.L2179:
mov r2, #48
- ldr r1, [r4, #1760]
- movw r8, #2328
- sub r0, r5, #3600
- ldr r7, .L2227+4
+ ldr r1, [r4, #1768]
+ movw r6, #2332
+ ldr r0, .L2197+24
bl ftl_memcpy
- ldrh r2, [r6, r8]
- ldr r1, [r4, #1760]
- ldr r0, [r4, #-3544]
+ ldrh r2, [r5, r6]
+ ldr r1, [r4, #1768]
+ ldr r0, [r4, #-3540]
+ lsl r2, r2, #1
add r1, r1, #48
- mov r2, r2, asl #1
bl ftl_memcpy
- ldrh r2, [r6, r8]
- ldr r1, [r4, #1760]
- ldr r0, [r4, #-3368]
- mov r3, r2, asl #1
- mov r2, r2, lsr #3
- add r3, r3, #51
+ ldrh r1, [r5, r6]
+ ldr r3, [r4, #1768]
+ ldr r0, [r5, #32]
+ lsr r2, r1, #3
+ lsl r1, r1, #1
+ add r1, r1, #51
add r2, r2, #4
- bic r3, r3, #3
- add r1, r1, r3
+ bic r1, r1, #3
+ add r1, r3, r1
bl ftl_memcpy
- add r3, r7, #2432
- ldrh r3, [r3]
+ movw r3, #2436
+ ldrh r3, [r5, r3]
cmp r3, #0
- beq .L2207
- ldrh r2, [r7, r8]
- ldr r1, [r5, #1760]
- ldr r0, [r5, #-448]
- mov r3, r2, lsr #3
- add r3, r3, r2, asl #1
- movw r2, #2424
- ldrh r2, [r7, r2]
+ beq .L2177
+ ldrh r1, [r5, r6]
+ movw r3, #2428
+ ldrh r2, [r5, r3]
+ ldr r0, [r4, #-448]
+ lsr r3, r1, #3
+ lsl r2, r2, #2
+ add r3, r3, r1, lsl #1
+ ldr r1, [r4, #1768]
add r3, r3, #52
ubfx r3, r3, #2, #14
- mov r2, r2, asl #2
- add r1, r1, r3, asl #2
+ add r1, r1, r3, lsl #2
bl ftl_memcpy
- b .L2207
-.L2205:
- sub r5, r5, #1
- uxth r5, r5
- b .L2201
-.L2207:
- ldr r2, [r4, #-3600]
- ldr r3, .L2227+24
- ldr r5, .L2227
+.L2177:
+ ldr r2, [r4, #-3596]
+ ldr r3, .L2197+20
cmp r2, r3
- bne .L2210
- sub r7, r5, #3600
- movw r1, #2342
- ldrb r0, [r5, #-3590] @ zero_extendqisi2
- add r3, r7, #300
- ldrh r1, [r6, r1]
- sub r8, r5, #3296
- ldrh r2, [r7, #8]
- cmp r0, r1
- strh r2, [r3, #6] @ movhi
- ldr r3, .L2227+4
- bne .L2210
- movw r1, #2388
- movw r0, #2394
- ldrh r1, [r3, r1]
- ldrh r0, [r3, r0]
- add r3, r3, #2320
- str r2, [r5, #1788]
- mul r1, r2, r1
- str r1, [r3, #128]
- mul r1, r0, r1
- str r1, [r3, #108]
- ldr r1, .L2227+28
- ldrh r0, [r1, #6]
- ldr r1, [r3, #12]
- rsb r0, r0, r1
- ldrh r1, [r3]
- rsb r0, r2, r0
+ bne .L2180
+ ldr r6, .L2197+24
+ movw r3, #2346
+ ldrb r1, [r4, #-3586] @ zero_extendqisi2
+ ldrh r3, [r5, r3]
+ ldrh r2, [r6, #8]
+ cmp r1, r3
+ strh r2, [r7, #2] @ movhi
+ bne .L2180
+ movw r3, #2390
+ movw r1, #2396
+ ldrh r3, [r5, r3]
+ ldrh r1, [r5, r1]
+ ldr r0, [r5, #2336]
+ str r2, [r4, #1796]
+ mul r3, r2, r3
+ str r3, [r5, #2452]
+ mul r3, r3, r1
+ str r3, [r5, #2432]
+ ldr r3, .L2197+28
+ ldrh r3, [r3, #6]
+ sub r0, r0, r3
+ movw r3, #2324
+ ldrh r1, [r5, r3]
+ sub r0, r0, r2
bl __aeabi_uidiv
- sub r3, r5, #3520
- add r2, r7, #76
- sub lr, r5, #3280
- sub ip, r5, #3424
- strh r0, [r8, #-8] @ movhi
- mov r8, ip
- ldrh r0, [r7, #14]
- strh r0, [r3, #-4] @ movhi
- ldrh r3, [r7, #16]
- mov r1, r3, lsr #6
+ ldrh r3, [r6, #16]
+ add r2, r6, #76
+ mov r5, r2
+ strh r0, [r7, #-8] @ movhi
+ ldrh r0, [r6, #14]
+ add r7, r2, #240
+ lsr r1, r3, #6
and r3, r3, #63
- strb r3, [r5, #-3518]
- ldrb r3, [r5, #-3589] @ zero_extendqisi2
- strh r1, [r7, #78] @ movhi
- ldrh r1, [r7, #18]
- strb r3, [r5, #-3516]
+ strb r3, [r4, #-3514]
+ strh r1, [r2, #2] @ movhi
+ ldrh r1, [r6, #18]
+ ldrb r3, [r4, #-3585] @ zero_extendqisi2
+ strh r0, [r2] @ movhi
+ strh r1, [r5, #48]! @ movhi
+ ldrh r1, [r6, #20]
+ strb r3, [r4, #-3512]
mvn r3, #0
- strh r3, [lr, #-4] @ movhi
+ strh r3, [r7, #-4] @ movhi
mov r3, #0
- strh r3, [r2, #242] @ movhi
- sub r2, r5, #3472
- strb r3, [r5, #-3278]
- strh r1, [r2, #-4] @ movhi
- ldrh r1, [r7, #20]
- strb r3, [r5, #-3276]
- str r3, [r5, #-3344]
- mov r6, r1, lsr #6
+ strh r3, [r2, #238] @ movhi
+ lsr ip, r1, #6
and r1, r1, #63
- strb r1, [r5, #-3470]
- ldrb r1, [r5, #-3588] @ zero_extendqisi2
- strh r6, [r2, #-2] @ movhi
+ strb r1, [r4, #-3466]
+ ldrb r1, [r4, #-3584] @ zero_extendqisi2
+ strh ip, [r5, #2] @ movhi
+ strb r3, [r4, #-3278]
+ strb r1, [r4, #-3464]
+ ldrh r1, [r6, #22]
+ strb r3, [r4, #-3276]
+ strh r1, [r2, #96]! @ movhi
+ ldrh r1, [r6, #24]
mov r6, r2
- strb r1, [r5, #-3468]
- ldrh r1, [r7, #22]
- strh r1, [ip, #-4] @ movhi
- ldrh r1, [r7, #24]
- mov r7, r1, lsr #6
+ lsr ip, r1, #6
and r1, r1, #63
- strb r1, [r5, #-3422]
- ldrb r1, [r5, #-3587] @ zero_extendqisi2
- strh r7, [r2, #46] @ movhi
- mov r7, lr
- strb r1, [r5, #-3420]
- str r3, [r5, #-3356]
- ldr r1, [r5, #-3568]
- str r3, [r5, #-3364]
- str r3, [r5, #-3348]
- str r3, [r5, #-3320]
- str r3, [r5, #-3312]
- str r3, [r5, #-3352]
- ldr r3, [r5, #-3560]
- str r1, [r5, #-3324]
- ldr r1, [r5, #-3332]
+ strb r1, [r4, #-3418]
+ ldrb r1, [r4, #-3583] @ zero_extendqisi2
+ strh ip, [r2, #2] @ movhi
+ strb r1, [r4, #-3416]
+ str r3, [r4, #-3344]
+ ldr r1, [r4, #-3564]
+ str r3, [r4, #-3356]
+ str r3, [r4, #-3364]
+ str r3, [r4, #-3348]
+ str r1, [r4, #-3324]
+ str r3, [r4, #-3320]
+ ldr r1, [r4, #-3332]
+ str r3, [r4, #-3312]
+ str r3, [r4, #-3352]
+ ldr r3, [r4, #-3556]
ldr r2, [r4, #-3328]
cmp r3, r1
- strhi r3, [r5, #-3332]
- ldr r3, [r4, #-3564]
+ strhi r3, [r4, #-3332]
+ ldr r3, [r4, #-3560]
cmp r3, r2
- ldrhi r2, .L2227
- strhi r3, [r2, #-3328]
+ strhi r3, [r4, #-3328]
movw r3, #65535
cmp r0, r3
- beq .L2213
- ldr r0, .L2227+32
+ beq .L2183
+ ldr r0, .L2197+32
bl make_superblock
-.L2213:
- ldrh r2, [r6, #-4]
+.L2183:
+ ldrh r2, [r5]
movw r3, #65535
cmp r2, r3
- beq .L2214
- ldr r0, .L2227+36
+ beq .L2184
+ ldr r0, .L2197+36
bl make_superblock
-.L2214:
- ldrh r2, [r8, #-4]
+.L2184:
+ ldrh r2, [r6]
movw r3, #65535
cmp r2, r3
- beq .L2215
- ldr r0, .L2227+40
+ beq .L2185
+ ldr r0, .L2197+40
bl make_superblock
-.L2215:
+.L2185:
ldrh r2, [r7, #-4]
movw r3, #65535
+ sub r0, r7, #4
cmp r2, r3
- beq .L2216
- ldr r0, .L2227+44
+ beq .L2186
bl make_superblock
-.L2216:
+.L2186:
mov r0, #0
-.L2200:
- add sp, sp, #36
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2228:
+ b .L2168
+.L2198:
.align 2
-.L2227:
+.L2197:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR2-3300
- .word .LANCHOR2+1752
- .word .LANCHOR0+2398
+ .word .LANCHOR2+1760
.word .LC109
+ .word .LANCHOR0+2392
.word 1179929683
- .word .LANCHOR0+2452
- .word .LANCHOR2-3524
- .word .LANCHOR2-3476
- .word .LANCHOR2-3428
- .word .LANCHOR2-3284
+ .word .LANCHOR2-3596
+ .word .LANCHOR0+2456
+ .word .LANCHOR2-3520
+ .word .LANCHOR2-3472
+ .word .LANCHOR2-3424
.fnend
.size FtlLoadSysInfo, .-FtlLoadSysInfo
.align 2
.global FtlDumpBlockInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlDumpBlockInfo, %function
FtlDumpBlockInfo:
.fnstart
- @ args = 0, pretend = 0, frame = 72
+ @ args = 0, pretend = 0, frame = 64
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2388
- ldr r5, .L2243
- .pad #100
- sub sp, sp, #100
+ movw r3, #2390
+ ldr r5, .L2211
+ .pad #92
+ sub sp, sp, #92
ubfx r0, r0, #10, #16
- mov r4, r1
- ldr r7, .L2243+4
- ldrh r9, [r5, r3]
+ mov r9, r1
+ ldr r7, .L2211+4
+ ldrh r8, [r5, r3]
bl P2V_block_in_plane
- ldr r1, .L2243+8
+ ldr r1, .L2211+8
mov r6, r0
- ldr r0, .L2243+12
+ ldr r0, .L2211+12
bl printk
- ldr r2, [r7, #-3544]
- mov r3, r6, asl #1
+ ldr r2, [r7, #-3540]
+ lsl r3, r6, #1
mov r1, r6
- ldr r0, .L2243+16
+ ldr r0, .L2211+16
ldrh r2, [r2, r3]
bl printk
- add r0, sp, #96
+ add r0, sp, #88
strh r6, [r0, #-48]! @ movhi
bl make_superblock
- ldrb r2, [r5, #144] @ zero_extendqisi2
- clz r3, r4
- cmp r2, #0
- mov r3, r3, lsr #5
- moveq r3, #0
+ ldrb r4, [r5, #152] @ zero_extendqisi2
+ str r7, [sp, #36]
+ adds r3, r4, #0
+ movne r3, #1
+ cmp r9, #0
+ movne r3, #0
cmp r3, #0
moveq r4, r3
- str r7, [sp, #44]
- beq .L2230
+ beq .L2200
mov r0, r6
bl ftl_get_blk_mode
cmp r0, #1
mov r4, r0
- movweq r3, #2390
- ldreqh r9, [r5, r3]
-.L2230:
- movw r3, #2388
- ldr r0, .L2243+20
- mov r1, r4
- mov r2, r9
- ldrh r3, [r5, r3]
+ movweq r3, #2392
+ ldrheq r8, [r5, r3]
+.L2200:
+ movw r3, #2390
mov r6, #0
+ mov r9, #36
+ ldrh r3, [r5, r3]
+ mov r2, r8
+ mov r1, r4
+ ldr r0, .L2211+20
bl printk
- ldr r8, .L2243+4
-.L2231:
- ldr r3, .L2243+24
- add r0, sp, #62
- movw lr, #65535
- mov r10, #36
+.L2201:
+ ldr r3, .L2211+24
+ add ip, sp, #54
+ movw r10, #65535
ldrh r3, [r3]
mov r7, r3
- ldr r3, [r8, #-536]
- str r3, [sp, #28]
- ldr r3, [r8, #-2696]
+ ldr r3, .L2211+4
+ ldr r2, [r3, #-2696]
+ ldr r0, [r3, #-536]
+ ldr r3, [r3, #-2692]
+ str r2, [sp, #24]
+ ldr r2, .L2211+28
str r3, [sp, #32]
- ldr r3, .L2243+28
- ldrh r2, [r3]
- ldrh ip, [r3, #2]
- str r2, [sp, #36]
- ldr r2, [r8, #-2692]
- str r2, [sp, #40]
+ ldrh r1, [r2]
+ ldrh lr, [r2, #2]
mov r2, #0
mov r5, r2
-.L2232:
+ str r1, [sp, #28]
+.L2202:
uxth r3, r2
- cmp r3, r7
- bcs .L2241
- ldrh r3, [r0, #2]!
- cmp r3, lr
- beq .L2233
- ldr r1, [sp, #28]
- orr r3, r6, r3, asl #10
- mla r1, r10, r5, r1
+ cmp r7, r3
+ bhi .L2204
+ ldr fp, .L2211+32
+ mov r10, #0
+ mov r2, r4
+ mov r1, r5
+ bl FlashReadPages
+.L2205:
+ uxth r3, r10
+ cmp r5, r3
+ bhi .L2206
+ add r6, r6, #1
+ uxth r6, r6
+ cmp r8, r6
+ bne .L2201
+.L2207:
+ mov r0, #0
+ add sp, sp, #92
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2204:
+ ldrh r3, [ip, #2]!
+ cmp r3, r10
+ beq .L2203
+ mla r1, r9, r5, r0
+ orr r3, r6, r3, lsl #10
str r3, [r1, #4]
- ldr r3, [sp, #36]
+ ldr r3, [sp, #28]
mul r3, r3, r5
+ add fp, r3, #3
+ cmp r3, #0
+ movlt r3, fp
+ ldr fp, [sp, #24]
+ bic r3, r3, #3
+ add r3, fp, r3
+ str r3, [r1, #8]
+ mul r3, lr, r5
+ add r5, r5, #1
+ uxth r5, r5
add fp, r3, #3
cmp r3, #0
movlt r3, fp
ldr fp, [sp, #32]
bic r3, r3, #3
add r3, fp, r3
- str r3, [r1, #8]
- mul r3, ip, r5
- add r5, r5, #1
- uxth r5, r5
- add fp, r3, #3
- cmp r3, #0
- movlt r3, fp
- ldr fp, [sp, #40]
- bic r3, r3, #3
- add r3, fp, r3
str r3, [r1, #12]
-.L2233:
+.L2203:
add r2, r2, #1
- b .L2232
-.L2241:
- ldr r0, [r8, #-536]
- mov r1, r5
- mov r2, r4
- mov r10, #0
- bl FlashReadPages
- mov fp, #36
-.L2235:
- uxth r3, r10
- cmp r3, r5
- bcs .L2242
- ldr r3, [sp, #44]
- mul r2, fp, r10
- ldrh r1, [sp, #48]
- ldr lr, [r3, #-536]
+ b .L2202
+.L2206:
+ ldr r3, [sp, #36]
+ mul r0, r9, r10
+ ldrh r1, [sp, #40]
add r10, r10, #1
- add ip, lr, r2
- ldr r3, [ip, #12]
- ldr r0, [ip, #8]
- ldr r7, [r3]
- str r7, [sp]
- ldr r7, [r3, #4]
- str r7, [sp, #4]
- ldr r7, [r3, #8]
- str r7, [sp, #8]
- ldr r3, [r3, #12]
- str r3, [sp, #12]
- ldr r3, [r0]
- str r3, [sp, #16]
- ldr r3, [r0, #4]
- ldr r0, .L2243+32
- str r3, [sp, #20]
- ldr r2, [lr, r2]
- ldr r3, [ip, #4]
+ ldr ip, [r3, #-536]
+ add r2, ip, r0
+ ldr lr, [r2, #8]
+ ldr r3, [r2, #12]
+ ldr r7, [lr, #4]
+ str r7, [sp, #20]
+ ldr lr, [lr]
+ str lr, [sp, #16]
+ ldr lr, [r3, #12]
+ str lr, [sp, #12]
+ ldr lr, [r3, #8]
+ str lr, [sp, #8]
+ ldr lr, [r3, #4]
+ str lr, [sp, #4]
+ ldr r3, [r3]
+ str r3, [sp]
+ ldr r3, [r2, #4]
+ ldr r2, [ip, r0]
+ mov r0, fp
bl printk
- b .L2235
-.L2242:
- add r6, r6, #1
- uxth r6, r6
- cmp r6, r9
- bne .L2231
-.L2237:
- mov r0, #0
- add sp, sp, #100
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2244:
+ b .L2205
+.L2212:
.align 2
-.L2243:
+.L2211:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR3+148
+ .word .LANCHOR3+141
.word .LC110
.word .LC111
.word .LC112
- .word .LANCHOR0+2320
- .word .LANCHOR0+2398
+ .word .LANCHOR0+2324
+ .word .LANCHOR0+2400
.word .LC113
.fnend
.size FtlDumpBlockInfo, .-FtlDumpBlockInfo
.align 2
.global FtlScanAllBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlScanAllBlock, %function
FtlScanAllBlock:
.fnstart
- @ args = 0, pretend = 0, frame = 64
+ @ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #92
- sub sp, sp, #92
- ldr r0, .L2260
- mov r7, #0
- ldr r1, .L2260+4
+ mov r6, #0
+ ldr r5, .L2224
+ .pad #84
+ sub sp, sp, #84
+ ldr r1, .L2224+4
+ ldr r0, .L2224+8
bl printk
- ldr r5, .L2260+8
- mov r6, r5
-.L2246:
- ldr r3, .L2260+12
- uxth r4, r7
+.L2214:
+ ldr r3, .L2224+12
+ uxth r0, r6
ldrh r3, [r3]
- cmp r3, r4
- bls .L2256
- add r8, sp, #88
- mov r0, r4
+ cmp r3, r0
+ bhi .L2222
+ mov r0, #0
+ add sp, sp, #84
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2222:
+ add r4, sp, #80
movw r9, #65535
+ strh r0, [r4, #-48]! @ movhi
mov r10, #36
- strh r4, [r8, #-48]! @ movhi
bl ftl_get_blk_mode
- ldr ip, [r5, #-3544]
- mov r2, r4, asl #1
- mov r1, r4
- ldrh r2, [ip, r2]
+ uxth r1, r6
+ ldr ip, [r5, #-3540]
mov r3, r0
- ldr r0, .L2260+16
+ ldr r0, .L2224+16
+ lsl r2, r1, #1
+ ldrh r2, [ip, r2]
bl printk
- mov r0, r8
+ mov r0, r4
bl make_superblock
- ldr r3, .L2260+20
- ldr lr, [r5, #-2692]
+ ldr r3, .L2224+20
+ add ip, sp, #46
+ ldr r0, [r5, #-536]
+ ldr r7, [r5, #-2692]
ldrh r2, [r3]
- ldrh ip, [r3, #78]
- ldrh r8, [r3, #80]
- str r2, [sp, #28]
- add r0, sp, #54
- ldr r2, [r5, #-536]
- str r2, [sp, #32]
+ ldrh lr, [r3, #76]
+ ldrh r8, [r3, #78]
+ str r2, [sp, #24]
ldr r2, [r5, #-2696]
- str r2, [sp, #36]
+ str r2, [sp, #28]
mov r2, #0
mov r4, r2
-.L2247:
- ldr r1, [sp, #28]
+.L2215:
+ ldr r1, [sp, #24]
uxth r3, r2
- cmp r3, r1
- bcs .L2257
- ldrh r3, [r0, #2]!
+ cmp r1, r3
+ bhi .L2217
+ ldr r9, .L2224+24
+ mov r7, #0
+ mov r8, #36
+ mov r2, #0
+ mov r1, r4
+ bl FlashReadPages
+.L2218:
+ uxth r3, r7
+ cmp r4, r3
+ bhi .L2219
+ ldr r9, .L2224+28
+ mov r7, #0
+ mov r8, #36
+ mov r2, #1
+ mov r1, r4
+ ldr r0, [r5, #-536]
+ bl FlashReadPages
+.L2220:
+ uxth r3, r7
+ cmp r4, r3
+ bhi .L2221
+ add r6, r6, #1
+ b .L2214
+.L2217:
+ ldrh r3, [ip, #2]!
cmp r3, r9
- beq .L2248
- ldr r1, [sp, #32]
- mov r3, r3, asl #10
- mla r1, r10, r4, r1
+ beq .L2216
+ mla r1, r10, r4, r0
+ lsl r3, r3, #10
str r3, [r1, #4]
- mul r3, ip, r4
+ mul r3, lr, r4
add fp, r3, #3
cmp r3, #0
movlt r3, fp
- ldr fp, [sp, #36]
+ ldr fp, [sp, #28]
bic r3, r3, #3
add r3, fp, r3
str r3, [r1, #8]
@@ -13213,673 +13684,764 @@
cmp r3, #0
movlt r3, fp
bic r3, r3, #3
- add r3, lr, r3
+ add r3, r7, r3
str r3, [r1, #12]
-.L2248:
+.L2216:
add r2, r2, #1
- b .L2247
-.L2257:
- ldr r0, [r6, #-536]
- mov r1, r4
- mov r2, #0
- mov r8, #0
- bl FlashReadPages
- mov r9, #36
-.L2250:
- uxth r3, r8
- cmp r3, r4
- bcs .L2258
- mul r2, r9, r8
- ldr lr, [r6, #-536]
- ldrh r1, [sp, #40]
- add r8, r8, #1
- add ip, lr, r2
- ldr r3, [ip, #12]
- ldr r0, [ip, #8]
- ldr r10, [r3]
- str r10, [sp]
- ldr r10, [r3, #4]
- str r10, [sp, #4]
- ldr r10, [r3, #8]
- str r10, [sp, #8]
- ldr r3, [r3, #12]
- str r3, [sp, #12]
- ldr r3, [r0]
- str r3, [sp, #16]
- ldr r3, [r0, #4]
- ldr r0, .L2260+24
- str r3, [sp, #20]
- ldr r2, [lr, r2]
- ldr r3, [ip, #4]
- bl printk
- b .L2250
-.L2258:
- ldr r0, [r6, #-536]
- mov r1, r4
- mov r2, #1
- mov r8, #0
- bl FlashReadPages
- mov r9, #36
-.L2252:
- uxth r3, r8
- cmp r3, r4
- bcs .L2259
- mul r2, r9, r8
- ldr lr, [r6, #-536]
- ldrh r1, [sp, #40]
- add r8, r8, #1
- add ip, lr, r2
- ldr r3, [ip, #12]
- ldr r0, [ip, #8]
- ldr r10, [r3]
- str r10, [sp]
- ldr r10, [r3, #4]
- str r10, [sp, #4]
- ldr r10, [r3, #8]
- str r10, [sp, #8]
- ldr r3, [r3, #12]
- str r3, [sp, #12]
- ldr r3, [r0]
- str r3, [sp, #16]
- ldr r3, [r0, #4]
- ldr r0, .L2260+28
- str r3, [sp, #20]
- ldr r2, [lr, r2]
- ldr r3, [ip, #4]
- bl printk
- b .L2252
-.L2259:
+ b .L2215
+.L2219:
+ mul r0, r8, r7
+ ldr ip, [r5, #-536]
+ ldrh r1, [sp, #32]
add r7, r7, #1
- b .L2246
-.L2256:
- mov r0, #0
- add sp, sp, #92
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2261:
+ add r2, ip, r0
+ ldr lr, [r2, #8]
+ ldr r3, [r2, #12]
+ ldr r10, [lr, #4]
+ str r10, [sp, #20]
+ ldr lr, [lr]
+ str lr, [sp, #16]
+ ldr lr, [r3, #12]
+ str lr, [sp, #12]
+ ldr lr, [r3, #8]
+ str lr, [sp, #8]
+ ldr lr, [r3, #4]
+ str lr, [sp, #4]
+ ldr r3, [r3]
+ str r3, [sp]
+ ldr r3, [r2, #4]
+ ldr r2, [ip, r0]
+ mov r0, r9
+ bl printk
+ b .L2218
+.L2221:
+ mul r0, r8, r7
+ ldr ip, [r5, #-536]
+ ldrh r1, [sp, #32]
+ add r7, r7, #1
+ add r2, ip, r0
+ ldr lr, [r2, #8]
+ ldr r3, [r2, #12]
+ ldr r10, [lr, #4]
+ str r10, [sp, #20]
+ ldr lr, [lr]
+ str lr, [sp, #16]
+ ldr lr, [r3, #12]
+ str lr, [sp, #12]
+ ldr lr, [r3, #8]
+ str lr, [sp, #8]
+ ldr lr, [r3, #4]
+ str lr, [sp, #4]
+ ldr r3, [r3]
+ str r3, [sp]
+ ldr r3, [r2, #4]
+ ldr r2, [ip, r0]
+ mov r0, r9
+ bl printk
+ b .L2220
+.L2225:
.align 2
-.L2260:
- .word .LC110
- .word .LANCHOR3+168
+.L2224:
.word .LANCHOR2
- .word .LANCHOR0+2330
+ .word .LANCHOR3+158
+ .word .LC110
+ .word .LANCHOR0+2334
.word .LC114
- .word .LANCHOR0+2320
+ .word .LANCHOR0+2324
.word .LC115
.word .LC116
.fnend
.size FtlScanAllBlock, .-FtlScanAllBlock
.align 2
.global ftl_scan_all_ppa
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_scan_all_ppa, %function
ftl_scan_all_ppa:
.fnstart
- @ args = 0, pretend = 0, frame = 0
+ @ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, lr}
- movw r3, #2386
- ldr r6, .L2281
- .pad #24
- sub sp, sp, #24
- ldr r5, .L2281+4
- ldrh r4, [r6, r3]
+ ldr r3, .L2243
+ movw r2, #2388
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .pad #36
+ sub sp, sp, #36
+ ldr r5, .L2243+4
+ ldrh r4, [r3, r2]
+ add r10, r5, #1760
+ str r3, [sp, #28]
sub r4, r4, #16
-.L2263:
- ldr r7, .L2281+8
- ldrh r3, [r7]
+ lsl r9, r4, #10
+.L2227:
+ ldr r3, .L2243+8
+ ldrh r3, [r3]
cmp r4, r3
- bge .L2279
- uxth r8, r4
- mov r0, r8
+ blt .L2235
+ ldr r1, .L2243+12
+ ldr r0, .L2243+16
+ add sp, sp, #36
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ b printk
+.L2235:
+ uxth r7, r4
+ mov r0, r7
bl ftl_get_blk_mode
- ldrb r3, [r6, #144] @ zero_extendqisi2
+ ldr r3, [sp, #28]
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L2264
- ldrh r3, [r7, #-58]
+ beq .L2228
+ ldr r3, .L2243+20
+ ldrh r2, [r3]
+ cmp r4, r2
+ bge .L2229
+ ldrh r3, [r3, #72]
cmp r4, r3
- bge .L2265
- ldrh r3, [r7, #16]
- cmp r4, r3
- blt .L2265
-.L2264:
+ blt .L2229
+.L2228:
cmp r0, #1
- bne .L2266
-.L2265:
- ldr r3, .L2281+12
- mov r9, #-2147483648
- ldrh r7, [r3]
- b .L2267
-.L2266:
- ldr r3, .L2281+16
- mov r9, #0
- ldrh r7, [r3]
-.L2267:
+ bne .L2230
+.L2229:
+ ldr r3, .L2243+24
+ mov r8, #-2147483648
+ ldrh r6, [r3]
+.L2231:
+ mov r3, r8
+ mov r2, r6
mov r1, r4
- mov r2, r7
- mov r3, r9
- ldr r0, .L2281+20
+ ldr r0, .L2243+28
bl printk
- mov r0, r8
+ mov r0, r7
bl FtlBbmIsBadBlock
cmp r0, #0
- beq .L2268
- ldr r0, .L2281+24
+ beq .L2232
+ mov r3, r8
+ mov r2, r6
mov r1, r4
- mov r2, r7
- mov r3, r9
+ ldr r0, .L2243+32
bl printk
-.L2268:
- mov r10, r4, asl #10
+.L2232:
+ ldr fp, .L2243+36
+ mov r7, #0
+.L2233:
+ cmp r7, r6
+ bne .L2234
+ add r4, r4, #1
+ add r9, r9, #1024
+ b .L2227
+.L2230:
+ ldr r3, .L2243+40
mov r8, #0
-.L2269:
- cmp r8, r7
- beq .L2280
- add r3, r9, r10
+ ldrh r6, [r3]
+ b .L2231
+.L2234:
+ add r3, r8, r9
mov r2, #0
- add r3, r3, r8
- str r3, [r5, #1756]
- ldr r3, [r5, #-524]
+ add r3, r3, r7
mov r1, #1
- ldr r0, .L2281+28
- add r8, r8, #1
- str r2, [r5, #1752]
- str r3, [r5, #1760]
- ldr r3, [r5, #-500]
str r3, [r5, #1764]
+ mov r0, r10
+ ldr r3, [r5, #-524]
+ add r7, r7, #1
+ str r2, [r5, #1760]
+ str r3, [r5, #1768]
+ ldr r3, [r5, #-500]
+ str r3, [r5, #1772]
bl FlashReadPages
- ldr r3, [r5, #1764]
+ ldr r2, [r5, #1768]
+ mov r0, fp
+ ldr r3, [r5, #1772]
+ ldr r1, [r2, #4]
+ str r1, [sp, #16]
+ ldr r2, [r2]
+ ldr r1, [r5, #1764]
+ str r2, [sp, #12]
+ ldr r2, [r3, #12]
+ str r2, [sp, #8]
+ ldr r2, [r3, #8]
+ str r2, [sp, #4]
+ ldr r2, [r3, #4]
+ str r2, [sp]
ldr r2, [r5, #1760]
- ldr r0, .L2281+32
- ldr r1, [r3, #4]
- str r1, [sp]
- ldr r1, [r3, #8]
- str r1, [sp, #4]
- ldr r1, [r3, #12]
- str r1, [sp, #8]
- ldr r1, [r2]
- str r1, [sp, #12]
- ldr r2, [r2, #4]
- ldr r1, [r5, #1756]
- str r2, [sp, #16]
- ldr r2, [r5, #1752]
ldr r3, [r3]
bl printk
- b .L2269
-.L2280:
- add r4, r4, #1
- b .L2263
-.L2279:
- ldr r0, .L2281+36
- ldr r1, .L2281+40
- add sp, sp, #24
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
- b printk
-.L2282:
+ b .L2233
+.L2244:
.align 2
-.L2281:
+.L2243:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2386
- .word .LANCHOR0+2390
.word .LANCHOR0+2388
+ .word .LANCHOR3+174
+ .word .LC120
+ .word .LANCHOR0+2332
+ .word .LANCHOR0+2392
.word .LC117
.word .LC118
- .word .LANCHOR2+1752
.word .LC119
- .word .LC120
- .word .LANCHOR3+184
+ .word .LANCHOR0+2390
.fnend
.size ftl_scan_all_ppa, .-ftl_scan_all_ppa
.align 2
.global FlashProgPages
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashProgPages, %function
FlashProgPages:
.fnstart
- @ args = 0, pretend = 0, frame = 64
+ @ args = 0, pretend = 0, frame = 72
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #76
- sub sp, sp, #76
- ldr r6, .L2339
- mov r4, r0
- str r1, [sp, #8]
- mov r9, r2
- str r3, [sp, #20]
- ldr ip, [r6, #44]
- ldrb r7, [r6] @ zero_extendqisi2
+ .pad #84
+ sub sp, sp, #84
+ ldr r5, .L2298
+ str r1, [sp, #12]
+ ldr ip, [r5, #48]
+ ldrb r8, [r5, #36] @ zero_extendqisi2
+ str r3, [sp, #24]
ldrb ip, [ip, #19] @ zero_extendqisi2
- cmp r7, #0
- str ip, [sp, #16]
- ldr ip, .L2339+4
- ldrb ip, [ip, #481] @ zero_extendqisi2
- str ip, [sp, #12]
- beq .L2284
+ cmp r8, #0
+ str ip, [sp, #20]
+ bne .L2246
+ ldr r3, .L2298+4
+ mov r4, r0
+ mov r9, r2
+ ldrb r3, [r3, #477] @ zero_extendqisi2
+ str r3, [sp, #16]
+ add r3, r5, #1216
+ add r3, r3, #4
+ str r3, [sp, #28]
+.L2247:
+ ldr r3, [sp, #12]
+ cmp r8, r3
+ bcc .L2260
+ ldr r7, .L2298+8
+ mov r6, #0
+.L2261:
+ ldrb r3, [r5, #2234] @ zero_extendqisi2
+ cmp r6, r3
+ bcc .L2263
+ ldr r3, [sp, #24]
+ cmp r3, #0
+ bne .L2264
+.L2272:
+ mov r0, #0
+ b .L2245
+.L2246:
bl FlashProgSlc2KPages
- b .L2285
-.L2297:
- mov r3, #36
+.L2245:
+ add sp, sp, #84
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2260:
+ ldr r3, [sp, #12]
+ mov r7, #36
+ mul r7, r7, r8
+ add r2, sp, #36
mov r1, r9
- mul r8, r3, r7
- ldr r3, [sp, #8]
- add r2, sp, #28
- rsb r3, r7, r3
- add fp, r4, r8
+ sub r3, r3, r8
uxtb r3, r3
+ add fp, r4, r7
str r3, [sp]
mov r0, fp
- add r3, sp, #32
+ add r3, sp, #40
bl LogAddr2PhyAddr
- ldrb r3, [r6, #2230] @ zero_extendqisi2
+ ldrb r3, [r5, #2234] @ zero_extendqisi2
mov r10, r0
- ldr r0, [sp, #32]
- cmp r0, r3
- mvncs r3, #0
- strcs r3, [r4, r8]
- bcc .L2336
-.L2287:
- add r7, r7, #1
-.L2284:
- ldr r3, [sp, #8]
- ldr r5, .L2339
- cmp r7, r3
- bcc .L2297
- b .L2337
-.L2336:
- ldrb r3, [r6, #2240] @ zero_extendqisi2
+ ldr r0, [sp, #40]
+ cmp r3, r0
+ mvnls r3, #0
+ strls r3, [r4, r7]
+ bls .L2250
+ ldrb r3, [r5, #2244] @ zero_extendqisi2
cmp r3, #0
- add r3, r6, r0, asl #4
- ldr r3, [r3, #2108]
+ add r3, r5, r0, lsl #4
moveq r10, #0
+ ldr r3, [r3, #2112]
cmp r3, #0
- beq .L2289
+ beq .L2252
uxtb r0, r0
bl FlashWaitCmdDone
-.L2289:
- ldr r3, [sp, #32]
+.L2252:
+ ldr r3, [sp, #40]
mov r1, #0
cmp r10, #0
- add r2, r6, r3, asl #4
- str r1, [r2, #2112]
- ldr r1, [sp, #28]
- str fp, [r2, #2108]
- str r1, [r2, #2104]
- addne r1, r8, #36
+ add r2, r5, r3, lsl #4
+ str r1, [r2, #2116]
+ ldr r1, [sp, #36]
+ str fp, [r2, #2112]
+ str r1, [r2, #2108]
+ addne r1, r7, #36
addne r1, r4, r1
- strne r1, [r2, #2112]
- add r2, r6, r3
- add r3, r6, r3, asl #4
- ldrb r5, [r2, #2232] @ zero_extendqisi2
- strb r5, [r3, #2100]
- mov r0, r5
- ldrb r3, [r6, #2230] @ zero_extendqisi2
+ strne r1, [r2, #2116]
+ add r2, r5, r3
+ ldrb r6, [r2, #2236] @ zero_extendqisi2
+ add r3, r5, r3, lsl #4
+ strb r6, [r3, #2104]
+ mov r0, r6
+ ldrb r3, [r5, #2234] @ zero_extendqisi2
cmp r3, #1
- bne .L2291
+ bne .L2254
bl NandcWaitFlashReady
- b .L2292
-.L2291:
- bl NandcFlashCs
- mov r0, r5
- ldr r3, [sp, #32]
- ldr r1, [sp, #28]
- add r3, r6, r3, asl #2
- ldr r2, [r3, #1172]
- adds r2, r2, #0
- movne r2, #1
- bl FlashWaitReadyEN
- mov r0, r5
- bl NandcFlashDeCs
-.L2292:
- ldr r3, [sp, #16]
+.L2255:
+ ldr r3, [sp, #20]
sub r3, r3, #1
cmp r3, #7
- bhi .L2293
- add r3, r6, r5
- ldrb r3, [r3, #2064] @ zero_extendqisi2
+ bhi .L2256
+ add r3, r5, r6
+ ldrb r3, [r3, #2068] @ zero_extendqisi2
cmp r3, #0
- beq .L2293
- mov r0, r5
- ldrb r1, [r6, #1211] @ zero_extendqisi2
- ldr r2, .L2339+8
+ beq .L2256
mov r3, #0
+ ldr r2, [sp, #28]
+ ldrb r1, [r5, #1217] @ zero_extendqisi2
+ mov r0, r6
bl HynixSetRRPara
-.L2293:
- mov r0, r5
+.L2256:
+ mov r0, r6
bl NandcFlashCs
cmp r9, #1
- mov r0, r5
- bne .L2294
- ldrb r3, [r6, #144] @ zero_extendqisi2
+ mov r0, r6
+ bne .L2257
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L2294
+ beq .L2257
bl flash_enter_slc_mode
- b .L2295
-.L2294:
- bl flash_exit_slc_mode
-.L2295:
- mov r0, r5
- ldr r1, [sp, #28]
+.L2258:
+ ldr r1, [sp, #36]
+ mov r0, r6
bl FlashProgFirstCmd
ldr r3, [fp, #12]
- mov r0, r5
mov r1, #1
+ ldr r2, [sp, #16]
+ mov r0, r6
str r3, [sp]
- ldr r2, [sp, #12]
ldr r3, [fp, #8]
bl NandcXferData
cmp r10, #0
- beq .L2296
- mov r0, r5
- ldr r1, [sp, #28]
+ beq .L2259
+ ldr r1, [sp, #36]
+ mov r0, r6
bl FlashProgDpFirstCmd
- mov r0, r5
- add r8, r8, #36
- add r8, r4, r8
- ldr r3, [sp, #32]
- ldr r1, [sp, #28]
- add r3, r6, r3, asl #2
- ldr r2, [r3, #1172]
+ ldr r3, [sp, #40]
+ mov r0, r6
+ ldr r1, [sp, #36]
+ add r7, r7, #36
+ add r7, r4, r7
+ add r3, r5, r3, lsl #2
+ ldr r2, [r3, #1180]
adds r2, r2, #0
movne r2, #1
bl FlashWaitReadyEN
- ldr r1, [r6, #4]
- mov r0, r5
- ldr r3, [sp, #28]
+ ldr r3, [r5, #40]
+ mov r0, r6
+ ldr r1, [sp, #36]
add r1, r1, r3
bl FlashProgDpSecondCmd
- ldr r3, [r8, #12]
- mov r0, r5
+ ldr r3, [r7, #12]
mov r1, #1
+ ldr r2, [sp, #16]
+ mov r0, r6
str r3, [sp]
- ldr r2, [sp, #12]
- ldr r3, [r8, #8]
+ ldr r3, [r7, #8]
bl NandcXferData
-.L2296:
- mov r0, r5
- ldr r1, [sp, #28]
+.L2259:
+ ldr r1, [sp, #36]
+ mov r0, r6
+ add r8, r8, r10
bl FlashProgSecondCmd
- mov r0, r5
+ mov r0, r6
bl NandcFlashDeCs
- add r7, r7, r10
- b .L2287
-.L2337:
- ldr r8, .L2339+12
- mov r6, #0
- mov r7, r5
-.L2298:
- ldrb r3, [r5, #2230] @ zero_extendqisi2
- cmp r6, r3
- bcs .L2338
+.L2250:
+ add r8, r8, #1
+ b .L2247
+.L2254:
+ bl NandcFlashCs
+ ldr r3, [sp, #40]
+ mov r0, r6
+ ldr r1, [sp, #36]
+ add r3, r5, r3, lsl #2
+ ldr r2, [r3, #1180]
+ adds r2, r2, #0
+ movne r2, #1
+ bl FlashWaitReadyEN
+ mov r0, r6
+ bl NandcFlashDeCs
+ b .L2255
+.L2257:
+ bl flash_exit_slc_mode
+ b .L2258
+.L2263:
uxtb r0, r6
bl FlashWaitCmdDone
cmp r9, #1
- bne .L2299
- ldrb r3, [r7, #144] @ zero_extendqisi2
+ bne .L2262
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L2299
- ldrb r0, [r8, r6, asl #4] @ zero_extendqisi2
+ beq .L2262
+ ldrb r0, [r7, r6, lsl #4] @ zero_extendqisi2
bl flash_exit_slc_mode
-.L2299:
+.L2262:
add r6, r6, #1
- b .L2298
-.L2338:
- ldr r3, [sp, #20]
- cmp r3, #0
- bne .L2301
-.L2309:
- mov r0, #0
- b .L2285
-.L2301:
- ldr r5, .L2339+16
+ b .L2261
+.L2264:
+ ldr r5, .L2298+12
mov r6, #0
- mov r7, r5
-.L2302:
- ldr r3, [sp, #8]
+ ldr r7, .L2298+16
+.L2265:
+ ldr r3, [sp, #12]
cmp r6, r3
- beq .L2309
+ beq .L2272
ldr r3, [r4]
cmn r3, #1
- bne .L2303
+ bne .L2266
ldr r1, [r4, #4]
- ldr r0, .L2339+20
+ ldr r0, .L2298+20
bl printk
- b .L2304
-.L2303:
- ldr r3, [sp, #8]
- mov r1, r9
- add r2, sp, #28
- mov r0, r4
- rsb r3, r6, r3
- uxtb r3, r3
- str r3, [sp]
- add r3, sp, #32
- bl LogAddr2PhyAddr
- ldr r2, [r5, #1724]
- mov r3, #0
- mov lr, r4
- str r3, [r2]
- ldr r2, [r5, #1728]
- str r3, [r2]
- ldmia lr!, {r0, r1, r2, r3}
- add ip, sp, #36
- stmia ip!, {r0, r1, r2, r3}
- ldmia lr!, {r0, r1, r2, r3}
- stmia ip!, {r0, r1, r2, r3}
- add r0, sp, #36
- ldr r3, [lr]
- mov r1, #1
- mov r2, r9
- str r3, [ip]
- ldr r3, [r5, #1724]
- str r3, [sp, #44]
- ldr r3, [r5, #1728]
- str r3, [sp, #48]
- bl FlashReadPages
- ldr r8, [sp, #36]
- cmn r8, #1
- bne .L2305
- ldr r0, .L2339+24
- ldr r1, [r4, #4]
- bl printk
- str r8, [r4]
-.L2305:
- ldr r3, [r4, #12]
- cmp r3, #0
- beq .L2306
- ldr r2, [r3]
- ldr r3, [r7, #1728]
- ldr r3, [r3]
- cmp r2, r3
- beq .L2306
- ldr r0, .L2339+28
- ldr r1, [r4, #4]
- bl printk
- mvn r3, #0
- str r3, [r4]
-.L2306:
- ldr r3, [r4, #8]
- cmp r3, #0
- beq .L2304
- ldr r2, [r3]
- ldr r3, [r7, #1724]
- ldr r3, [r3]
- cmp r2, r3
- beq .L2304
- ldr r0, .L2339+32
- ldr r1, [r4, #4]
- bl printk
- mvn r3, #0
- str r3, [r4]
-.L2304:
+.L2267:
add r6, r6, #1
add r4, r4, #36
- b .L2302
-.L2285:
- add sp, sp, #76
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2340:
+ b .L2265
+.L2266:
+ ldr r3, [sp, #12]
+ add r2, sp, #36
+ mov r1, r9
+ mov r0, r4
+ sub r3, r3, r6
+ uxtb r3, r3
+ str r3, [sp]
+ add r3, sp, #40
+ bl LogAddr2PhyAddr
+ ldr r2, [r5, #1732]
+ mov r3, #0
+ mov lr, r4
+ add ip, sp, #44
+ str r3, [r2]
+ ldr r2, [r5, #1736]
+ str r3, [r2]
+ ldmia lr!, {r0, r1, r2, r3}
+ stmia ip!, {r0, r1, r2, r3}
+ ldmia lr!, {r0, r1, r2, r3}
+ stmia ip!, {r0, r1, r2, r3}
+ mov r2, r9
+ ldr r3, [lr]
+ mov r1, #1
+ add r0, sp, #44
+ str r3, [ip]
+ ldr r3, [r5, #1732]
+ str r3, [sp, #52]
+ ldr r3, [r5, #1736]
+ str r3, [sp, #56]
+ bl FlashReadPages
+ ldr r8, [sp, #44]
+ cmn r8, #1
+ bne .L2268
+ ldr r1, [r4, #4]
+ ldr r0, .L2298+24
+ bl printk
+ str r8, [r4]
+.L2268:
+ ldr r3, [r4, #12]
+ cmp r3, #0
+ beq .L2269
+ ldr r2, [r3]
+ ldr r3, [r5, #1736]
+ ldr r3, [r3]
+ cmp r2, r3
+ beq .L2269
+ ldr r1, [r4, #4]
+ ldr r0, .L2298+28
+ bl printk
+ mvn r3, #0
+ str r3, [r4]
+.L2269:
+ ldr r3, [r4, #8]
+ cmp r3, #0
+ beq .L2267
+ ldr r2, [r3]
+ ldr r3, [r5, #1732]
+ ldr r3, [r3]
+ cmp r2, r3
+ beq .L2267
+ ldr r1, [r4, #4]
+ mov r0, r7
+ bl printk
+ mvn r3, #0
+ str r3, [r4]
+ b .L2267
+.L2299:
.align 2
-.L2339:
+.L2298:
.word .LANCHOR0
.word .LANCHOR1
- .word .LANCHOR0+1214
- .word .LANCHOR0+2100
+ .word .LANCHOR0+2104
.word .LANCHOR2
+ .word .LC108
.word .LC104
.word .LC105
.word .LC107
- .word .LC108
.fnend
.size FlashProgPages, .-FlashProgPages
.align 2
.global FlashTestBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashTestBlk, %function
FlashTestBlk:
.fnstart
@ args = 0, pretend = 0, frame = 104
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, lr}
+ push {r4, r5, lr}
.save {r4, r5, lr}
.pad #108
sub sp, sp, #108
- ldr r5, .L2345
- ldr r3, [r5, #1708]
+ ldr r5, .L2304
+ ldr r3, [r5, #1716]
cmp r0, r3
movcc r4, #0
- bcc .L2342
- ldr r3, [r5, #1716]
+ bcc .L2300
+ ldr r3, [r5, #1724]
mov r4, r0
- mov r1, #165
- add r0, sp, #40
mov r2, #32
+ add r0, sp, #40
+ mov r1, #165
str r0, [sp, #16]
str r3, [sp, #12]
bl ftl_memset
- mov r1, #90
mov r2, #8
- ldr r0, [r5, #1716]
- mov r4, r4, asl #10
+ mov r1, #90
+ ldr r0, [r5, #1724]
bl ftl_memset
- mov r1, #1
- mov r2, r1
- add r0, sp, #4
- str r4, [sp, #8]
- bl FlashEraseBlocks
- mov r1, #1
- mov r2, r1
- mov r3, r1
- add r0, sp, #4
- bl FlashProgPages
- mov r1, #0
+ lsl r0, r4, #10
mov r2, #1
+ mov r1, r2
+ str r0, [sp, #8]
+ add r0, sp, #4
+ bl FlashEraseBlocks
+ mov r3, #1
+ add r0, sp, #4
+ mov r2, r3
+ mov r1, r3
+ bl FlashProgPages
ldr r4, [sp, #4]
+ mov r2, #1
+ mov r1, #0
add r0, sp, #4
adds r4, r4, #0
movne r4, #1
rsb r4, r4, #0
bl FlashEraseBlocks
-.L2342:
+.L2300:
mov r0, r4
add sp, sp, #108
@ sp needed
- ldmfd sp!, {r4, r5, pc}
-.L2346:
+ pop {r4, r5, pc}
+.L2305:
.align 2
-.L2345:
+.L2304:
.word .LANCHOR2
.fnend
.size FlashTestBlk, .-FlashTestBlk
.align 2
.global FlashMakeFactorBbt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashMakeFactorBbt, %function
FlashMakeFactorBbt:
.fnstart
@ args = 0, pretend = 0, frame = 80
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r2, .L2357
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #84
sub sp, sp, #84
- ldr r5, .L2403
- mov r1, #1
- ldr r4, .L2403+4
- ldr r0, .L2403+8
- ldr r3, [r5, #1720]
- ldrh r8, [r4, #128]
- str r3, [sp, #20]
- ldrh r3, [r4, #130]
- smulbb r8, r8, r3
- ldr r3, [r4, #44]
- ldrb r3, [r3, #24] @ zero_extendqisi2
- uxth r8, r8
+ ldr r5, .L2357
+ mov r4, r2
+ ldr r3, [r2, #1728]
str r3, [sp, #24]
- ldrh r3, [r4, #4]
- str r3, [sp, #16]
- ldrb r3, [r4] @ zero_extendqisi2
- ldr r4, .L2403+4
+ ldr r3, .L2357+4
+ ldrh r0, [r3, #136]
+ ldrh r1, [r3, #138]
+ smulbb r1, r1, r0
+ ldr r0, .L2357+8
+ uxth r1, r1
+ str r1, [sp, #4]
+ ldr r1, [r3, #48]
+ ldrb r1, [r1, #24] @ zero_extendqisi2
+ str r1, [sp, #28]
+ ldrh r1, [r3, #40]
+ ldrb r3, [r3, #36] @ zero_extendqisi2
+ str r1, [sp, #20]
cmp r3, #1
- ldreq r3, [sp, #16]
- moveq r3, r3, asl #1
+ moveq r3, r1
+ mov r1, #1
+ lsleq r3, r3, #1
uxtheq r3, r3
- streq r3, [sp, #16]
+ streq r3, [sp, #20]
bl printk
- ldr r0, [r5, #1720]
- mov r1, #0
+ ldr r0, [r4, #1728]
mov r2, #4096
+ mov r1, #0
+ ldr r4, .L2357+4
bl ftl_memset
- ldr r5, .L2403
- mov r3, r8, lsr #4
- str r3, [sp, #28]
+ ldr r3, [sp, #4]
+ lsr r3, r3, #4
+ str r3, [sp, #32]
mov r3, #0
- str r3, [sp, #8]
-.L2349:
- ldrb r7, [sp, #8] @ zero_extendqisi2
- ldrb r3, [r4, #2230] @ zero_extendqisi2
+ str r3, [sp, #12]
+.L2308:
+ ldrb r7, [sp, #12] @ zero_extendqisi2
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
cmp r3, r7
- bls .L2399
- ldr r2, .L2403+12
- mov r3, r7, asl #1
+ bhi .L2335
+ add sp, sp, #84
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2335:
+ ldr r2, .L2357+12
+ lsl r3, r7, #1
ldrh r6, [r2, r3]
cmp r6, #0
- bne .L2379
- ldrh r2, [r4, #136]
+ bne .L2309
+ ldrh r2, [r4, #144]
mov r1, r6
- ldr r0, [r5, #1688]
+ ldr r0, [r5, #1696]
+ add fp, r4, r7, lsl #2
+ mov r8, r6
mov r9, r6
- mov r2, r2, asl #9
+ lsl r2, r2, #9
bl ftl_memset
add r3, r4, r7
- ldrb r10, [r3, #2232] @ zero_extendqisi2
- mov r3, r7, asl #2
- add fp, r4, r3
- str r6, [sp, #4]
- str r3, [sp, #32]
-.L2351:
- ldrh r3, [sp, #4]
- cmp r3, r8
- str r3, [sp, #12]
- bcs .L2361
+ str r6, [sp, #8]
+ ldrb r10, [r3, #2236] @ zero_extendqisi2
+.L2310:
+ ldrh r3, [sp, #8]
+ ldr r2, [sp, #4]
+ str r3, [sp, #16]
+ cmp r3, r2
+ bcc .L2321
+.L2320:
+ mov r2, r8
+ mov r1, r7
+ ldr r0, .L2357+16
+ bl printk
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ ldr r2, [sp, #32]
+ mul r3, r2, r3
+ cmp r8, r3
+ blt .L2322
+ ldrh r2, [r4, #144]
+ mov r1, #0
+ ldr r0, [r5, #1696]
+ lsl r2, r2, #9
+ bl ftl_memset
+.L2322:
+ cmp r7, #0
+ bne .L2324
+ add r3, r5, #1712
+ ldr r8, .L2357+20
+ add r3, r3, #4
+ ldrh r10, [r3]
+ mov r9, #1
+.L2325:
+ ldrb r3, [r4, #37] @ zero_extendqisi2
+ cmp r3, r10
+ bhi .L2327
+ ldr r3, [sp, #4]
+ mov r10, #1
+ ldr r9, .L2357+20
+ sub fp, r3, #1
+ sub r8, r3, #50
+ uxth fp, fp
+.L2328:
+ cmp fp, r8
+ bgt .L2330
+ ldrb r3, [r4, #37] @ zero_extendqisi2
+ ldr r2, [r5, #1716]
+ sub r3, r3, r2
+ cmp r6, r3
+ bcc .L2324
+ ldrh r2, [r4, #144]
+ mov r1, #0
+ ldr r0, [r5, #1696]
+ lsl r2, r2, #9
+ bl ftl_memset
+.L2324:
+ ldr r3, [sp, #4]
+ ldrb r8, [sp, #12] @ zero_extendqisi2
+ ldr r9, .L2357+12
+ sub r6, r3, #1
+ ldr fp, .L2357+24
+ ldr r10, .L2357+28
+ uxth r6, r6
+ mul r8, r3, r8
+ add r9, r9, r7, lsl #1
+.L2332:
+ mov r1, r7
+ mov r2, r6
+ mov r0, fp
+ bl printk
+ ldr r1, [r5, #1696]
+.L2333:
+ lsr r2, r6, #5
+ and r3, r6, #31
+ ldr r2, [r1, r2, lsl #2]
+ lsr r3, r2, r3
+ ands r3, r3, #1
+ bne .L2334
+ ldr r2, [sp, #24]
+ add r0, sp, #44
+ strh r6, [r9] @ movhi
+ strh r10, [r2] @ movhi
+ strh r6, [r2, #2] @ movhi
+ strh r3, [r2, #8] @ movhi
+ mov r2, #1
+ ldr r3, [r5, #1696]
+ mov r1, r2
+ str r3, [sp, #52]
+ ldr r3, [r5, #1728]
+ str r3, [sp, #56]
+ add r3, r6, r8
+ lsl r3, r3, #10
+ str r3, [sp, #48]
+ bl FlashEraseBlocks
+ mov r3, #1
+ add r0, sp, #44
+ mov r2, r3
+ mov r1, r3
+ bl FlashProgPages
+ ldr r3, [sp, #44]
+ cmp r3, #0
+ beq .L2309
+ sub r6, r6, #1
+ uxth r6, r6
+ b .L2332
+.L2321:
mvn r3, #0
strb r3, [sp, #42]
strb r3, [sp, #43]
- ldr r3, [sp, #24]
+ ldr r3, [sp, #28]
tst r3, #1
- beq .L2353
- ldr r3, [fp, #1172]
+ beq .L2312
+ ldr r3, [fp, #1180]
add r2, sp, #42
mov r0, r10
- add r3, r6, r3
- str r3, [sp, #36]
+ add r3, r9, r3
mov r1, r3
+ str r3, [sp, #36]
bl FlashReadSpare
- ldrb r2, [r4] @ zero_extendqisi2
- cmp r2, #1
+ ldrb r2, [r4, #36] @ zero_extendqisi2
ldr r3, [sp, #36]
- bne .L2353
- ldr r1, [r4, #4]
+ cmp r2, #1
+ bne .L2312
+ ldr r1, [r4, #40]
add r2, sp, #43
mov r0, r10
add r1, r3, r1
@@ -13888,1198 +14450,1097 @@
ldrb r2, [sp, #43] @ zero_extendqisi2
and r3, r3, r2
strb r3, [sp, #42]
-.L2353:
- ldr r3, [sp, #24]
+.L2312:
+ ldr r3, [sp, #28]
tst r3, #2
- beq .L2355
- ldr r3, [r4, #44]
- mov r0, r10
+ beq .L2314
+ ldr r3, [r4, #48]
add r2, sp, #43
+ mov r0, r10
ldrh r1, [r3, #10]
- ldr r3, [fp, #1172]
+ ldr r3, [fp, #1180]
sub r1, r1, #1
add r1, r1, r3
- add r1, r1, r6
+ add r1, r1, r9
bl FlashReadSpare
-.L2355:
- ldr r2, [r4, #44]
+.L2314:
+ ldr r2, [r4, #48]
ldrb r3, [r2, #7] @ zero_extendqisi2
- cmp r3, #1
- cmpne r3, #8
+ cmp r3, #8
+ cmpne r3, #1
ldrb r3, [sp, #42] @ zero_extendqisi2
- beq .L2356
+ beq .L2315
ldrb r2, [r2, #18] @ zero_extendqisi2
cmp r2, #12
- bne .L2357
-.L2356:
+ bne .L2316
+.L2315:
cmp r3, #0
- ldrneb r0, [sp, #43] @ zero_extendqisi2
+ ldrbne r0, [sp, #43] @ zero_extendqisi2
clzne r0, r0
- movne r0, r0, lsr #5
- bne .L2358
- b .L2378
-.L2357:
+ lsrne r0, r0, #5
+ bne .L2317
+.L2337:
+ mov r0, #1
+ b .L2317
+.L2316:
cmp r3, #255
- bne .L2378
+ bne .L2337
ldrb r0, [sp, #43] @ zero_extendqisi2
subs r0, r0, #255
movne r0, #1
- b .L2358
-.L2378:
- mov r0, #1
-.L2358:
- ldr r3, [sp, #24]
+.L2317:
+ ldr r3, [sp, #28]
tst r3, #4
- beq .L2359
- ldr r3, .L2403+4
+ beq .L2318
+ ldr r1, [fp, #1180]
mov r0, r10
- ldr r2, [sp, #32]
- add r3, r3, r2
- ldr r1, [r3, #1172]
- add r1, r6, r1
+ add r1, r9, r1
bl SandiskProgTestBadBlock
-.L2359:
+.L2318:
cmp r0, #0
- beq .L2360
+ beq .L2319
+ ldr r2, [sp, #8]
mov r1, r7
- ldr r2, [sp, #4]
- ldr r0, .L2403+16
- add r9, r9, #1
+ ldr r0, .L2357+32
+ add r8, r8, #1
bl printk
- ldr r1, [r5, #1688]
- mov ip, #1
- uxth r9, r9
- ldr r3, [sp, #12]
- mov r0, r3, lsr #5
- and r3, r3, #31
- ldr r2, [r1, r0, asl #2]
- orr r3, r2, ip, asl r3
- ldr r2, [sp, #28]
- str r3, [r1, r0, asl #2]
- ldrb r3, [r4, #2230] @ zero_extendqisi2
- mul r3, r3, r2
- cmp r9, r3
- bgt .L2361
-.L2360:
- ldr r3, [sp, #4]
- add r3, r3, #1
- str r3, [sp, #4]
ldr r3, [sp, #16]
- add r6, r6, r3
- b .L2351
-.L2361:
- mov r2, r9
- ldr r0, .L2403+20
- mov r1, r7
- bl printk
- ldrb r3, [r4, #2230] @ zero_extendqisi2
- ldr r2, [sp, #28]
- mul r3, r3, r2
- cmp r9, r3
- blt .L2363
- ldrh r2, [r4, #136]
- mov r1, #0
- ldr r0, [r5, #1688]
- mov r2, r2, asl #9
- bl ftl_memset
-.L2363:
- cmp r7, #0
- bne .L2365
- ldr r3, [r5, #1708]
- mov r6, r7
- mov r9, #1
- uxth r10, r3
-.L2366:
- ldr r3, .L2403+4
- ldrb r3, [r3, #1] @ zero_extendqisi2
- cmp r3, r10
- bls .L2400
- mov r0, r10
- bl FlashTestBlk
- cmp r0, #0
- beq .L2367
- mov r1, r10
- ldr r0, .L2403+24
- bl printk
- ldr r1, [r5, #1688]
- mov r0, r10, lsr #5
- add r6, r6, #1
- and r3, r10, #31
- ldr r2, [r1, r0, asl #2]
- uxth r6, r6
- orr r3, r2, r9, asl r3
- str r3, [r1, r0, asl #2]
-.L2367:
- add r10, r10, #1
- uxth r10, r10
- b .L2366
-.L2400:
- sub fp, r8, #1
- sub r9, r8, #50
- mov r10, #1
- uxth fp, fp
-.L2369:
- cmp fp, r9
- ble .L2401
- mov r0, fp
- bl FlashTestBlk
- cmp r0, #0
- beq .L2370
- mov r1, fp
- ldr r0, .L2403+24
- bl printk
- ldr r1, [r5, #1688]
- mov r0, fp, lsr #5
- and r3, fp, #31
- ldr r2, [r1, r0, asl #2]
- orr r3, r2, r10, asl r3
- str r3, [r1, r0, asl #2]
-.L2370:
- sub fp, fp, #1
- uxth fp, fp
- b .L2369
-.L2401:
- ldr r3, .L2403+4
- ldr r2, [r5, #1708]
- ldrb r3, [r3, #1] @ zero_extendqisi2
- rsb r3, r2, r3
- cmp r6, r3
- bcc .L2365
- ldrh r2, [r4, #136]
- mov r1, #0
- ldr r0, [r5, #1688]
- mov r2, r2, asl #9
- bl ftl_memset
-.L2365:
- ldrb r6, [sp, #8] @ zero_extendqisi2
- sub r10, r8, #1
- ldr r9, .L2403+12
- uxth r10, r10
- mul r6, r8, r6
- add r9, r9, r7, asl #1
-.L2373:
- mov r1, r7
- ldr r0, .L2403+28
- mov r2, r10
- bl printk
- ldr r1, [r5, #1688]
-.L2374:
- mov r2, r10, lsr #5
- and r3, r10, #31
- ldr r2, [r1, r2, asl #2]
- mov r3, r2, lsr r3
- ands r3, r3, #1
- subne r10, r10, #1
- uxthne r10, r10
- bne .L2374
-.L2402:
- ldr r1, [sp, #20]
- add r0, sp, #44
- ldr r2, .L2403+32
- strh r10, [r9] @ movhi
- strh r10, [r1, #2] @ movhi
- strh r2, [r1] @ movhi
- strh r3, [r1, #8] @ movhi
- mov r1, #1
- ldr r3, [r5, #1688]
- mov r2, r1
- str r3, [sp, #52]
- ldr r3, [r5, #1720]
- str r3, [sp, #56]
- add r3, r10, r6
- mov r3, r3, asl #10
- str r3, [sp, #48]
- bl FlashEraseBlocks
- mov r1, #1
- mov r3, r1
- mov r2, r1
- add r0, sp, #44
- bl FlashProgPages
- ldr r3, [sp, #44]
- cmp r3, #0
- subne r10, r10, #1
- uxthne r10, r10
- bne .L2373
-.L2379:
+ mov ip, #1
+ ldr r2, [r5, #1696]
+ uxth r8, r8
+ and r0, r3, #31
+ lsr r1, r3, #5
+ ldr r3, [r2, r1, lsl #2]
+ orr r3, r3, ip, lsl r0
+ str r3, [r2, r1, lsl #2]
+ ldr r2, [sp, #32]
+ ldrb r3, [r4, #2234] @ zero_extendqisi2
+ mul r3, r2, r3
+ cmp r8, r3
+ bgt .L2320
+.L2319:
ldr r3, [sp, #8]
add r3, r3, #1
str r3, [sp, #8]
- b .L2349
-.L2399:
- add sp, sp, #84
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2404:
+ ldr r3, [sp, #20]
+ add r9, r9, r3
+ b .L2310
+.L2327:
+ mov r0, r10
+ bl FlashTestBlk
+ cmp r0, #0
+ beq .L2326
+ mov r1, r10
+ mov r0, r8
+ bl printk
+ ldr r1, [r5, #1696]
+ lsr r0, r10, #5
+ add r6, r6, #1
+ and r3, r10, #31
+ uxth r6, r6
+ ldr r2, [r1, r0, lsl #2]
+ orr r3, r2, r9, lsl r3
+ str r3, [r1, r0, lsl #2]
+.L2326:
+ add r10, r10, #1
+ uxth r10, r10
+ b .L2325
+.L2330:
+ mov r0, fp
+ bl FlashTestBlk
+ cmp r0, #0
+ beq .L2329
+ mov r1, fp
+ mov r0, r9
+ bl printk
+ ldr r1, [r5, #1696]
+ lsr r0, fp, #5
+ and r3, fp, #31
+ ldr r2, [r1, r0, lsl #2]
+ orr r3, r2, r10, lsl r3
+ str r3, [r1, r0, lsl #2]
+.L2329:
+ sub fp, fp, #1
+ uxth fp, fp
+ b .L2328
+.L2334:
+ sub r6, r6, #1
+ uxth r6, r6
+ b .L2333
+.L2309:
+ ldr r3, [sp, #12]
+ add r3, r3, #1
+ str r3, [sp, #12]
+ b .L2308
+.L2358:
.align 2
-.L2403:
+.L2357:
.word .LANCHOR2
.word .LANCHOR0
.word .LC121
- .word .LANCHOR2+1736
- .word .LC122
+ .word .LANCHOR2+1742
.word .LC123
.word .LC124
.word .LC125
.word -3872
+ .word .LC122
.fnend
.size FlashMakeFactorBbt, .-FlashMakeFactorBbt
.align 2
.global FtlLowFormatEraseBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLowFormatEraseBlock, %function
FtlLowFormatEraseBlock:
.fnstart
@ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L2404
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #28
sub sp, sp, #28
- ldr r9, .L2455
- ldr fp, .L2455+4
- ldr r5, [r9, #-3616]
- ldrb r3, [fp, #2240] @ zero_extendqisi2
- cmp r5, #0
- str r3, [sp, #16]
- movne r0, #0
- bne .L2406
- ldrb r3, [fp, #144] @ zero_extendqisi2
- mov r6, fp
- add fp, fp, #2400
- mov r10, r9
- mov r4, r5
- mov r9, r5
+ ldr r2, [r3, #-3612]
+ cmp r2, #0
+ movne r4, #0
+ bne .L2359
+ ldr r5, .L2404+4
+ mov r10, r3
+ ldr fp, .L2404+8
+ mov r9, r2
+ mov r6, r2
+ mov r4, r2
+ ldrb r3, [r5, #2244] @ zero_extendqisi2
mov r8, #36
- str r1, [sp]
- str r0, [sp, #4]
- str r3, [sp, #8]
+ str r1, [sp, #4]
+ str r0, [sp, #8]
+ str r3, [sp, #20]
+ ldrb r3, [r5, #152] @ zero_extendqisi2
str r0, [r10, #-548]
-.L2407:
- ldr ip, .L2455+4
- add r1, ip, #2320
- ldrh r0, [r1]
+ str r3, [sp, #12]
+.L2361:
+ ldrh r0, [fp]
uxth r1, r9
cmp r0, r1
- bls .L2450
- mul r0, r8, r1
- ldr ip, [r10, #-3612]
+ bhi .L2365
+ cmp r6, #0
+ beq .L2359
+ ldr r3, [sp, #12]
+ mov r8, #0
+ mov r2, r6
+ ldr r0, [r10, #-3608]
+ strb r8, [r5, #2244]
+ mov r9, #36
+ adds r7, r3, #0
+ movne r7, #1
+ mov r1, r7
+ bl FlashEraseBlocks
+ ldrb r3, [sp, #20] @ zero_extendqisi2
+ strb r3, [r5, #2244]
+.L2367:
+ uxth r2, r8
+ cmp r6, r2
+ bhi .L2369
+ ldr r3, [sp, #4]
+ cmp r3, #0
+ bne .L2370
+ uxth r7, r7
+ mov r3, #6
+ str r3, [sp, #16]
+ mov r3, #1
+ str r3, [sp, #12]
+.L2371:
+ ldr r6, .L2404
+ mov r9, #0
+.L2380:
+ ldr fp, .L2404+4
+ mov r10, #0
+ mov r5, r10
+.L2372:
+ ldr r3, .L2404+8
+ ldrh r1, [r3]
+ uxth r3, r10
+ cmp r1, r3
+ bhi .L2375
+ cmp r5, #0
+ beq .L2359
+ mov r3, #1
+ mov r8, #0
+ mov r2, r7
+ mov r1, r5
+ ldr r0, [r6, #-3608]
+ strb r8, [fp, #2244]
+ bl FlashProgPages
+ ldrb r3, [sp, #20] @ zero_extendqisi2
+ strb r3, [fp, #2244]
+ mov fp, #36
+.L2377:
+ uxth r3, r8
+ cmp r5, r3
+ bhi .L2379
+ ldr r3, [sp, #16]
+ add r9, r9, r3
+ ldr r3, [sp, #12]
+ uxth r9, r9
+ cmp r3, r9
+ bhi .L2380
+ mov r8, #0
+ mov r9, #36
+.L2381:
+ uxth r3, r8
+ cmp r5, r3
+ ldr r3, [sp, #4]
+ bhi .L2383
+ adds r0, r3, #0
+ ldr r3, [sp, #8]
+ movne r0, #1
+ cmp r3, #63
+ orrls r0, r0, #1
+ cmp r0, #0
+ beq .L2359
+ mov r2, r5
+ mov r1, r7
+ ldr r0, [r6, #-3608]
+ bl FlashEraseBlocks
+.L2359:
+ mov r0, r4
+ add sp, sp, #28
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2365:
+ uxth r1, r9
+ ldr ip, [r10, #-3608]
mov r3, #0
+ mul r0, r8, r1
str r3, [ip, r0]
- ldr r3, .L2455+4
- add r1, r3, r1
- ldrb r0, [r1, #2348] @ zero_extendqisi2
- ldr r1, [sp, #4]
+ add r0, r5, r1
+ ldrb r0, [r0, #2350] @ zero_extendqisi2
+ ldr r1, [sp, #8]
bl V2P_block
- ldr r3, [sp]
+ ldr r3, [sp, #4]
mov r7, r0
cmp r3, #0
- beq .L2408
+ beq .L2362
bl IsBlkInVendorPart
cmp r0, #0
- bne .L2409
-.L2408:
+ bne .L2363
+.L2362:
mov r0, r7
bl FtlBbmIsBadBlock
cmp r0, #0
addne r4, r4, #1
uxthne r4, r4
- bne .L2409
- ldr ip, [r10, #-3612]
- mov r7, r7, asl #10
- ldrh r1, [fp]
- mla ip, r8, r5, ip
- mul r1, r1, r5
- add r5, r5, #1
- uxth r5, r5
- cmp r1, #0
+ bne .L2363
+ ldr r3, .L2404+12
+ lsl r7, r7, #10
+ ldr ip, [r10, #-3608]
+ ldrh r1, [r3]
+ mla ip, r8, r6, ip
+ mul r1, r6, r1
+ add r6, r6, #1
+ uxth r6, r6
str r0, [ip, #8]
- add r0, r1, #3
str r7, [ip, #4]
+ add r0, r1, #3
+ cmp r1, #0
movlt r1, r0
ldr r0, [r10, #-496]
bic r1, r1, #3
add r1, r0, r1
str r1, [ip, #12]
-.L2409:
+.L2363:
add r9, r9, #1
- b .L2407
-.L2450:
- cmp r5, #0
- beq .L2430
- ldr r3, [sp, #8]
- mov r2, r5
- ldr r0, [r10, #-3612]
- mov r8, #0
- adds r7, r3, #0
- strb r8, [ip, #2240]
- str ip, [sp, #8]
- mov r9, #36
- movne r7, #1
- mov r1, r7
- bl FlashEraseBlocks
- ldrb r3, [sp, #16] @ zero_extendqisi2
- ldr ip, [sp, #8]
- strb r3, [ip, #2240]
-.L2413:
- uxth r2, r8
- cmp r2, r5
- bcs .L2451
+ b .L2361
+.L2369:
mul r2, r9, r8
- ldr r1, [r10, #-3612]
- add r0, r1, r2
+ ldr r1, [r10, #-3608]
+ add ip, r1, r2
ldr r2, [r1, r2]
cmn r2, #1
- bne .L2414
- ldr r0, [r0, #4]
+ bne .L2368
+ ldr r0, [ip, #4]
add r4, r4, #1
- ubfx r0, r0, #10, #16
uxth r4, r4
+ ubfx r0, r0, #10, #16
bl FtlBbmMapBadBlock
-.L2414:
+.L2368:
add r8, r8, #1
- b .L2413
-.L2451:
- ldr r3, [sp]
- cmp r3, #0
- bne .L2416
- mov r3, #6
- uxth r7, r7
+ b .L2367
+.L2370:
+ movw r3, #2392
+ ldrh r3, [r5, r3]
str r3, [sp, #12]
- mov r3, #1
- str r3, [sp, #8]
- b .L2417
-.L2416:
- movw r3, #2390
- ldrh r3, [r6, r3]
- str r3, [sp, #8]
- ldrb r3, [r6, #144] @ zero_extendqisi2
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- ldreq r3, [sp, #8]
- moveq r7, #1
+ ldreq r3, [sp, #12]
movne r7, #1
- strne r7, [sp, #12]
- moveq r3, r3, lsr #2
- streq r3, [sp, #12]
-.L2417:
- ldr r10, .L2455
- mov r5, #0
- mov r8, r10
-.L2426:
- mov fp, #0
- mov r6, fp
-.L2418:
- ldr r9, .L2455+4
- add r3, r9, #2320
- ldrh r1, [r3]
- uxth r3, fp
- cmp r1, r3
- bls .L2452
+ moveq r7, #1
+ strne r7, [sp, #16]
+ lsreq r3, r3, #2
+ streq r3, [sp, #16]
+ b .L2371
+.L2375:
+ uxth r3, r10
mov r2, #36
- ldr r0, [r10, #-3612]
+ ldr r0, [r6, #-3608]
mul r1, r2, r3
+ add r3, fp, r3
mov r2, #0
str r2, [r0, r1]
- ldr r2, .L2455+4
- ldr r1, [sp, #4]
- add r3, r2, r3
- ldrb r0, [r3, #2348] @ zero_extendqisi2
+ ldr r1, [sp, #8]
+ ldrb r0, [r3, #2350] @ zero_extendqisi2
bl V2P_block
- ldr r3, [sp]
- mov r9, r0
+ ldr r3, [sp, #4]
+ mov r8, r0
cmp r3, #0
- beq .L2419
+ beq .L2373
bl IsBlkInVendorPart
cmp r0, #0
- bne .L2420
-.L2419:
- mov r0, r9
+ bne .L2374
+.L2373:
+ mov r0, r8
bl FtlBbmIsBadBlock
cmp r0, #0
- bne .L2420
- ldr r1, [r8, #-3612]
+ bne .L2374
+ ldr r1, [r6, #-3608]
mov r3, #36
- add r9, r5, r9, asl #10
- mla r1, r3, r6, r1
- ldr r3, [r8, #-508]
+ add r8, r9, r8, lsl #10
+ mla r1, r3, r5, r1
+ ldr r3, [r6, #-508]
str r3, [r1, #8]
- ldr r3, .L2455+8
- str r9, [r1, #4]
+ ldr r3, .L2404+12
+ str r8, [r1, #4]
ldrh r3, [r3]
- mul r3, r3, r6
- add r6, r6, #1
- uxth r6, r6
+ mul r3, r5, r3
+ add r5, r5, #1
+ uxth r5, r5
add r0, r3, #3
cmp r3, #0
movlt r3, r0
- ldr r0, [r8, #-504]
+ ldr r0, [r6, #-504]
bic r3, r3, #3
add r3, r0, r3
str r3, [r1, #12]
-.L2420:
- add fp, fp, #1
- b .L2418
-.L2452:
- cmp r6, #0
- beq .L2430
- mov r2, r7
- mov r3, #1
- ldr r0, [r10, #-3612]
- mov r1, r6
- mov fp, #0
- strb fp, [r9, #2240]
- bl FlashProgPages
- mov r2, #36
- ldrb r3, [sp, #16] @ zero_extendqisi2
- strb r3, [r9, #2240]
- ldr r9, .L2455
-.L2423:
- uxth r3, fp
- cmp r3, r6
- bcs .L2453
- mul r3, r2, fp
- ldr r1, [r8, #-3612]
- add r0, r1, r3
- ldr r3, [r1, r3]
- cmp r3, #0
- beq .L2424
- ldr r0, [r0, #4]
- add r4, r4, #1
- str r2, [sp, #20]
- ubfx r0, r0, #10, #16
- uxth r4, r4
- bl FtlBbmMapBadBlock
- ldr r2, [sp, #20]
-.L2424:
- add fp, fp, #1
- b .L2423
-.L2453:
- ldr r3, [sp, #12]
- add r5, r5, r3
- ldr r3, [sp, #8]
- uxth r5, r5
- cmp r5, r3
- bcc .L2426
- mov r5, #0
- mov r8, #36
-.L2427:
- uxth r3, r5
- cmp r3, r6
- ldr r3, [sp]
- bcs .L2454
- cmp r3, #0
- beq .L2428
- mul r3, r8, r5
- ldr r2, [r9, #-3612]
+.L2374:
+ add r10, r10, #1
+ b .L2372
+.L2379:
+ mul r3, fp, r8
+ ldr r2, [r6, #-3608]
add r1, r2, r3
ldr r3, [r2, r3]
cmp r3, #0
- bne .L2428
+ beq .L2378
+ ldr r0, [r1, #4]
+ add r4, r4, #1
+ uxth r4, r4
+ ubfx r0, r0, #10, #16
+ bl FtlBbmMapBadBlock
+.L2378:
+ add r8, r8, #1
+ b .L2377
+.L2383:
+ cmp r3, #0
+ beq .L2382
+ mul r3, r9, r8
+ ldr r2, [r6, #-3608]
+ add r1, r2, r3
+ ldr r3, [r2, r3]
+ cmp r3, #0
+ bne .L2382
ldr r0, [r1, #4]
mov r1, #1
ubfx r0, r0, #10, #16
bl FtlFreeSysBlkQueueIn
-.L2428:
- add r5, r5, #1
- b .L2427
-.L2454:
- adds r1, r3, #0
- ldr r3, [sp, #4]
- movne r1, #1
- cmp r3, #63
- orrls r1, r1, #1
- cmp r1, #0
- beq .L2430
- ldr r0, [r9, #-3612]
- mov r1, r7
- mov r2, r6
- bl FlashEraseBlocks
-.L2430:
- mov r0, r4
-.L2406:
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2456:
+.L2382:
+ add r8, r8, #1
+ b .L2381
+.L2405:
.align 2
-.L2455:
+.L2404:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR0+2400
+ .word .LANCHOR0+2324
+ .word .LANCHOR0+2402
.fnend
.size FtlLowFormatEraseBlock, .-FtlLowFormatEraseBlock
.align 2
.global FtlBbmTblFlush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlBbmTblFlush, %function
FtlBbmTblFlush:
.fnstart
- @ args = 0, pretend = 0, frame = 8
+ @ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #20
- sub sp, sp, #20
- ldr r4, .L2475
- ldr r5, [r4, #-3616]
+ .pad #12
+ ldr r4, .L2421
+ ldr r5, [r4, #-3612]
cmp r5, #0
- bne .L2459
- ldr r3, [r4, #-500]
+ bne .L2408
+ ldr r7, .L2421+4
+ sub r10, r4, #436
+ ldr r8, .L2421+8
mov r1, r5
- ldr r2, .L2475+4
- sub r9, r4, #436
ldr r0, [r4, #-524]
- str r3, [r4, #1764]
- movw r3, #2398
- ldrh r2, [r2, r3]
- str r0, [r4, #1760]
- bl ftl_memset
- ldr r6, .L2475+8
- sub r8, r6, #134
-.L2460:
- ldrh r3, [r8]
- ldr r7, .L2475+4
- cmp r5, r3
- bge .L2474
- ldrh r2, [r9]
- ldr r3, [r4, #1760]
- ldr r1, [r6, #4]!
- mul r0, r2, r5
- mov r2, r2, asl #2
- add r5, r5, #1
- add r0, r3, r0, asl #2
- bl ftl_memcpy
- b .L2460
-.L2474:
- ldr r9, [r4, #1764]
- mov r1, #255
- mov r2, #16
- ldr r5, .L2475+12
- ldr r10, .L2475
- mov r6, #0
- mov r0, r9
- bl ftl_memset
- ldr r3, .L2475+16
- mov r8, r5
- strh r3, [r9] @ movhi
- ldr r3, [r7, #2460]
- str r3, [r9, #4]
- movw r3, #2452
- ldrh r3, [r7, r3]
- strh r3, [r9, #2] @ movhi
- ldrh r3, [r5, #4]
- strh r3, [r9, #8] @ movhi
- ldrh r3, [r5, #6]
- strh r3, [r9, #10] @ movhi
- ldr r3, [r7, #2316]
- strh r3, [r9, #12] @ movhi
- str r6, [sp, #12]
-.L2462:
- ldr r3, [r4, #-524]
- mov fp, #0
- ldrh r1, [r5]
- ldrh r2, [r5, #2]
- str r3, [r4, #1760]
ldr r3, [r4, #-500]
- str fp, [r4, #1752]
+ mov r6, r7
+ sub r7, r7, #2400
+ ldrh r2, [r6], #80
+ mov r9, r7
+ str r0, [r4, #1768]
+ str r3, [r4, #1772]
+ bl ftl_memset
+.L2409:
+ ldrh r3, [r8]
+ cmp r5, r3
+ blt .L2410
+ ldr r6, [r4, #1772]
+ mov r2, #16
+ mov r1, #255
+ ldr r5, .L2421+12
+ ldr fp, .L2421+16
+ mov r0, r6
+ bl ftl_memset
+ ldr r3, .L2421+20
+ strh r3, [r6] @ movhi
+ ldr r3, [r7, #2464]
+ str r3, [r6, #4]
+ movw r3, #2456
+ ldrh r3, [r7, r3]
+ strh r3, [r6, #2] @ movhi
+ ldrh r3, [r5, #4]
+ strh r3, [r6, #8] @ movhi
+ ldrh r3, [r5, #6]
+ strh r3, [r6, #10] @ movhi
+ ldr r3, [r7, #2320]
+ mov r7, #0
+ mov r8, r7
+ strh r3, [r6, #12] @ movhi
+.L2411:
+ ldr r3, [r4, #-524]
+ mov r10, #0
+ ldrh r2, [r5, #2]
+ ldrh r1, [r5]
+ str r3, [r4, #1768]
+ ldr r3, [r4, #-500]
+ str r10, [r4, #1760]
+ str r3, [r4, #1772]
+ orr r3, r2, r1, lsl #10
+ ldrh r0, [r6, #10]
str r3, [r4, #1764]
- orr r3, r2, r1, asl #10
- ldrh r0, [r9, #10]
- str r3, [r4, #1756]
ldrh r3, [r5, #4]
str r0, [sp]
- ldr r0, .L2475+20
+ mov r0, fp
bl printk
- ldr r3, .L2475+24
+ ldr r3, .L2421+24
ldrh r2, [r5, #2]
ldrh r3, [r3]
sub r3, r3, #1
cmp r2, r3
- blt .L2463
- ldr r3, [r7, #2460]
- mov r1, #1
- ldrh r2, [r8]
+ blt .L2412
+ ldr r3, [r9, #2464]
+ ldrh r2, [r5]
+ ldr r0, [r4, #-3608]
add r3, r3, #1
- ldr r0, [r10, #-3612]
- str r3, [r7, #2460]
- str r3, [r9, #4]
- ldrh r3, [r8, #4]
- strh r2, [r9, #8] @ movhi
- strh r2, [r8, #4] @ movhi
- mov r2, r1
- strh r3, [r8] @ movhi
- mov r3, r3, asl #10
- str r3, [r10, #1756]
+ strh r10, [r5, #2] @ movhi
+ str r3, [r9, #2464]
+ str r3, [r6, #4]
+ ldrh r3, [r5, #4]
+ strh r2, [r6, #8] @ movhi
+ strh r2, [r5, #4] @ movhi
+ mov r2, #1
+ strh r3, [r5] @ movhi
+ mov r1, r2
+ lsl r3, r3, #10
+ str r3, [r4, #1764]
str r3, [r0, #4]
- strh fp, [r8, #2] @ movhi
bl FlashEraseBlocks
-.L2463:
- mov r1, #1
- ldr r0, .L2475+28
- mov r3, r1
- mov r2, r1
+.L2412:
+ mov r3, #1
+ ldr r0, .L2421+28
+ mov r2, r3
+ mov r1, r3
bl FlashProgPages
ldrh r3, [r5, #2]
- ldr fp, .L2475
add r3, r3, #1
strh r3, [r5, #2] @ movhi
- ldr r3, [r4, #1752]
+ ldr r3, [r4, #1760]
cmn r3, #1
- bne .L2464
- add r6, r6, #1
- ldr r0, .L2475+32
- ldr r1, [r10, #1756]
- uxth r6, r6
+ bne .L2413
+ add r7, r7, #1
+ ldr r1, [r4, #1764]
+ uxth r7, r7
+ ldr r0, .L2421+32
bl printk
- cmp r6, #3
- bls .L2462
- ldr r0, .L2475+36
- mov r2, r6
- ldr r1, [fp, #1756]
+ cmp r7, #3
+ bls .L2411
+ mov r2, r7
+ ldr r1, [r4, #1764]
+ ldr r0, .L2421+36
bl printk
mov r3, #1
- str r3, [fp, #-3616]
- b .L2459
-.L2464:
- ldr r2, [sp, #12]
- add r2, r2, #1
- str r2, [sp, #12]
- cmp r2, #1
- beq .L2462
- cmp r3, #256
- beq .L2462
-.L2459:
+ str r3, [r4, #-3612]
+.L2408:
mov r0, #0
- add sp, sp, #20
+ add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2476:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2410:
+ ldrh r2, [r10]
+ ldr r3, [r4, #1768]
+ ldr r1, [r6, #4]!
+ mul r0, r5, r2
+ lsl r2, r2, #2
+ add r5, r5, #1
+ add r0, r3, r0, lsl #2
+ bl ftl_memcpy
+ b .L2409
+.L2416:
+ mov r8, #1
+ b .L2411
+.L2413:
+ add r8, r8, #1
+ cmp r8, #1
+ ble .L2416
+ cmp r3, #256
+ bne .L2408
+ b .L2411
+.L2422:
.align 2
-.L2475:
+.L2421:
.word .LANCHOR2
- .word .LANCHOR0
- .word .LANCHOR0+2476
- .word .LANCHOR0+2452
- .word -3887
+ .word .LANCHOR0+2400
+ .word .LANCHOR0+2346
+ .word .LANCHOR0+2456
.word .LC126
- .word .LANCHOR0+2390
- .word .LANCHOR2+1752
+ .word -3887
+ .word .LANCHOR0+2392
+ .word .LANCHOR2+1760
.word .LC127
.word .LC128
.fnend
.size FtlBbmTblFlush, .-FtlBbmTblFlush
.align 2
.global allocate_data_superblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type allocate_data_superblock, %function
allocate_data_superblock:
.fnstart
- @ args = 0, pretend = 0, frame = 16
+ @ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #20
- sub sp, sp, #20
- ldr r4, .L2532
- ldr r3, [r4, #-3616]
+ .pad #28
+ sub sp, sp, #28
+ ldr r4, .L2473
+ ldr r3, [r4, #-3612]
cmp r3, #0
- bne .L2478
- mov r5, r0
- mov r8, r4
-.L2479:
- ldr r3, .L2532+4
- ldr r10, .L2532+8
- cmp r5, r3
- ldrb r2, [r5, #8] @ zero_extendqisi2
- bne .L2480
- ldrh r3, [r5, #-100]
- ldr ip, [r8, #-2708]
- mov r0, r3, lsr #1
- mul lr, ip, r3
- add r1, r0, #1
- add r1, r1, lr, lsr #2
- ldr lr, [r10, #2244]
- cmp lr, #0
+ bne .L2424
+ sub r9, r4, #3520
+ mov r7, r0
+ sub r3, r9, #8
+ str r3, [sp, #12]
+.L2425:
+ ldr r3, .L2473+4
+ ldr r8, .L2473+8
+ ldrb r2, [r7, #8] @ zero_extendqisi2
+ cmp r7, r3
+ bne .L2426
+ ldrh r0, [r9, #-4]
+ ldr lr, [r4, #-2708]
+ lsr ip, r0, #1
+ mul r5, lr, r0
+ add r1, ip, #1
+ add r1, r1, r5, lsr #2
+ ldr r5, [r8, #2248]
uxth r1, r1
- beq .L2481
- ldr lr, [r8, #-3308]
- cmp lr, #39
- bhi .L2481
- cmp lr, #2
- bls .L2506
- cmp ip, #0
- movne r3, #0
- andeq r3, r3, #1
- cmp r3, #0
- moveq r1, r0
- beq .L2481
- b .L2506
-.L2480:
+ cmp r5, #0
+ beq .L2427
+ ldr r5, [r4, #-3308]
+ cmp r5, #39
+ bhi .L2427
+ cmp r5, #2
+ bls .L2453
+ cmp lr, #0
+ movne r0, #0
+ andeq r0, r0, #1
+ cmp r0, #0
+ moveq r1, ip
+ beq .L2427
+.L2453:
+ mov r1, #0
+ b .L2428
+.L2426:
cmp r2, #1
- bne .L2506
- ldr r1, .L2532+12
+ bne .L2453
+ ldr r1, .L2473+12
ldrh r1, [r1]
cmp r1, #1
- beq .L2506
- ldrb r1, [r10, #144] @ zero_extendqisi2
+ beq .L2453
+ ldrb r1, [r8, #152] @ zero_extendqisi2
cmp r1, #0
- bne .L2506
- ldr r0, [r10, #2244]
- ldrh r3, [r3, #-100]
- cmp r0, #0
- mov r1, r3, lsr #3
- beq .L2481
- ldr r0, [r8, #-3308]
- cmp r0, #1
- rsbls r3, r3, r3, asl #3
- ubfxls r1, r3, #3, #16
-.L2481:
+ bne .L2453
+ ldr ip, [r8, #2248]
+ ldrh r0, [r9, #-4]
+ cmp ip, #0
+ lsr r1, r0, #3
+ beq .L2427
+ ldr ip, [r4, #-3308]
+ cmp ip, #1
+ rsbls r0, r0, r0, lsl #3
+ ubfxls r1, r0, #3, #16
+.L2427:
cmp r1, #0
subne r1, r1, #1
uxthne r1, r1
- b .L2482
-.L2506:
- mov r1, #0
-.L2482:
- ldr r0, .L2532+16
+.L2428:
+ ldr r0, [sp, #12]
bl List_pop_index_node
- ldr r2, .L2532+20
- ldrh r3, [r2]
- sub r3, r3, #1
- strh r3, [r2] @ movhi
- ldr r3, .L2532+24
- ldrh r3, [r3]
- uxth r9, r0
- cmp r3, r9
- bls .L2479
- ldr r3, [r8, #-3544]
- mov r7, r9, asl #1
- ldrh r6, [r3, r7]
- cmp r6, #0
- bne .L2479
- strh r9, [r5] @ movhi
- mov r0, r5
- bl make_superblock
- ldrb r3, [r5, #7] @ zero_extendqisi2
- cmp r3, #0
- beq .L2484
- ldr r2, .L2532+28
- add ip, r5, #14
- ldr r0, [r8, #-3612]
- ldrh lr, [r2]
- mov r2, #36
- mov r3, r0
- mla r1, r2, lr, r0
- mov lr, r6
- str r1, [sp]
- b .L2485
-.L2484:
- ldr r3, [r8, #-3544]
- b .L2527
-.L2485:
- ldr r1, [sp]
- cmp r3, r1
- beq .L2529
- str lr, [r3, #8]
- movw fp, #65535
- str lr, [r3, #12]
- add r3, r3, #36
- ldrh r1, [ip, #2]!
- cmp r1, fp
- movne r1, r1, asl #10
- mlane fp, r2, r6, r0
- addne r6, r6, #1
- uxthne r6, r6
- strne r1, [fp, #4]
- b .L2485
-.L2529:
- ldr r3, .L2532+32
- ldr r2, [r10, #2244]
- rsb r3, r3, r5
- clz r3, r3
- cmp r2, #0
- mov r3, r3, lsr #5
- moveq r3, #0
- cmp r3, #0
- beq .L2488
- ldr r3, [r8, #-3608]
- ldrh r3, [r3, r7]
- cmp r3, #40
- movhi r3, #0
- strhib r3, [r8, #-3516]
-.L2488:
- ldrb r3, [r5, #8] @ zero_extendqisi2
- ldr r2, [r4, #-3608]
- cmp r3, #0
- ldr fp, .L2532+36
- ldrh r3, [r2, r7]
- bne .L2489
- cmp r3, #0
- mov r0, r9
- ldrneh r1, [fp]
- moveq r3, #2
- addne r3, r3, r1
- mov r1, #0
- uxthne r3, r3
- strh r3, [r2, r7] @ movhi
- ldr r3, [r4, #-3324]
- add r3, r3, #1
- str r3, [r4, #-3324]
- bl ftl_set_blk_mode
- b .L2491
-.L2489:
- add r3, r3, #1
- strh r3, [r2, r7] @ movhi
- ldr r2, [r4, #-3368]
- mov r1, r9, lsr #5
- ldr r3, [r4, #-3320]
- mov r0, #1
- add r3, r3, #1
- str r3, [r4, #-3320]
- ldr ip, [r2, r1, asl #2]
- and r3, r9, #31
- orr r3, ip, r0, asl r3
- str r3, [r2, r1, asl #2]
-.L2491:
- ldr r3, [r4, #-3608]
- ldr r2, [r4, #-3312]
- ldr r0, [r4, #-3324]
- ldrh r3, [r3, r7]
- cmp r3, r2
- ldrh r2, [fp]
- strhi r3, [r8, #-3312]
- ldr r3, [r4, #-3320]
- mla r0, r0, r2, r3
- ldr r3, .L2532+24
- ldrh r1, [r3]
- bl __aeabi_uidiv
- ldr r2, [r4, #-480]
- ldr r1, [r4, #-3612]
- ldr r3, [r2, #16]
- add r3, r3, #1
- str r3, [r2, #16]
- mov r3, #36
- add r2, r1, #4
- mla r3, r3, r6, r1
- add r3, r3, #40
- str r0, [r4, #-3316]
-.L2493:
- add r2, r2, #36
+ ldrh r2, [r9, #-4]
+ uxth r3, r0
+ ldr r10, .L2473+16
+ str r3, [sp, #4]
+ sub r2, r2, #1
+ strh r2, [r9, #-4] @ movhi
+ ldrh r2, [r10]
cmp r2, r3
- ldrne r1, [r2, #-36]
- bicne r1, r1, #1020
- bicne r1, r1, #3
- strne r1, [r2, #-36]
- bne .L2493
-.L2530:
- ldrb r3, [r10, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L2495
- ldrb r3, [r5, #8] @ zero_extendqisi2
+ bls .L2425
+ ldr r2, [r4, #-3540]
+ lsl r5, r3, #1
+ ldrh r6, [r2, r5]
+ cmp r6, #0
+ bne .L2425
+ ldrh r3, [sp, #4]
+ mov r0, r7
+ strh r3, [r7] @ movhi
+ bl make_superblock
+ ldrb r2, [r7, #7] @ zero_extendqisi2
+ cmp r2, #0
+ beq .L2470
+ ldr r0, [r4, #-3608]
+ add r3, r7, #16
+ ldrh ip, [r10, #-8]
+ mov r1, #36
+ str r3, [sp, #8]
+ add fp, r7, #16
+ mov r2, r0
+ str r1, [sp, #16]
+ mla r3, r1, ip, r0
+ mov ip, r6
+.L2431:
+ cmp r3, r2
+ bne .L2433
+ ldr r2, [r8, #2248]
+ adds r2, r2, #0
+ movne r2, #1
+ cmp r7, r9
+ movne r2, #0
+ cmp r2, #0
+ beq .L2434
+ ldr r2, [r4, #-3604]
+ ldrh r2, [r2, r5]
+ cmp r2, #40
+ movhi r2, #0
+ strbhi r2, [r4, #-3512]
+.L2434:
+ ldrb r2, [r7, #8] @ zero_extendqisi2
+ ldr r1, [r4, #-3604]
+ ldr fp, .L2473+20
+ cmp r2, #0
+ ldrh r2, [r1, r5]
+ bne .L2435
+ cmp r2, #0
+ ldrhne r0, [fp]
+ moveq r2, #2
+ addne r2, r2, r0
+ ldr r0, [sp, #4]
+ strh r2, [r1, r5] @ movhi
+ mov r1, #0
+ ldr r2, [r4, #-3324]
+ add r2, r2, #1
+ str r2, [r4, #-3324]
+ bl ftl_set_blk_mode
+.L2438:
+ ldr r2, [r4, #-3604]
+ ldr r1, [r4, #-3312]
+ ldr ip, [r4, #-3324]
+ ldrh r2, [r2, r5]
+ ldrh r0, [fp]
+ cmp r2, r1
+ ldrh r1, [r10]
+ strhi r2, [r4, #-3312]
+ ldr r2, [r4, #-3320]
+ mla r0, ip, r0, r2
+ bl __aeabi_uidiv
+ ldr r1, [r4, #-480]
+ str r0, [r4, #-3316]
+ ldr r0, [r4, #-3608]
+ ldr r2, [r1, #16]
+ ldr ip, .L2473+24
+ add r2, r2, #1
+ str r2, [r1, #16]
+ mov r1, #36
+ mla r1, r1, r6, r0
+ add r2, r0, #4
+ add r1, r1, #40
+.L2440:
+ add r2, r2, #36
+ cmp r1, r2
+ bne .L2441
+ ldrb r2, [r8, #152] @ zero_extendqisi2
+ cmp r2, #0
+ beq .L2442
+ ldrb r2, [r7, #8] @ zero_extendqisi2
+ ldr r0, [r4, #-3608]
+ cmp r2, #1
mov r2, r6
- ldr r0, [r4, #-3612]
- cmp r3, #1
moveq r1, #0
movne r1, #1
bl FlashEraseBlocks
-.L2495:
- ldrb r1, [r5, #8] @ zero_extendqisi2
+.L2442:
+ ldrb r1, [r7, #8] @ zero_extendqisi2
mov r2, r6
- ldr r0, [r4, #-3612]
- mov fp, #0
+ ldr r0, [r4, #-3608]
+ mov r10, #0
bl FlashEraseBlocks
- add r1, r5, #16
- mov r2, fp
- mov ip, #36
-.L2497:
- uxth r3, fp
- cmp r3, r6
- bcs .L2531
- mul r3, ip, fp
- ldr lr, [r4, #-3612]
- add r0, lr, r3
- ldr r3, [lr, r3]
- cmn r3, #1
- bne .L2498
- ldr r0, [r0, #4]
- add r2, r2, #1
- stmib sp, {r1, r3, ip}
- ubfx r0, r0, #10, #16
- str r2, [sp]
- bl FtlBbmMapBadBlock
- ldmib sp, {r1, r3}
- ldr ip, [sp, #12]
- ldr r2, [sp]
- strh r3, [r1] @ movhi
- ldrb r3, [r5, #7] @ zero_extendqisi2
- sub r3, r3, #1
- strb r3, [r5, #7]
-.L2498:
- add fp, fp, #1
- add r1, r1, #2
- b .L2497
-.L2531:
- cmp r2, #0
- beq .L2500
- mov r0, r9
+ mov fp, r10
+ mov r1, #36
+.L2444:
+ uxth r2, r10
+ cmp r6, r2
+ bhi .L2446
+ cmp fp, #0
+ ble .L2447
+ ldr r0, [sp, #4]
bl update_multiplier_value
bl FtlBbmTblFlush
-.L2500:
- ldrb r3, [r5, #7] @ zero_extendqisi2
- cmp r3, #0
- bne .L2501
- ldr r3, [r4, #-3544]
-.L2527:
- mvn r2, #0
- strh r2, [r3, r7] @ movhi
- b .L2479
-.L2501:
- movw r2, #2388
- ldrh r2, [r10, r2]
- strh r9, [r5] @ movhi
- smulbb r3, r2, r3
- mov r2, #0
- strh r2, [r5, #2] @ movhi
- strb r2, [r5, #6]
- ldr r2, [r4, #-3332]
- ldr r1, [r4, #-3544]
- uxth r3, r3
- strh r3, [r5, #4] @ movhi
- str r2, [r5, #12]
+.L2447:
+ ldrb r1, [r7, #7] @ zero_extendqisi2
+ cmp r1, #0
+ bne .L2448
+.L2470:
+ ldr r2, [r4, #-3540]
+ mvn r1, #0
+ strh r1, [r2, r5] @ movhi
+ b .L2425
+.L2433:
+ str ip, [r2, #8]
+ movw lr, #65535
+ str ip, [r2, #12]
+ add r2, r2, #36
+ ldrh r1, [fp], #2
+ cmp r1, lr
+ ldrne lr, [sp, #16]
+ lslne r1, r1, #10
+ mlane lr, lr, r6, r0
+ addne r6, r6, #1
+ uxthne r6, r6
+ strne r1, [lr, #4]
+ b .L2431
+.L2435:
add r2, r2, #1
- str r2, [r4, #-3332]
- ldrh r2, [r5]
- mov r2, r2, asl #1
- strh r3, [r1, r2] @ movhi
-.L2478:
+ ldr r0, [sp, #4]
+ strh r2, [r1, r5] @ movhi
+ ldr r2, [r4, #-3320]
+ add r2, r2, #1
+ str r2, [r4, #-3320]
+ bl ftl_set_blk_mode.part.9
+ b .L2438
+.L2441:
+ ldr r0, [r2, #-36]
+ and r0, r0, ip
+ str r0, [r2, #-36]
+ b .L2440
+.L2446:
+ mul r2, r1, r10
+ ldr r0, [r4, #-3608]
+ add ip, r0, r2
+ ldr r2, [r0, r2]
+ cmn r2, #1
+ bne .L2445
+ ldr r0, [ip, #4]
+ add fp, fp, #1
+ str r1, [sp, #20]
+ str r2, [sp, #16]
+ ubfx r0, r0, #10, #16
+ bl FtlBbmMapBadBlock
+ ldr r2, [sp, #16]
+ ldr r3, [sp, #8]
+ ldr r1, [sp, #20]
+ strh r2, [r3] @ movhi
+ ldrb r2, [r7, #7] @ zero_extendqisi2
+ sub r2, r2, #1
+ strb r2, [r7, #7]
+.L2445:
+ ldr r3, [sp, #8]
+ add r10, r10, #1
+ add r3, r3, #2
+ str r3, [sp, #8]
+ b .L2444
+.L2448:
+ movw r2, #2390
+ ldrh r3, [sp, #4]
+ ldrh r2, [r8, r2]
+ strh r3, [r7] @ movhi
+ smulbb r2, r2, r1
+ mov r1, #0
+ strh r1, [r7, #2] @ movhi
+ strb r1, [r7, #6]
+ ldr r1, [r4, #-3332]
+ uxth r2, r2
+ strh r2, [r7, #4] @ movhi
+ str r1, [r7, #12]
+ add r1, r1, #1
+ str r1, [r4, #-3332]
+ ldrh r3, [r7]
+ ldr r1, [r4, #-3540]
+ lsl r3, r3, #1
+ strh r2, [r1, r3] @ movhi
+.L2424:
mov r0, #0
- add sp, sp, #20
+ add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2533:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2474:
.align 2
-.L2532:
+.L2473:
.word .LANCHOR2
- .word .LANCHOR2-3428
+ .word .LANCHOR2-3424
.word .LANCHOR0
- .word .LANCHOR0+2340
- .word .LANCHOR2-3532
- .word .LANCHOR2-3528
- .word .LANCHOR0+2328
- .word .LANCHOR0+2320
- .word .LANCHOR2-3524
- .word .LANCHOR0+2380
+ .word .LANCHOR0+2344
+ .word .LANCHOR0+2332
+ .word .LANCHOR0+2382
+ .word -1024
.fnend
.size allocate_data_superblock, .-allocate_data_superblock
.align 2
.global FtlGcFreeBadSuperBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcFreeBadSuperBlk, %function
FtlGcFreeBadSuperBlk:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L2548
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- ldrh r2, [r3, #-2]
- cmp r2, #0
- beq .L2536
- sub r10, r3, #2
- mov r7, r0
- mov r9, #0
- mov r5, r3
- mov r8, r10
-.L2535:
- ldr r3, .L2548+4
- add r2, r3, #2320
- ldrh r1, [r2]
- uxth r2, r9
- cmp r1, r2
- bls .L2545
- add r3, r3, r2
- mov r1, r7
- mov fp, #0
- ldrb r0, [r3, #2348] @ zero_extendqisi2
- bl V2P_block
- mov r6, r0
-.L2537:
- ldrh r3, [r10]
- uxth r4, fp
- cmp r3, r4
- bls .L2546
- mov r3, r4, asl #1
- add ip, r5, r3
- ldrh r3, [r5, r3]
- cmp r3, r6
- bne .L2538
- mov r1, r6
- ldr r0, .L2548+8
- str ip, [sp, #4]
- bl printk
- mov r0, r6
- bl FtlBbmMapBadBlock
- bl FtlBbmTblFlush
- ldrh r2, [r10]
- ldr ip, [sp, #4]
- mov r3, ip
-.L2539:
- cmp r4, r2
- ldrcch r1, [r3, #2]
- addcc r4, r4, #1
- uxthcc r4, r4
- strcch r1, [r3], #2 @ movhi
- bcc .L2539
-.L2547:
- sub r2, r2, #1
- strh r2, [r8] @ movhi
-.L2538:
- add fp, fp, #1
- b .L2537
-.L2546:
- add r9, r9, #1
- b .L2535
-.L2545:
+ ldr r4, .L2488
+ ldrh r3, [r4, #-2]
+ cmp r3, #0
+ beq .L2476
+ ldr r9, .L2488+4
+ mov r6, #0
+ ldr r8, .L2488+8
+ ldr r10, .L2488+12
+ str r0, [sp]
+.L2477:
+ ldrh r2, [r8]
+ uxth r3, r6
+ cmp r2, r3
+ bhi .L2483
bl FtlGcReFreshBadBlk
-.L2536:
+.L2476:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2549:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2483:
+ uxtah r3, r9, r6
+ ldr r1, [sp]
+ mov fp, #0
+ ldrb r0, [r3, #2350] @ zero_extendqisi2
+ bl V2P_block
+ mov r7, r0
+.L2478:
+ ldrh r3, [r4, #-2]
+ uxth r5, fp
+ cmp r3, r5
+ addls r6, r6, #1
+ bls .L2477
+.L2482:
+ uxth r3, fp
+ lsl r1, r3, #1
+ ldrh r1, [r4, r1]
+ cmp r1, r7
+ bne .L2479
+ mov r1, r7
+ mov r0, r10
+ str r3, [sp, #4]
+ bl printk
+ mov r0, r7
+ bl FtlBbmMapBadBlock
+ bl FtlBbmTblFlush
+ ldr r3, [sp, #4]
+ ldrh r1, [r4, #-2]
+ add r3, r4, r3, lsl #1
+.L2480:
+ cmp r5, r1
+ bcc .L2481
+ sub r1, r1, #1
+ strh r1, [r4, #-2] @ movhi
+.L2479:
+ add fp, fp, #1
+ b .L2478
+.L2481:
+ ldrh r0, [r3, #2]!
+ add r5, r5, #1
+ uxth r5, r5
+ strh r0, [r3, #-2] @ movhi
+ b .L2480
+.L2489:
.align 2
-.L2548:
+.L2488:
.word .LANCHOR2-2656
.word .LANCHOR0
+ .word .LANCHOR0+2324
.word .LC129
.fnend
.size FtlGcFreeBadSuperBlk, .-FtlGcFreeBadSuperBlk
.align 2
.global update_vpc_list
+ .syntax unified
+ .arm
+ .fpu softvfp
.type update_vpc_list, %function
update_vpc_list:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L2560
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r3, r0, asl #1
- ldr r1, [r2, #-3544]
- mov r4, r0
+ ldr r2, .L2499
+ lsl r3, r0, #1
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r1, [r2, #-3540]
ldrh r3, [r1, r3]
cmp r3, #0
- bne .L2551
+ bne .L2491
sub r1, r2, #3280
+ mov r4, r0
ldrh r0, [r1, #-4]
+ sub r5, r2, #3520
cmp r0, r4
mvneq r3, #0
- streqh r3, [r1, #-4] @ movhi
- beq .L2553
- sub r1, r2, #3520
- ldrh r1, [r1, #-4]
+ strheq r3, [r1, #-4] @ movhi
+ beq .L2493
+ ldrh r1, [r5]
cmp r1, r4
- beq .L2559
+ beq .L2490
sub r1, r2, #3472
- ldrh r1, [r1, #-4]
+ ldrh r1, [r1]
cmp r1, r4
- beq .L2559
+ beq .L2490
sub r2, r2, #3424
- ldrh r2, [r2, #-4]
+ ldrh r2, [r2]
cmp r2, r4
- beq .L2559
-.L2553:
- ldr r5, .L2560+4
+ beq .L2490
+.L2493:
mov r1, r4
- sub r0, r5, #12
+ ldr r0, .L2499+4
bl List_remove_node
- ldrh r3, [r5]
+ ldrh r3, [r5, #-12]
mov r0, r4
sub r3, r3, #1
- strh r3, [r5] @ movhi
+ strh r3, [r5, #-12] @ movhi
bl free_data_superblock
mov r0, r4
bl FtlGcFreeBadSuperBlk
- mov r0, #1
- ldmfd sp!, {r3, r4, r5, pc}
-.L2551:
+ mov r3, #1
+.L2490:
+ mov r0, r3
+ pop {r4, r5, r6, pc}
+.L2491:
bl List_update_data_list
-.L2559:
- mov r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L2561:
+ mov r3, #0
+ b .L2490
+.L2500:
.align 2
-.L2560:
+.L2499:
.word .LANCHOR2
- .word .LANCHOR2-3536
+ .word .LANCHOR2-3544
.fnend
.size update_vpc_list, .-update_vpc_list
.align 2
.global decrement_vpc_count
+ .syntax unified
+ .arm
+ .fpu softvfp
.type decrement_vpc_count, %function
decrement_vpc_count:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
movw r3, #65535
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
cmp r0, r3
mov r4, r0
- beq .L2563
- ldr r6, .L2573
- mov r5, r0, asl #1
- ldr r3, [r6, #-3544]
+ beq .L2502
+ ldr r6, .L2512
+ lsl r5, r0, #1
+ ldr r3, [r6, #-3540]
ldrh r2, [r3, r5]
cmp r2, #0
subne r2, r2, #1
- strneh r2, [r3, r5] @ movhi
- bne .L2563
- mov r1, r4
- ldr r0, .L2573+4
+ strhne r2, [r3, r5] @ movhi
+ bne .L2502
+ mov r1, r0
+ ldr r0, .L2512+4
bl printk
- ldr r3, [r6, #-3544]
+ ldr r3, [r6, #-3540]
sub r7, r6, #3520
mov r2, #32
- sub r0, r7, #12
+ sub r8, r7, #8
mov r1, r4
+ mov r0, r8
strh r2, [r3, r5] @ movhi
bl test_node_in_list
cmp r0, #0
- beq .L2565
+ beq .L2504
mov r1, r4
- sub r0, r7, #12
+ mov r0, r8
bl List_remove_node
- ldrh r3, [r7, #-8]
+ ldrh r3, [r7, #-4]
mov r0, r4
sub r3, r3, #1
- strh r3, [r7, #-8] @ movhi
+ strh r3, [r7, #-4] @ movhi
bl INSERT_DATA_LIST
- ldr r3, [r6, #-3544]
- ldr r0, .L2573+8
+ ldr r3, [r6, #-3540]
mov r1, r4
+ ldr r0, .L2512+8
ldrh r2, [r3, r5]
bl printk
-.L2565:
+.L2504:
mov r0, r4
bl FtlGcRefreshBlock
- b .L2568
-.L2563:
- ldr r5, .L2573+12
+.L2507:
+ mov r0, #0
+ pop {r4, r5, r6, r7, r8, pc}
+.L2502:
+ ldr r5, .L2512+12
movw r3, #65535
ldrh r0, [r5]
cmp r0, r3
- streqh r4, [r5] @ movhi
- beq .L2568
- cmp r0, r4
- beq .L2568
+ strheq r4, [r5] @ movhi
+ beq .L2507
+ cmp r4, r0
+ beq .L2507
bl update_vpc_list
- strh r4, [r5] @ movhi
adds r0, r0, #0
+ strh r4, [r5] @ movhi
movne r0, #1
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L2568:
- mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L2574:
+ pop {r4, r5, r6, r7, r8, pc}
+.L2513:
.align 2
-.L2573:
+.L2512:
.word .LANCHOR2
.word .LC130
.word .LC131
@@ -15088,59 +15549,44 @@
.size decrement_vpc_count, .-decrement_vpc_count
.align 2
.global FtlSlcSuperblockCheck
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlSlcSuperblockCheck, %function
FtlSlcSuperblockCheck:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
ldrh r3, [r0, #4]
cmp r3, #0
- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
+ bxeq lr
ldrh r2, [r0]
movw r3, #65535
cmp r2, r3
- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
- ldrb r3, [r0, #6] @ zero_extendqisi2
+ bxeq lr
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r4, r0
- ldr r5, .L2588
- ldr r6, .L2588+4
- add r3, r0, r3, asl #1
- add r7, r5, #2320
+ ldrb r3, [r0, #6] @ zero_extendqisi2
+ ldr r5, .L2529
+ ldr r6, .L2529+4
+ add r3, r0, r3, lsl #1
ldrh r3, [r3, #16]
-.L2579:
+.L2518:
movw r1, #65535
cmp r3, r1
- bne .L2587
-.L2581:
- ldrb r3, [r4, #6] @ zero_extendqisi2
- ldrh r2, [r7]
- add r3, r3, #1
- uxtb r3, r3
- strb r3, [r4, #6]
- cmp r2, r3
- ldreqh r3, [r4, #2]
- addeq r3, r3, #1
- streqh r3, [r4, #2] @ movhi
- moveq r3, #0
- streqb r3, [r4, #6]
- ldrb r3, [r4, #6] @ zero_extendqisi2
- add r3, r4, r3, asl #1
- ldrh r3, [r3, #16]
- b .L2579
-.L2587:
+ beq .L2520
ldrb r2, [r4, #8] @ zero_extendqisi2
cmp r2, #1
- bne .L2582
- ldrb r3, [r5, #144] @ zero_extendqisi2
+ bne .L2521
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L2582
+ bne .L2521
ldrh r3, [r4, #2]
- mov r3, r3, asl #1
+ lsl r3, r3, #1
ldrh r3, [r6, r3]
cmp r3, r1
- bne .L2582
+ bne .L2521
ldrh r3, [r4, #4]
ldrh r0, [r4]
sub r3, r3, #1
@@ -15148,178 +15594,191 @@
bl decrement_vpc_count
ldrh r2, [r4, #4]
cmp r2, #0
- bne .L2581
+ bne .L2520
ldrh r3, [r4, #2]
strb r2, [r4, #6]
add r3, r3, #1
strh r3, [r4, #2] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L2582:
- ldr r1, .L2588
- ldrb r3, [r1, #144] @ zero_extendqisi2
- cmp r3, #0
- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
- cmp r2, #1
- ldmnefd sp!, {r3, r4, r5, r6, r7, pc}
- movw r3, #2390
- ldrh r2, [r4, #2]
- ldrh r3, [r1, r3]
+ pop {r4, r5, r6, pc}
+.L2520:
+ ldrb r3, [r4, #6] @ zero_extendqisi2
+ ldr r2, .L2529+8
+ add r3, r3, #1
+ ldrh r2, [r2]
+ uxtb r3, r3
+ strb r3, [r4, #6]
cmp r2, r3
- ldmccfd sp!, {r3, r4, r5, r6, r7, pc}
- ldr r2, .L2588+8
+ ldrheq r3, [r4, #2]
+ addeq r3, r3, #1
+ strheq r3, [r4, #2] @ movhi
+ moveq r3, #0
+ strbeq r3, [r4, #6]
+ ldrb r3, [r4, #6] @ zero_extendqisi2
+ add r3, r4, r3, lsl #1
+ ldrh r3, [r3, #16]
+ b .L2518
+.L2521:
+ ldrb r3, [r5, #152] @ zero_extendqisi2
+ adds r3, r3, #0
+ movne r3, #1
+ cmp r2, #1
+ movne r3, #0
+ cmp r3, #0
+ popeq {r4, r5, r6, pc}
+ movw r3, #2392
+ ldrh r2, [r4, #2]
+ ldrh r3, [r5, r3]
+ cmp r2, r3
+ popcc {r4, r5, r6, pc}
ldrh r3, [r4]
- ldrh ip, [r4, #4]
- ldr r0, [r2, #-3544]
- mov r3, r3, asl #1
- ldrh r2, [r0, r3]
- rsb r2, ip, r2
- strh r2, [r0, r3] @ movhi
- movw r2, #2388
+ ldr r2, .L2529+12
+ ldrh r0, [r4, #4]
+ ldr r1, [r2, #-3540]
+ lsl r3, r3, #1
+ ldrh r2, [r1, r3]
+ sub r2, r2, r0
+ strh r2, [r1, r3] @ movhi
+ movw r2, #2390
+ ldrh r2, [r5, r2]
mov r3, #0
- ldrh r2, [r1, r2]
strh r3, [r4, #4] @ movhi
strb r3, [r4, #6]
strh r2, [r4, #2] @ movhi
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L2589:
+ pop {r4, r5, r6, pc}
+.L2530:
.align 2
-.L2588:
+.L2529:
.word .LANCHOR0
.word .LANCHOR2-2620
+ .word .LANCHOR0+2324
.word .LANCHOR2
.fnend
.size FtlSlcSuperblockCheck, .-FtlSlcSuperblockCheck
.align 2
.global get_new_active_ppa
+ .syntax unified
+ .arm
+ .fpu softvfp
.type get_new_active_ppa, %function
get_new_active_ppa:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
mov r3, #0
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
strb r3, [r0, #10]
mov r4, r0
ldrb r3, [r0, #6] @ zero_extendqisi2
- ldr r7, .L2608
- ldr r9, .L2608+4
- add r3, r0, r3, asl #1
- sub r8, r7, #2320
+ ldr r5, .L2547
+ ldr r7, .L2547+4
+ add r3, r0, r3, lsl #1
ldrh r2, [r3, #16]
-.L2591:
+.L2532:
movw r1, #65535
cmp r2, r1
- ldr r6, .L2608
- bne .L2607
-.L2592:
- ldrb r3, [r4, #6] @ zero_extendqisi2
- ldrh r2, [r7]
- add r3, r3, #1
- uxtb r3, r3
- strb r3, [r4, #6]
- cmp r2, r3
- ldreqh r3, [r4, #2]
- addeq r3, r3, #1
- streqh r3, [r4, #2] @ movhi
- moveq r3, #0
- streqb r3, [r4, #6]
- ldrb r3, [r4, #6] @ zero_extendqisi2
- add r3, r4, r3, asl #1
- ldrh r2, [r3, #16]
- b .L2591
-.L2607:
+ beq .L2533
ldrb r3, [r4, #8] @ zero_extendqisi2
- ldrh r5, [r4, #2]
+ ldrh r6, [r4, #2]
cmp r3, #1
ldrh r3, [r4, #4]
- bne .L2594
- ldrb r0, [r8, #144] @ zero_extendqisi2
+ bne .L2535
+ ldr r0, .L2547+8
+ ldrb r0, [r0, #152] @ zero_extendqisi2
cmp r0, #0
- bne .L2594
- mov r0, r5, asl #1
- ldrh r0, [r9, r0]
+ bne .L2535
+ lsl r0, r6, #1
+ ldrh r0, [r7, r0]
cmp r0, r1
- bne .L2594
+ bne .L2535
sub r3, r3, #1
ldrh r0, [r4]
strh r3, [r4, #4] @ movhi
bl decrement_vpc_count
- b .L2592
-.L2594:
- ldr r7, .L2608+8
- orr r5, r5, r2, asl #10
+.L2533:
+ ldrb r3, [r4, #6] @ zero_extendqisi2
+ ldrh r2, [r5]
+ add r3, r3, #1
+ uxtb r3, r3
+ cmp r2, r3
+ strb r3, [r4, #6]
+ ldrheq r3, [r4, #2]
+ addeq r3, r3, #1
+ strheq r3, [r4, #2] @ movhi
+ moveq r3, #0
+ strbeq r3, [r4, #6]
+ ldrb r3, [r4, #6] @ zero_extendqisi2
+ add r3, r4, r3, lsl #1
+ ldrh r2, [r3, #16]
+ b .L2532
+.L2535:
+ ldr r7, .L2547+4
+ orr r6, r6, r2, lsl #10
sub r3, r3, #1
strh r3, [r4, #4] @ movhi
-.L2595:
+.L2536:
ldrb r3, [r4, #6] @ zero_extendqisi2
- movw r2, #65535
- ldrh r0, [r6]
-.L2597:
+ movw r1, #65535
+ ldrh r0, [r5]
+.L2538:
add r3, r3, #1
uxtb r3, r3
cmp r3, r0
- ldreqh r3, [r4, #2]
+ ldrheq r3, [r4, #2]
addeq r3, r3, #1
- streqh r3, [r4, #2] @ movhi
+ strheq r3, [r4, #2] @ movhi
moveq r3, #0
- add r1, r4, r3, asl #1
- ldrh r1, [r1, #16]
- cmp r1, r2
- beq .L2597
+ add r2, r4, r3, lsl #1
+ ldrh r2, [r2, #16]
+ cmp r2, r1
+ beq .L2538
strb r3, [r4, #6]
ldrb r3, [r4, #8] @ zero_extendqisi2
cmp r3, #1
- bne .L2602
- ldrb r3, [r7, #144] @ zero_extendqisi2
+ bne .L2531
+ ldr r2, .L2547+8
+ ldrb r3, [r2, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L2599
ldrh r3, [r4, #2]
- ldr r2, .L2608+4
- mov r3, r3, asl #1
- ldrh r2, [r2, r3]
- movw r3, #65535
- cmp r2, r3
- bne .L2599
+ bne .L2540
+ lsl r3, r3, #1
+ ldrh r3, [r7, r3]
+ cmp r3, r1
+ bne .L2531
ldrh r3, [r4, #4]
cmp r3, #0
- beq .L2599
+ beq .L2531
sub r3, r3, #1
ldrh r0, [r4]
strh r3, [r4, #4] @ movhi
bl decrement_vpc_count
- b .L2595
-.L2599:
- ldr r1, .L2608+8
- ldrb r3, [r1, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L2602
- movw r3, #2390
- ldrh r2, [r4, #2]
- ldrh r3, [r1, r3]
- cmp r2, r3
- bcc .L2602
- ldr r2, .L2608+12
+ b .L2536
+.L2540:
+ movw r1, #2392
+ ldrh r1, [r2, r1]
+ cmp r3, r1
+ bcc .L2531
ldrh r3, [r4]
+ ldr r1, .L2547+12
ldrh ip, [r4, #4]
- ldr r0, [r2, #-3544]
- mov r3, r3, asl #1
- ldrh r2, [r0, r3]
- rsb r2, ip, r2
- strh r2, [r0, r3] @ movhi
- movw r2, #2388
+ ldr r0, [r1, #-3540]
+ lsl r3, r3, #1
+ ldrh r1, [r0, r3]
+ sub r1, r1, ip
+ strh r1, [r0, r3] @ movhi
+ movw r1, #2390
+ ldrh r2, [r2, r1]
mov r3, #0
- ldrh r2, [r1, r2]
strh r3, [r4, #4] @ movhi
strb r3, [r4, #6]
strh r2, [r4, #2] @ movhi
-.L2602:
- mov r0, r5
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L2609:
+.L2531:
+ mov r0, r6
+ pop {r4, r5, r6, r7, r8, pc}
+.L2548:
.align 2
-.L2608:
- .word .LANCHOR0+2320
+.L2547:
+ .word .LANCHOR0+2324
.word .LANCHOR2-2620
.word .LANCHOR0
.word .LANCHOR2
@@ -15327,320 +15786,323 @@
.size get_new_active_ppa, .-get_new_active_ppa
.align 2
.global FtlVpcTblFlush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlVpcTblFlush, %function
FtlVpcTblFlush:
.fnstart
- @ args = 0, pretend = 0, frame = 0
+ @ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
- ldr r4, .L2628
- ldr r3, [r4, #-3616]
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .pad #12
+ ldr r4, .L2567
+ ldr r3, [r4, #-3612]
cmp r3, #0
- bne .L2612
+ bne .L2551
ldr r2, [r4, #-524]
- sub r6, r4, #3600
+ sub r5, r4, #3296
ldr r7, [r4, #-500]
+ sub r8, r5, #300
+ ldr r6, .L2567+4
mov r1, #255
- ldr r5, .L2628+4
- str r2, [r4, #1760]
- sub r2, r4, #3296
- str r7, [r4, #1764]
- ldrh r2, [r2, #-4]
+ str r2, [r4, #1768]
+ ldrh r2, [r5, #-4]
+ str r7, [r4, #1772]
+ add r9, r6, #2400
str r3, [r7, #12]
strh r2, [r7, #2] @ movhi
- ldr r2, .L2628+8
+ ldr r2, .L2567+8
strh r2, [r7] @ movhi
ldr r2, [r4, #-3292]
stmib r7, {r2, r3}
- ldr r3, .L2628+12
- ldrh r2, [r6, #78]
- str r3, [r4, #-3600]
- ldr r3, .L2628+16
+ ldr r3, .L2567+12
str r3, [r4, #-3596]
- add r3, r6, #300
- ldrh r3, [r3, #6]
- strh r3, [r6, #8] @ movhi
- movw r3, #2342
- ldrh r3, [r5, r3]
- strb r3, [r4, #-3590]
+ ldr r3, .L2567+16
+ str r3, [r4, #-3592]
+ ldrh r3, [r5, #2]
+ strh r3, [r8, #8] @ movhi
+ movw r3, #2346
+ ldrh r3, [r6, r3]
+ strb r3, [r4, #-3586]
sub r3, r4, #3520
- ldrh r3, [r3, #-4]
- strh r3, [r6, #14] @ movhi
- ldrb r3, [r4, #-3518] @ zero_extendqisi2
- orr r3, r3, r2, asl #6
- strh r3, [r6, #16] @ movhi
- ldrb r3, [r4, #-3516] @ zero_extendqisi2
- ldrh r2, [r6, #126]
- strb r3, [r4, #-3589]
+ ldrh r2, [r3]
+ strh r2, [r8, #14] @ movhi
+ ldrh r2, [r3, #2]
+ ldrb r3, [r4, #-3514] @ zero_extendqisi2
+ orr r3, r3, r2, lsl #6
+ strh r3, [r8, #16] @ movhi
+ ldrb r3, [r4, #-3512] @ zero_extendqisi2
+ strb r3, [r4, #-3585]
sub r3, r4, #3472
- ldrh r3, [r3, #-4]
- strh r3, [r6, #18] @ movhi
- ldrb r3, [r4, #-3470] @ zero_extendqisi2
- orr r3, r3, r2, asl #6
- strh r3, [r6, #20] @ movhi
- ldrb r3, [r4, #-3468] @ zero_extendqisi2
- strb r3, [r4, #-3588]
+ ldrh r2, [r3]
+ strh r2, [r8, #18] @ movhi
+ ldrh r2, [r3, #2]
+ ldrb r3, [r4, #-3466] @ zero_extendqisi2
+ orr r3, r3, r2, lsl #6
+ strh r3, [r8, #20] @ movhi
+ ldrb r3, [r4, #-3464] @ zero_extendqisi2
+ strb r3, [r4, #-3584]
sub r3, r4, #3424
- ldrh r3, [r3, #-4]
- strh r3, [r6, #22] @ movhi
- ldrh r2, [r6, #174]
- ldrb r3, [r4, #-3422] @ zero_extendqisi2
- ldr r0, [r4, #1760]
- orr r3, r3, r2, asl #6
- strh r3, [r6, #24] @ movhi
- ldrb r3, [r4, #-3420] @ zero_extendqisi2
- strb r3, [r4, #-3587]
+ ldrh r2, [r3]
+ strh r2, [r8, #22] @ movhi
+ ldrh r2, [r3, #2]
+ ldrb r3, [r4, #-3418] @ zero_extendqisi2
+ ldr r0, [r4, #1768]
+ orr r3, r3, r2, lsl #6
+ strh r3, [r8, #24] @ movhi
+ ldrb r3, [r4, #-3416] @ zero_extendqisi2
+ strb r3, [r4, #-3583]
ldr r3, [r4, #-3324]
- str r3, [r4, #-3568]
- ldr r3, [r4, #-3332]
- str r3, [r4, #-3560]
- ldr r3, [r4, #-3328]
str r3, [r4, #-3564]
+ ldr r3, [r4, #-3332]
+ str r3, [r4, #-3556]
+ ldr r3, [r4, #-3328]
+ str r3, [r4, #-3560]
sub r3, r4, #2656
ldrh r2, [r3, #-10]
ldrh r3, [r3, #-8]
- strh r2, [r6, #44] @ movhi
- strh r3, [r6, #46] @ movhi
- movw r3, #2398
- ldrh r2, [r5, r3]
+ strh r2, [r8, #44] @ movhi
+ ldrh r2, [r9]
+ strh r3, [r5, #-254] @ movhi
bl ftl_memset
- mov r1, r6
+ mov r1, r8
mov r2, #48
- movw r6, #2328
- ldr r0, [r4, #1760]
+ movw r8, #2332
+ ldr r0, [r4, #1768]
bl ftl_memcpy
- ldrh r2, [r5, r6]
- ldr r0, [r4, #1760]
- ldr r1, [r4, #-3544]
- mov r2, r2, asl #1
+ ldrh r2, [r6, r8]
+ ldr r0, [r4, #1768]
+ ldr r1, [r4, #-3540]
+ lsl r2, r2, #1
add r0, r0, #48
bl ftl_memcpy
- ldrh r2, [r5, r6]
- ldr r0, [r4, #1760]
- ldr r1, [r4, #-3368]
- mov r3, r2, asl #1
- mov r2, r2, lsr #3
- add r3, r3, #51
+ ldrh r0, [r6, r8]
+ ldr r3, [r4, #1768]
+ ldr r1, [r6, #32]
+ lsr r2, r0, #3
+ lsl r0, r0, #1
+ add r0, r0, #51
add r2, r2, #4
- bic r3, r3, #3
- add r0, r0, r3
+ bic r0, r0, #3
+ add r0, r3, r0
bl ftl_memcpy
- add r3, r5, #2432
- ldrh r3, [r3]
+ movw r3, #2436
+ str r9, [sp, #4]
+ ldrh r3, [r6, r3]
cmp r3, #0
- beq .L2613
- ldrh r2, [r5, r6]
- ldr r0, [r4, #1760]
+ beq .L2552
+ ldrh r0, [r6, r8]
+ movw r3, #2428
+ ldrh r2, [r6, r3]
ldr r1, [r4, #-452]
- mov r3, r2, lsr #3
- add r3, r3, r2, asl #1
- movw r2, #2424
+ lsr r3, r0, #3
+ lsl r2, r2, #2
+ add r3, r3, r0, lsl #1
+ ldr r0, [r4, #1768]
add r3, r3, #52
- ldrh r2, [r5, r2]
ubfx r3, r3, #2, #14
- mov r2, r2, asl #2
- add r0, r0, r3, asl #2
+ add r0, r0, r3, lsl #2
bl ftl_memcpy
-.L2613:
- mov r0, #0
- ldr r8, .L2628
- bl FtlUpdateVaildLpn
- ldr r10, .L2628+20
- mov r6, #0
+.L2552:
+ ldr r10, .L2567+20
+ mov r8, #0
movw r9, #65535
-.L2614:
+ sub r5, r5, #4
+ mov r0, #0
+ mov fp, r10
+ bl FtlUpdateVaildLpn
+.L2553:
ldr r3, [r4, #-524]
- ldrh r2, [r10]
- ldr fp, .L2628+24
- str r3, [r4, #1760]
+ ldrh r1, [r5, #2]
+ ldrh r2, [r5]
+ str r3, [r4, #1768]
ldr r3, [r4, #-500]
- ldrh r1, [r10, #2]
+ str r3, [r4, #1772]
+ orr r3, r1, r2, lsl #10
str r3, [r4, #1764]
- orr r3, r1, r2, asl #10
- str r3, [r4, #1756]
- ldrh r3, [fp]
+ ldrh r3, [r10]
sub r3, r3, #1
cmp r1, r3
- blt .L2615
+ blt .L2554
mov r3, #0
- ldrh r9, [r10, #4]
- strh r3, [r10, #2] @ movhi
- strh r2, [r10, #4] @ movhi
+ ldrh r9, [r5, #4]
+ strh r3, [r5, #2] @ movhi
+ strh r2, [r5, #4] @ movhi
bl FtlFreeSysBlkQueueOut
- ldr r3, [r8, #-3332]
+ ldr r3, [r4, #-3332]
+ strh r0, [r5] @ movhi
add r2, r3, #1
- str r2, [r8, #-3332]
- str r3, [r8, #-3292]
- mov r2, r0, asl #10
- strh r0, [r10] @ movhi
- str r2, [r8, #1756]
+ str r3, [r4, #-3292]
+ str r2, [r4, #-3332]
+ lsl r2, r0, #10
+ str r2, [r4, #1764]
str r3, [r7, #4]
strh r0, [r7, #2] @ movhi
-.L2615:
- ldrb r3, [r5] @ zero_extendqisi2
+.L2554:
+ ldrb r3, [r6, #36] @ zero_extendqisi2
cmp r3, #0
- beq .L2616
- ldr r3, .L2628+28
+ beq .L2555
+ ldr r3, [sp, #4]
ldr r0, [r4, #-524]
ldrh r1, [r3]
bl js_hash
str r0, [r7, #12]
-.L2616:
- mov r1, #1
- ldr r0, .L2628+32
- mov r2, r1
- mov r3, r1
+.L2555:
+ mov r3, #1
+ ldr r0, .L2567+24
+ mov r2, r3
+ mov r1, r3
bl FlashProgPages
- ldr r3, .L2628+20
- ldr r2, .L2628+20
- ldrh r3, [r3, #2]
+ ldrh r3, [r5, #2]
+ ldr r2, [r4, #1760]
add r3, r3, #1
uxth r3, r3
- strh r3, [r2, #2] @ movhi
- ldr r2, [r4, #1752]
cmn r2, #1
- bne .L2617
+ strh r3, [r5, #2] @ movhi
+ bne .L2556
cmp r3, #1
- add r6, r6, #1
- ldreqh r3, [fp]
- uxth r6, r6
+ add r8, r8, #1
+ ldrheq r3, [fp]
+ uxth r8, r8
subeq r3, r3, #1
- streqh r3, [r10, #2] @ movhi
- cmp r6, #3
- bls .L2614
- ldr r0, .L2628+36
- mov r2, r6
- ldr r1, [r4, #1756]
+ strheq r3, [r5, #2] @ movhi
+ cmp r8, #3
+ bls .L2553
+ mov r2, r8
+ ldr r1, [r4, #1764]
+ ldr r0, .L2567+28
bl printk
mov r3, #1
- str r3, [r4, #-3616]
- b .L2612
-.L2617:
- cmp r2, #256
- cmpne r3, #1
- beq .L2614
+ str r3, [r4, #-3612]
+.L2551:
+ mov r0, #0
+ add sp, sp, #12
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2556:
+ cmp r3, #1
+ cmpne r2, #256
+ beq .L2553
movw r3, #65535
cmp r9, r3
- beq .L2612
- mov r0, r9
+ beq .L2551
mov r1, #1
+ mov r0, r9
bl FtlFreeSysBlkQueueIn
-.L2612:
- mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2629:
+ b .L2551
+.L2568:
.align 2
-.L2628:
+.L2567:
.word .LANCHOR2
.word .LANCHOR0
.word -3932
.word 1179929683
.word 1342177379
- .word .LANCHOR2-3300
- .word .LANCHOR0+2390
- .word .LANCHOR0+2398
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2392
+ .word .LANCHOR2+1760
.word .LC132
.fnend
.size FtlVpcTblFlush, .-FtlVpcTblFlush
.align 2
.global FtlSuperblockPowerLostFix
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlSuperblockPowerLostFix, %function
FtlSuperblockPowerLostFix:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #44
- sub sp, sp, #44
- ldr r5, .L2647
- ldr r3, [r5, #-3616]
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ .pad #40
+ sub sp, sp, #40
+ ldr r5, .L2585
+ ldr r10, [r5, #-3612]
+ cmp r10, #0
+ bne .L2569
+ ldr r8, .L2585+4
+ ldrb r3, [r8, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L2630
- ldr r8, .L2647+4
- ldrb r6, [r8, #144] @ zero_extendqisi2
- cmp r6, #0
- beq .L2646
- ldrb r6, [r0, #8] @ zero_extendqisi2
- cmp r6, #1
- ldreqh fp, [r0, #4]
- beq .L2632
- mov r6, r3
-.L2646:
- mov fp, #12
-.L2632:
- ldr r7, [r5, #-500]
+ beq .L2580
+ ldrb r3, [r0, #8] @ zero_extendqisi2
+ cmp r3, #1
+ ldrheq r7, [r0, #4]
+ moveq r10, r3
+ beq .L2571
+.L2580:
+ mov r7, #12
+.L2571:
mvn r3, #0
+ ldr r6, [r5, #-500]
str r3, [sp, #20]
mov r9, #0
ldr r3, [r5, #-524]
movw r2, #61589
- str r7, [sp, #16]
+ str r6, [sp, #16]
mov r4, r0
- ldr r10, .L2647
str r3, [sp, #12]
mvn r3, #2
- str r3, [r7, #8]
+ str r3, [r6, #8]
mvn r3, #1
- str r3, [r7, #12]
+ str r3, [r6, #12]
ldrh r3, [r0]
- strh r9, [r7] @ movhi
- strh r3, [r7, #2] @ movhi
+ strh r9, [r6] @ movhi
+ strh r3, [r6, #2] @ movhi
ldr r3, [r5, #-524]
str r2, [r3]
- ldr r2, .L2647+8
+ ldr r2, .L2585+8
ldr r3, [r5, #-524]
str r2, [r3, #4]
-.L2633:
- subs fp, fp, #1
- bcc .L2636
+.L2572:
+ subs r7, r7, #1
+ bcc .L2575
ldrh r3, [r4, #4]
cmp r3, #0
- bne .L2634
-.L2636:
+ bne .L2573
+.L2575:
ldrh r3, [r4]
- ldr r1, [r5, #-3544]
+ ldr r1, [r5, #-3540]
ldrh r0, [r4, #4]
- mov r3, r3, asl #1
+ lsl r3, r3, #1
ldrh r2, [r1, r3]
- rsb r2, r0, r2
+ sub r2, r2, r0
strh r2, [r1, r3] @ movhi
- movw r3, #2388
+ movw r3, #2390
ldrh r3, [r8, r3]
strh r3, [r4, #2] @ movhi
mov r3, #0
strb r3, [r4, #6]
strh r3, [r4, #4] @ movhi
- b .L2630
-.L2634:
+.L2569:
+ add sp, sp, #40
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L2573:
mov r0, r4
bl get_new_active_ppa
cmn r0, #1
str r0, [sp, #8]
- beq .L2636
+ beq .L2575
ldr r3, [r5, #-3328]
+ mov r2, r10
mov r1, #1
- mov r2, r6
add r0, sp, #4
- str r3, [r7, #4]
+ str r3, [r6, #4]
add r3, r3, #1
cmn r3, #1
moveq r3, r9
- str r3, [r10, #-3328]
+ str r3, [r5, #-3328]
mov r3, #0
bl FlashProgPages
ldrh r0, [r4]
bl decrement_vpc_count
- b .L2633
-.L2630:
- add sp, sp, #44
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2648:
+ b .L2572
+.L2586:
.align 2
-.L2647:
+.L2585:
.word .LANCHOR2
.word .LANCHOR0
.word 305419896
@@ -15648,32 +16110,35 @@
.size FtlSuperblockPowerLostFix, .-FtlSuperblockPowerLostFix
.align 2
.global ftl_map_blk_gc
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_map_blk_gc, %function
ftl_map_blk_gc:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
mov r4, r0
ldr r5, [r0, #12]
- ldr r7, [r0, #24]
+ ldr r10, [r0, #24]
bl ftl_free_no_use_map_blk
ldrh r3, [r4, #10]
ldrh r2, [r4, #8]
+ ldr fp, .L2600
sub r3, r3, #4
- ldr r8, .L2663
cmp r2, r3
- blt .L2650
+ blt .L2588
uxth r0, r0
- mov r0, r0, asl #1
- ldrh r10, [r5, r0]
- cmp r10, #0
- beq .L2650
+ lsl r0, r0, #1
+ ldrh r9, [r5, r0]
+ cmp r9, #0
+ beq .L2588
ldr r3, [r4, #32]
cmp r3, #0
- bne .L2650
+ bne .L2588
mov r2, #1
str r2, [r4, #32]
strh r3, [r5, r0] @ movhi
@@ -15681,114 +16146,117 @@
ldrh r2, [r4, #2]
sub r3, r3, #1
strh r3, [r4, #8] @ movhi
- movw r3, #2390
- ldrh r3, [r8, r3]
+ movw r3, #2392
+ ldrh r3, [fp, r3]
cmp r2, r3
- bcc .L2651
+ bcc .L2589
mov r0, r4
bl ftl_map_blk_alloc_new_blk
-.L2651:
- ldr r5, .L2663+4
- mov fp, #0
-.L2652:
- ldrh r3, [r4, #6]
- uxth r6, fp
- cmp r3, r6
- bls .L2662
- ldr r3, [r7, r6, asl #2]
- add ip, r7, r6, asl #2
- cmp r10, r3, lsr #10
- bne .L2653
- ldr r3, [r5, #-520]
+.L2589:
+ ldr r5, .L2600+4
+ mov r6, #0
+.L2590:
+ ldrh r2, [r4, #6]
+ uxth r3, r6
+ cmp r2, r3
+ bhi .L2595
mov r1, #1
- ldr r9, [r5, #-500]
- mov r2, r1
- ldr r0, .L2663+8
- str r3, [r5, #1760]
- str r9, [r5, #1764]
- ldr r3, [r7, r6, asl #2]
- str ip, [sp, #4]
- str r3, [r5, #1756]
- bl FlashReadPages
- ldr r3, [r5, #1752]
- cmn r3, #1
- ldr r3, .L2663+4
- ldr ip, [sp, #4]
- bne .L2654
-.L2656:
- mov r2, #0
- ldr r0, .L2663+12
- str r2, [ip]
- ldr r1, [r3, #1756]
- ldrh r2, [r9, #8]
- str r3, [sp, #4]
- bl printk
- mov r2, #1
- ldr r3, [sp, #4]
- str r2, [r3, #-3616]
- b .L2655
-.L2654:
- ldrh r1, [r9, #8]
- cmp r1, r6
- bne .L2656
- ldrh r0, [r9]
- ldrh r2, [r4, #4]
- cmp r0, r2
- bne .L2656
- mov r0, r4
- ldr r2, [r5, #1760]
- bl FtlMapWritePage
-.L2653:
- add fp, fp, #1
- b .L2652
-.L2662:
- mov r0, r10
- mov r1, #1
+ mov r0, r9
bl FtlFreeSysBlkQueueIn
mov r3, #0
str r3, [r4, #32]
-.L2650:
- movw r3, #2390
+.L2588:
+ movw r3, #2392
ldrh r2, [r4, #2]
- ldrh r3, [r8, r3]
+ ldrh r3, [fp, r3]
cmp r2, r3
- bcc .L2655
+ bcc .L2593
mov r0, r4
bl ftl_map_blk_alloc_new_blk
-.L2655:
+ b .L2593
+.L2595:
+ uxth r7, r6
+ add r2, r10, r7, lsl #2
+ str r2, [sp]
+ ldr r2, [r10, r7, lsl #2]
+ cmp r9, r2, lsr #10
+ bne .L2591
+ ldr r2, [r5, #-520]
+ ldr r8, [r5, #-500]
+ ldr r0, .L2600+8
+ str r2, [r5, #1768]
+ str r8, [r5, #1772]
+ ldr r2, [r10, r7, lsl #2]
+ str r3, [sp, #4]
+ str r2, [r5, #1764]
+ mov r2, #1
+ mov r1, r2
+ bl FlashReadPages
+ ldr r2, [r5, #1760]
+ ldr r3, [sp, #4]
+ cmn r2, #1
+ bne .L2592
+.L2594:
+ ldr r2, [sp]
+ mov r3, #0
+ ldr r0, .L2600+12
+ str r3, [r2]
+ ldrh r2, [r8, #8]
+ ldr r1, [r5, #1764]
+ bl printk
+ mov r3, #1
+ str r3, [r5, #-3612]
+.L2593:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2664:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2592:
+ ldrh r2, [r8, #8]
+ cmp r2, r3
+ bne .L2594
+ ldrh r2, [r8]
+ ldrh r3, [r4, #4]
+ cmp r2, r3
+ bne .L2594
+ ldr r2, [r5, #1768]
+ mov r1, r7
+ mov r0, r4
+ bl FtlMapWritePage
+.L2591:
+ add r6, r6, #1
+ b .L2590
+.L2601:
.align 2
-.L2663:
+.L2600:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR2+1752
+ .word .LANCHOR2+1760
.word .LC133
.fnend
.size ftl_map_blk_gc, .-ftl_map_blk_gc
.align 2
.global Ftl_write_map_blk_to_last_page
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_write_map_blk_to_last_page, %function
Ftl_write_map_blk_to_last_page:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
- ldr r5, .L2677
- ldr r7, [r0, #12]
- ldr r9, [r0, #24]
- ldr r6, [r5, #-3616]
+ ldr r5, .L2613
+ ldr r6, [r5, #-3612]
cmp r6, #0
- bne .L2666
+ bne .L2603
ldrh r3, [r0]
movw r2, #65535
mov r4, r0
+ ldr r7, [r0, #12]
cmp r3, r2
- bne .L2667
+ bne .L2604
ldrh r3, [r0, #8]
add r3, r3, #1
strh r3, [r0, #8] @ movhi
@@ -15796,479 +16264,346 @@
strh r0, [r7] @ movhi
ldr r3, [r4, #28]
strh r6, [r4, #2] @ movhi
- add r3, r3, #1
strh r6, [r4] @ movhi
+ add r3, r3, #1
str r3, [r4, #28]
- b .L2666
-.L2667:
- mov r3, r3, asl #1
- ldr r10, .L2677+4
+.L2603:
+ mov r0, #0
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L2604:
+ lsl r3, r3, #1
+ ldr r8, [r0, #24]
+ ldr r10, .L2613+4
mov r1, #255
- ldrh r8, [r7, r3]
+ ldrh r9, [r7, r3]
ldrh r3, [r0, #2]
ldr r7, [r5, #-500]
- orr r3, r3, r8, asl #10
- str r3, [r5, #1756]
+ orr r3, r3, r9, lsl #10
+ str r7, [r5, #1772]
+ str r3, [r5, #1764]
ldr r3, [r5, #-524]
- str r7, [r5, #1764]
- str r3, [r5, #1760]
+ str r3, [r5, #1768]
ldr r3, [r0, #28]
str r3, [r7, #4]
- ldr r3, .L2677+8
+ ldr r3, .L2613+8
strh r3, [r7, #8] @ movhi
ldrh r3, [r0, #4]
- strh r8, [r7, #2] @ movhi
+ strh r9, [r7, #2] @ movhi
strh r3, [r7] @ movhi
- movw r3, #2390
+ movw r3, #2392
ldrh r2, [r10, r3]
ldr r0, [r5, #-524]
- mov r2, r2, asl #3
+ lsl r2, r2, #3
bl ftl_memset
mov r2, r6
-.L2668:
- ldrh r1, [r4, #6]
- uxth r3, r2
- cmp r1, r3
- bls .L2676
- ldr r1, [r9, r3, asl #2]
- cmp r8, r1, lsr #10
- bne .L2669
- add r6, r6, #1
- ldr r1, [r5, #-524]
- uxth r6, r6
- str r3, [r1, r6, asl #3]
- ldr r1, [r9, r3, asl #2]
- ldr r3, [r5, #-524]
- add r3, r3, r6, asl #3
- str r1, [r3, #4]
-.L2669:
- add r2, r2, #1
- b .L2668
-.L2676:
- ldrb r3, [r10] @ zero_extendqisi2
+ mov r3, r6
+.L2605:
+ ldrh r0, [r4, #6]
+ uxth r1, r2
+ cmp r0, r1
+ bhi .L2607
+ ldrb r3, [r10, #36] @ zero_extendqisi2
cmp r3, #0
- beq .L2671
- ldr r2, .L2677+4
- movw r3, #2398
- ldr r0, [r5, #1760]
- ldrh r1, [r2, r3]
+ beq .L2608
+ ldr r3, .L2613+12
+ ldr r0, [r5, #1768]
+ ldrh r1, [r3]
bl js_hash
str r0, [r7, #12]
-.L2671:
- mov r1, #1
+.L2608:
+ mov r2, #1
mov r3, #0
- ldr r0, .L2677+12
- mov r2, r1
+ mov r1, r2
+ ldr r0, .L2613+16
bl FlashProgPages
ldrh r3, [r4, #2]
mov r0, r4
add r3, r3, #1
strh r3, [r4, #2] @ movhi
bl ftl_map_blk_gc
-.L2666:
- mov r0, #0
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L2678:
+ b .L2603
+.L2607:
+ uxth r1, r2
+ ldr r0, [r8, r1, lsl #2]
+ cmp r9, r0, lsr #10
+ bne .L2606
+ ldr r0, [r5, #-524]
+ add r3, r3, #1
+ uxth r3, r3
+ str r1, [r0, r3, lsl #3]
+ ldr r0, [r8, r1, lsl #2]
+ ldr r1, [r5, #-524]
+ add r1, r1, r3, lsl #3
+ str r0, [r1, #4]
+.L2606:
+ add r2, r2, #1
+ b .L2605
+.L2614:
.align 2
-.L2677:
+.L2613:
.word .LANCHOR2
.word .LANCHOR0
.word -1291
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2400
+ .word .LANCHOR2+1760
.fnend
.size Ftl_write_map_blk_to_last_page, .-Ftl_write_map_blk_to_last_page
.align 2
.global FtlMapWritePage
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlMapWritePage, %function
FtlMapWritePage:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
mov r4, r0
- ldr r10, .L2698
- mov r8, r1
- ldr fp, .L2698+4
- mov r5, #0
- str r2, [sp]
- mov r9, r10
-.L2680:
- ldr r3, [r10, #-3348]
- ldr r6, .L2698
+ ldr r7, .L2634
+ mov r9, r1
+ mov fp, r2
+ mov r6, #0
+ ldr r10, .L2634+4
+ mov r5, r7
+.L2616:
+ ldr r3, [r7, #-3348]
add r3, r3, #1
- str r3, [r10, #-3348]
- ldrh r3, [fp]
+ str r3, [r7, #-3348]
+ ldrh r3, [r10]
ldrh r2, [r4, #2]
sub r3, r3, #1
cmp r2, r3
- bge .L2681
+ bge .L2617
ldrh r2, [r4]
movw r3, #65535
cmp r2, r3
- bne .L2682
-.L2681:
+ bne .L2618
+.L2617:
mov r0, r4
bl Ftl_write_map_blk_to_last_page
-.L2682:
- ldr r1, [r9, #-3616]
+.L2618:
+ ldr r1, [r5, #-3612]
cmp r1, #0
- bne .L2683
+ bne .L2619
ldrh r3, [r4]
ldr r2, [r4, #12]
- ldr r0, [r10, #-500]
- mov r3, r3, asl #1
- ldrh r7, [r2, r3]
+ ldr r0, [r5, #-500]
+ lsl r3, r3, #1
+ ldrh r8, [r2, r3]
mov r2, #16
ldrh r3, [r4, #2]
- str r0, [r10, #1764]
- orr r3, r3, r7, asl #10
- str r3, [r10, #1756]
- ldr r3, [sp]
- str r3, [r10, #1760]
+ str fp, [r5, #1768]
+ str r0, [r5, #1772]
+ orr r3, r3, r8, lsl #10
+ str r3, [r5, #1764]
bl ftl_memset
+ ldr r3, [r5, #1772]
ldr r2, [r4, #28]
- ldr r3, [r10, #1764]
+ strh r9, [r3, #8] @ movhi
str r2, [r3, #4]
- strh r8, [r3, #8] @ movhi
ldrh r2, [r4, #4]
- strh r7, [r3, #2] @ movhi
- strh r2, [r3] @ movhi
- ldr r2, .L2698+8
- ldrb r2, [r2] @ zero_extendqisi2
- cmp r2, #0
- beq .L2684
- ldr r2, .L2698+12
- ldr r0, [r10, #1760]
str r3, [sp, #4]
+ strh r8, [r3, #2] @ movhi
+ strh r2, [r3] @ movhi
+ ldr r2, .L2634+8
+ ldrb r1, [r2, #36] @ zero_extendqisi2
+ cmp r1, #0
+ beq .L2620
+ add r2, r2, #2400
+ ldr r0, [r5, #1768]
ldrh r1, [r2]
bl js_hash
ldr r3, [sp, #4]
str r0, [r3, #12]
-.L2684:
- mov r1, #1
- ldr r0, .L2698+16
- mov r2, r1
- mov r3, r1
+.L2620:
+ mov r3, #1
+ ldr r0, .L2634+12
+ mov r2, r3
+ mov r1, r3
bl FlashProgPages
ldrh r3, [r4, #2]
add r3, r3, #1
uxth r3, r3
strh r3, [r4, #2] @ movhi
- ldr r2, [r9, #1752]
+ ldr r2, [r5, #1760]
cmn r2, #1
- bne .L2685
- ldr r0, .L2698+20
- add r5, r5, #1
- ldr r1, [r10, #1756]
+ bne .L2621
+ ldr r1, [r5, #1764]
+ add r6, r6, #1
+ ldr r0, .L2634+16
+ uxth r6, r6
bl printk
ldrh r3, [r4, #2]
- uxth r5, r5
cmp r3, #2
- ldrls r3, .L2698+4
- ldrlsh r3, [r3]
+ ldrhls r3, [r10]
subls r3, r3, #1
- strlsh r3, [r4, #2] @ movhi
- cmp r5, #3
- bls .L2680
- ldr r0, .L2698+24
- mov r2, r5
- ldr r1, [r6, #1756]
+ strhls r3, [r4, #2] @ movhi
+ cmp r6, #3
+ bls .L2616
+ mov r2, r6
+ ldr r1, [r5, #1764]
+ ldr r0, .L2634+20
bl printk
mov r3, #1
- str r3, [r6, #-3616]
- b .L2683
-.L2685:
- cmp r2, #0
- strneh r7, [r4, #40] @ movhi
- cmp r2, #256
- cmpne r3, #1
- beq .L2689
- ldr r3, [r4, #36]
- cmp r3, #0
- beq .L2690
-.L2689:
- mov r3, #0
- str r3, [r4, #36]
- b .L2680
-.L2690:
- ldr r2, [r6, #1756]
- ldr r3, [r4, #24]
- str r2, [r3, r8, asl #2]
-.L2683:
+ str r3, [r5, #-3612]
+.L2619:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2699:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2621:
+ cmp r2, #0
+ strhne r8, [r4, #40] @ movhi
+ cmp r3, #1
+ cmpne r2, #256
+ beq .L2625
+ ldr r3, [r4, #36]
+ cmp r3, #0
+ beq .L2626
+.L2625:
+ mov r3, #0
+ str r3, [r4, #36]
+ b .L2616
+.L2626:
+ ldr r2, [r5, #1764]
+ ldr r3, [r4, #24]
+ str r2, [r3, r9, lsl #2]
+ b .L2619
+.L2635:
.align 2
-.L2698:
+.L2634:
.word .LANCHOR2
- .word .LANCHOR0+2390
+ .word .LANCHOR0+2392
.word .LANCHOR0
- .word .LANCHOR0+2398
- .word .LANCHOR2+1752
+ .word .LANCHOR2+1760
.word .LC134
.word .LC135
.fnend
.size FtlMapWritePage, .-FtlMapWritePage
.align 2
.global flush_l2p_region
+ .syntax unified
+ .arm
+ .fpu softvfp
.type flush_l2p_region, %function
flush_l2p_region:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r4, #12
- ldr r5, .L2702
+ ldr r5, .L2638
mul r4, r4, r0
+ ldr r3, [r5, #-3376]
sub r0, r5, #432
- ldr r3, [r5, #-3380]
add r2, r3, r4
ldrh r1, [r3, r4]
ldr r2, [r2, #8]
bl FtlMapWritePage
- ldr r3, [r5, #-3380]
+ ldr r3, [r5, #-3376]
mov r0, #0
add r4, r3, r4
ldr r3, [r4, #4]
bic r3, r3, #-2147483648
str r3, [r4, #4]
- ldmfd sp!, {r3, r4, r5, pc}
-.L2703:
+ pop {r4, r5, r6, pc}
+.L2639:
.align 2
-.L2702:
+.L2638:
.word .LANCHOR2
.fnend
.size flush_l2p_region, .-flush_l2p_region
.align 2
.global FtlMapTblRecovery
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlMapTblRecovery, %function
FtlMapTblRecovery:
.fnstart
@ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #28
sub sp, sp, #28
- ldr r3, [r0, #16]
+ ldr r3, [r0, #24]
mov r4, r0
- ldrh r10, [r0, #6]
mov r1, #0
- ldr r8, [r0, #24]
+ mov r7, #0
+ ldr r5, .L2682
+ str r3, [sp]
+ ldr r3, [r0, #16]
+ ldr r8, [r0, #12]
+ ldr fp, .L2682+4
str r3, [sp, #12]
+ ldrh r3, [r0, #6]
+ str r3, [sp, #4]
ldrh r3, [r0, #8]
- mov r2, r10, asl #2
- ldr r9, [r0, #12]
- mov r0, r8
+ ldr r0, [sp]
str r3, [sp, #8]
+ ldr r3, [sp, #4]
+ lsl r2, r3, #2
bl ftl_memset
- ldr r1, .L2747
- mov r2, #1
- str r2, [r4, #36]
- ldr r3, [r1, #-524]
- mov r5, r1
- ldr r6, [r1, #-500]
- mov r7, r1
- str r3, [r1, #1760]
+ ldr r3, [r5, #-524]
+ ldr r6, [r5, #-500]
+ str r7, [r4, #32]
+ str r3, [r5, #1768]
mvn r3, #0
- str r6, [r1, #1764]
+ str r6, [r5, #1772]
strh r3, [r4] @ movhi
strh r3, [r4, #2] @ movhi
- mov r3, #0
- str r3, [r4, #32]
- str r3, [r4, #28]
- str r3, [sp, #4]
-.L2705:
- ldrh r3, [sp, #4]
- ldr r2, [sp, #8]
- sxth fp, r3
- cmp fp, r2
- bge .L2723
- ldr r2, [sp, #8]
- sub r2, r2, #1
- cmp fp, r2
- mov r2, fp, asl #1
- bne .L2706
- ldrh r0, [r9, r2]
+ mov r3, #1
+ str r7, [r4, #28]
+ str r3, [r4, #36]
+.L2641:
+ ldr r3, [sp, #8]
+ sxth r10, r7
+ cmp r10, r3
+ bge .L2660
+ ldr r3, [sp, #8]
+ sub r3, r3, #1
+ cmp r10, r3
+ lsl r3, r10, #1
+ bne .L2642
+ ldrh r0, [r8, r3]
mov r1, #1
- str r3, [sp, #8]
- add r3, r9, r2
- str r3, [sp, #4]
+ add r9, r8, r3
+ mov r8, #0
bl FtlGetLastWrittenPage
- mov r7, #0
- ldr r3, [sp, #8]
- add r2, r0, #1
- strh r2, [r4, #2] @ movhi
- sxth r0, r0
- add r9, r0, #1
- strh r3, [r4] @ movhi
- ldr r3, [sp, #12]
- ldr r3, [r3, fp, asl #2]
- ldr fp, .L2747
- str r3, [r4, #28]
-.L2707:
- sxth r3, r7
- cmp r3, r9
- bge .L2723
- ldr r2, [sp, #4]
- mov r1, #1
- ldr r0, .L2747+4
- ldrh r2, [r2]
- orr r3, r3, r2, asl #10
- mov r2, r1
- str r3, [r5, #1756]
- bl FlashReadPages
- ldr r3, .L2747+8
- ldrb r3, [r3] @ zero_extendqisi2
- cmp r3, #0
- beq .L2708
- ldr r3, [fp, #1764]
- ldr r3, [r3, #12]
- cmp r3, #0
- beq .L2708
- ldr r2, .L2747+12
- ldr r0, [fp, #1760]
+ sxth r3, r0
+ strh r7, [r4] @ movhi
+ add r0, r0, #1
+ ldr r7, .L2682+8
str r3, [sp, #8]
- ldrh r1, [r2]
- bl js_hash
+ ldr r3, [sp, #12]
+ strh r0, [r4, #2] @ movhi
+ add fp, r7, #2400
+ ldr r3, [r3, r10, lsl #2]
+ ldr r10, .L2682+12
+ str r3, [r4, #28]
+.L2643:
ldr r3, [sp, #8]
- cmp r3, r0
- mvnne r3, #0
- strne r3, [fp, #1752]
-.L2708:
- ldr r3, [fp, #1752]
- cmn r3, #1
- beq .L2709
- ldrh r3, [r6, #8]
- cmp r3, r10
- bcs .L2709
- ldrh r2, [r4, #4]
- ldrh r1, [r6]
- cmp r1, r2
- ldreq r2, [fp, #1756]
- streq r2, [r8, r3, asl #2]
-.L2709:
- add r7, r7, #1
- b .L2707
-.L2723:
+ sxth r2, r8
+ add r1, r3, #1
+ cmp r2, r1
+ blt .L2646
+.L2660:
mov r0, r4
bl ftl_free_no_use_map_blk
- ldr r1, .L2747+8
- movw r3, #2390
+ ldr r1, .L2682+8
+ movw r3, #2392
ldrh r2, [r4, #2]
ldrh r3, [r1, r3]
cmp r2, r3
- bne .L2712
+ bne .L2648
mov r0, r4
bl ftl_map_blk_alloc_new_blk
- b .L2712
-.L2706:
- ldr r3, [r5, #-524]
- mov r1, #1
- ldr fp, .L2747+16
- ldr r0, .L2747+4
- str r3, [r5, #1760]
- add r3, r9, r2
- ldrh r2, [r9, r2]
- str r3, [sp, #16]
- ldrh r3, [fp]
- sub r3, r3, #1
- orr r3, r3, r2, asl #10
- mov r2, r1
- str r3, [r5, #1756]
- bl FlashReadPages
- ldr r3, [r5, #1752]
- cmn r3, #1
- mov r3, fp
- beq .L2725
- ldrh r1, [r6]
- ldrh r2, [r4, #4]
- cmp r1, r2
- bne .L2725
- ldrh r1, [r6, #8]
- movw r2, #64245
- cmp r1, r2
- bne .L2725
- mov r0, #0
- mov lr, #8
- mov fp, #4
-.L2714:
- uxth r2, r0
- ldrh ip, [r3]
- sxth r1, r2
- sub ip, ip, #1
- cmp r1, ip
- bge .L2717
- ldr ip, [r5, #-524]
- add r0, r0, #1
- ldr r1, [ip, r1, asl #3]
- uxth r1, r1
- cmp r1, r10
- smlabbcc r2, r2, lr, fp
- ldrcc r2, [ip, r2]
- strcc r2, [r8, r1, asl #2]
- b .L2714
-.L2725:
- mov fp, #0
-.L2745:
- ldr r3, .L2747+16
- sxth r2, fp
- ldrh r1, [r3]
- cmp r2, r1
- bge .L2717
- str r3, [sp, #20]
- ldr r3, [sp, #16]
- ldr r0, .L2747+4
- ldrh r1, [r3]
- orr r2, r2, r1, asl #10
- mov r1, #1
- str r2, [r7, #1756]
- mov r2, r1
- bl FlashReadPages
- ldr r3, .L2747+8
- ldrb r2, [r3] @ zero_extendqisi2
- cmp r2, #0
- ldr r3, [sp, #20]
- beq .L2718
- ldr r2, [r7, #1764]
- ldr r2, [r2, #12]
- cmp r2, #0
- beq .L2718
- ldrh r1, [r3, #8]
- ldr r0, [r7, #1760]
- str r2, [sp, #20]
- bl js_hash
- ldr r2, [sp, #20]
- cmp r2, r0
- mvnne r3, #0
- strne r3, [r7, #1752]
-.L2718:
- ldr r3, .L2747
- ldr r3, [r3, #1752]
- cmn r3, #1
- beq .L2719
- ldrh r3, [r6, #8]
- cmp r3, r10
- bcs .L2719
- ldrh r2, [r4, #4]
- ldrh r1, [r6]
- cmp r1, r2
- ldreq r2, [r7, #1756]
- streq r2, [r8, r3, asl #2]
-.L2719:
- add fp, fp, #1
- b .L2745
-.L2717:
- ldr r3, [sp, #4]
- add r3, r3, #1
- str r3, [sp, #4]
- b .L2705
-.L2712:
+.L2648:
mov r0, r4
bl ftl_map_blk_gc
mov r0, r4
@@ -16276,54 +16611,199 @@
mov r0, #0
add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2748:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2646:
+ ldrh r1, [r9]
+ mov r0, r10
+ orr r2, r2, r1, lsl #10
+ str r2, [r5, #1764]
+ mov r2, #1
+ mov r1, r2
+ bl FlashReadPages
+ ldrb r2, [r7, #36] @ zero_extendqisi2
+ cmp r2, #0
+ beq .L2644
+ ldr r2, [r5, #1772]
+ ldr r2, [r2, #12]
+ cmp r2, #0
+ str r2, [sp, #12]
+ beq .L2644
+ ldrh r1, [fp]
+ ldr r0, [r5, #1768]
+ bl js_hash
+ ldr r2, [sp, #12]
+ cmp r2, r0
+ mvnne r2, #0
+ strne r2, [r5, #1760]
+.L2644:
+ ldr r1, .L2682
+ ldr r2, [r1, #1760]
+ cmn r2, #1
+ beq .L2645
+ ldrh r2, [r6, #8]
+ ldr r3, [sp, #4]
+ cmp r3, r2
+ bls .L2645
+ ldrh ip, [r6]
+ ldrh r0, [r4, #4]
+ cmp ip, r0
+ ldreq r1, [r1, #1764]
+ ldreq r3, [sp]
+ streq r1, [r3, r2, lsl #2]
+.L2645:
+ add r8, r8, #1
+ b .L2643
+.L2642:
+ ldr r2, [r5, #-524]
+ ldr r0, .L2682+12
+ str r2, [r5, #1768]
+ add r2, r8, r3
+ str r2, [sp, #16]
+ ldrh r2, [r8, r3]
+ ldrh r3, [fp]
+ sub r3, r3, #1
+ orr r3, r3, r2, lsl #10
+ mov r2, #1
+ mov r1, r2
+ str r3, [r5, #1764]
+ bl FlashReadPages
+ ldr r3, [r5, #1760]
+ cmn r3, #1
+ beq .L2662
+ ldrh r2, [r6]
+ ldrh r3, [r4, #4]
+ cmp r2, r3
+ bne .L2662
+ ldrh r2, [r6, #8]
+ movw r3, #64245
+ cmp r2, r3
+ beq .L2650
+.L2662:
+ ldr r9, .L2682
+ mov r10, #0
+.L2651:
+ ldrh r2, [fp]
+ sxth r3, r10
+ cmp r3, r2
+ bge .L2658
+ ldr r2, [sp, #16]
+ ldr r0, .L2682+12
+ ldrh r2, [r2]
+ orr r3, r3, r2, lsl #10
+ mov r2, #1
+ mov r1, r2
+ str r3, [r9, #1764]
+ bl FlashReadPages
+ ldr r3, .L2682+8
+ ldrb r3, [r3, #36] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L2655
+ ldr r3, [r9, #1772]
+ ldr r3, [r3, #12]
+ cmp r3, #0
+ str r3, [sp, #20]
+ beq .L2655
+ ldr r2, .L2682+16
+ ldr r0, [r9, #1768]
+ ldrh r1, [r2]
+ bl js_hash
+ ldr r3, [sp, #20]
+ cmp r3, r0
+ mvnne r3, #0
+ strne r3, [r9, #1760]
+.L2655:
+ ldr r3, [r9, #1760]
+ cmn r3, #1
+ beq .L2656
+ ldrh r3, [r6, #8]
+ ldr r2, [sp, #4]
+ cmp r2, r3
+ bls .L2656
+ ldrh r1, [r6]
+ ldrh r2, [r4, #4]
+ cmp r1, r2
+ ldreq r2, [r9, #1764]
+ ldreq r1, [sp]
+ streq r2, [r1, r3, lsl #2]
+.L2656:
+ add r10, r10, #1
+ b .L2651
+.L2650:
+ mov r1, #0
+ mov ip, #4
+.L2652:
+ ldrh r2, [fp]
+ sxth r3, r1
+ sub r2, r2, #1
+ cmp r3, r2
+ blt .L2654
+.L2658:
+ add r7, r7, #1
+ b .L2641
+.L2654:
+ ldr r0, [r5, #-524]
+ add r1, r1, #1
+ ldr r9, [sp, #4]
+ ldr r2, [r0, r3, lsl #3]
+ uxth lr, r2
+ cmp r9, lr
+ addhi r3, ip, r3, lsl #3
+ movhi r2, lr
+ ldrhi r3, [r0, r3]
+ ldrhi r0, [sp]
+ strhi r3, [r0, r2, lsl #2]
+ b .L2652
+.L2683:
.align 2
-.L2747:
+.L2682:
.word .LANCHOR2
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2392
.word .LANCHOR0
- .word .LANCHOR0+2398
- .word .LANCHOR0+2390
+ .word .LANCHOR2+1760
+ .word .LANCHOR0+2400
.fnend
.size FtlMapTblRecovery, .-FtlMapTblRecovery
.align 2
.global FtlLoadVonderInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadVonderInfo, %function
FtlLoadVonderInfo:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L2751
- movw r1, #2408
- stmfd sp!, {r3, lr}
- .save {r3, lr}
- ldr r3, .L2751+4
+ ldr r2, .L2686
+ movw r1, #2412
+ ldr r3, .L2686+4
+ push {r4, lr}
+ .save {r4, lr}
ldrh r1, [r2, r1]
add r0, r3, #1792
+ add r0, r0, #8
strh r1, [r0, #10] @ movhi
- ldr r1, .L2751+8
+ ldr r1, .L2686+8
strh r1, [r0, #4] @ movhi
- movw r1, #2434
+ movw r1, #2438
ldrh r1, [r2, r1]
strh r1, [r0, #8] @ movhi
- movw r1, #2410
+ movw r1, #2414
ldrh r1, [r2, r1]
- ldr r2, [r2, #2436]
+ ldr r2, [r2, #2440]
strh r1, [r0, #6] @ movhi
- str r2, [r3, #1804]
- ldr r2, [r3, #-460]
- str r2, [r3, #1808]
- ldr r2, [r3, #-464]
str r2, [r3, #1812]
- ldr r2, [r3, #-456]
+ ldr r2, [r3, #-460]
str r2, [r3, #1816]
+ ldr r2, [r3, #-464]
+ str r2, [r3, #1820]
+ ldr r2, [r3, #-456]
+ str r2, [r3, #1824]
bl FtlMapTblRecovery
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L2752:
+ pop {r4, pc}
+.L2687:
.align 2
-.L2751:
+.L2686:
.word .LANCHOR0
.word .LANCHOR2
.word -3962
@@ -16331,237 +16811,241 @@
.size FtlLoadVonderInfo, .-FtlLoadVonderInfo
.align 2
.global FtlLoadMapInfo
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadMapInfo, %function
FtlLoadMapInfo:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
bl FtlL2PDataInit
- ldr r0, .L2755
+ ldr r0, .L2690
bl FtlMapTblRecovery
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L2756:
+ pop {r4, pc}
+.L2691:
.align 2
-.L2755:
+.L2690:
.word .LANCHOR2-432
.fnend
.size FtlLoadMapInfo, .-FtlLoadMapInfo
.align 2
.global FtlVendorPartWrite
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlVendorPartWrite, %function
FtlVendorPartWrite:
.fnstart
@ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L2768
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L2702
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
mov r10, r2
- movw r2, #2396
- mov r6, r0
- ldrh r5, [r3, r2]
- add r3, r3, #2384
- add r2, r0, r1
+ movw r2, #2386
+ mov r5, r1
+ add r1, r0, r1
.pad #60
sub sp, sp, #60
- ldrh r3, [r3]
- mov r4, r1
- cmp r2, r3
- mvnhi r0, #0
- bhi .L2758
- ldr fp, .L2768+4
- mov r5, r6, lsr r5
- mov r3, r5, asl #2
- str r3, [sp, #4]
- mov r7, fp
- mov r3, #0
- str r3, [sp]
-.L2759:
- cmp r4, #0
- beq .L2767
- ldr r2, [sp, #4]
- mov r0, r6
- ldr r3, [fp, #-456]
- ldr ip, [r3, r2]
- ldr r3, .L2768+8
- str ip, [sp, #12]
- ldrh r2, [r3]
- mov r1, r2
- str r2, [sp, #8]
- bl __aeabi_uidivmod
- ldr r2, [sp, #8]
- mov r8, r1
- ldr ip, [sp, #12]
- rsb r3, r1, r2
- uxth r9, r3
- cmp r9, r4
- uxthhi r9, r4
- cmp r9, r2
- cmpne ip, #0
- movne r1, #1
- moveq r1, #0
- beq .L2761
- ldr r2, [r7, #-516]
- mov r1, #1
- add r0, sp, #20
- str ip, [sp, #24]
- str r2, [sp, #28]
- mov r2, #0
- str r2, [sp, #32]
- mov r2, r1
- bl FlashReadPages
- b .L2762
-.L2761:
- ldr r2, .L2768+12
- ldr r0, [r7, #-516]
- ldrh r2, [r2]
- bl ftl_memset
-.L2762:
- mov ip, r9, asl #9
- ldr r0, [r7, #-516]
- uxth r8, r8
- mov r1, r10
- mov r2, ip
- str ip, [sp, #8]
- add r0, r0, r8, asl #9
- rsb r4, r9, r4
- bl ftl_memcpy
- mov r1, r5
- ldr r0, .L2768+16
- add r5, r5, #1
- ldr r2, [r7, #-516]
- add r6, r6, r9
- bl FtlMapWritePage
- ldr r3, [sp]
- cmn r0, #1
- ldr ip, [sp, #8]
- mvneq r3, #0
- str r3, [sp]
- add r10, r10, ip
- ldr r3, [sp, #4]
- add r3, r3, #4
- str r3, [sp, #4]
- b .L2759
-.L2767:
- ldr r0, [sp]
-.L2758:
+ ldrh r2, [r3, r2]
+ cmp r1, r2
+ mvnhi r9, #0
+ bhi .L2692
+ movw r2, #2398
+ ldr r8, .L2702+4
+ ldrh r6, [r3, r2]
+ mov r7, r0
+ mov r9, #0
+ lsr r6, r0, r6
+ lsl fp, r6, #2
+.L2694:
+ cmp r5, #0
+ bne .L2699
+.L2692:
+ mov r0, r9
add sp, sp, #60
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2769:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2699:
+ ldr r3, [r8, #-456]
+ mov r0, r7
+ ldr r2, [r3, fp]
+ ldr r3, .L2702+8
+ str r2, [sp, #12]
+ ldrh r3, [r3]
+ mov r1, r3
+ str r3, [sp, #8]
+ bl __aeabi_uidivmod
+ ldr r3, [sp, #8]
+ ldr r2, [sp, #12]
+ str r1, [sp, #4]
+ sub r4, r3, r1
+ uxth r4, r4
+ cmp r5, r4
+ uxthcc r4, r5
+ cmp r2, #0
+ cmpne r4, r3
+ movne r1, #1
+ moveq r1, #0
+ beq .L2696
+ ldr r3, [r8, #-516]
+ add r0, sp, #20
+ str r2, [sp, #24]
+ mov r2, #1
+ mov r1, r2
+ str r3, [sp, #28]
+ mov r3, #0
+ str r3, [sp, #32]
+ bl FlashReadPages
+.L2697:
+ lsl r3, r4, #9
+ ldr r0, [r8, #-516]
+ mov r1, r10
+ mov r2, r3
+ str r3, [sp, #8]
+ ldr r3, [sp, #4]
+ sub r5, r5, r4
+ add r7, r7, r4
+ add fp, fp, #4
+ add r0, r0, r3, lsl #9
+ bl ftl_memcpy
+ mov r1, r6
+ ldr r2, [r8, #-516]
+ ldr r0, .L2702+12
+ add r6, r6, #1
+ bl FtlMapWritePage
+ ldr r3, [sp, #8]
+ cmn r0, #1
+ mvneq r9, #0
+ add r10, r10, r3
+ b .L2694
+.L2696:
+ ldr r3, .L2702+16
+ ldr r0, [r8, #-516]
+ ldrh r2, [r3]
+ bl ftl_memset
+ b .L2697
+.L2703:
.align 2
-.L2768:
+.L2702:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2394
- .word .LANCHOR0+2398
- .word .LANCHOR2+1792
+ .word .LANCHOR0+2396
+ .word .LANCHOR2+1800
+ .word .LANCHOR0+2400
.fnend
.size FtlVendorPartWrite, .-FtlVendorPartWrite
.align 2
.global Ftl_save_ext_data
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_save_ext_data, %function
Ftl_save_ext_data:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r2, .L2772
- ldr r3, .L2772+4
- ldr r1, [r2, #-3232]
- cmp r1, r3
+ ldr r3, .L2706
+ ldr r2, .L2706+4
+ ldr r1, [r3, #-3236]
+ cmp r1, r2
bxne lr
- ldr r3, .L2772+8
- mov r0, #0
+ ldr r2, .L2706+8
mov r1, #1
- sub r2, r2, #3232
- str r3, [r2, #4]
- ldr r3, [r2, #-108]
- str r3, [r2, #88]
- ldr r3, [r2, #-104]
- str r3, [r2, #92]
- ldr r3, [r2, #-112]
- str r3, [r2, #8]
- ldr r3, [r2, #-124]
- str r3, [r2, #12]
- ldr r3, [r2, #-132]
- str r3, [r2, #16]
- ldr r3, [r2, #-116]
- str r3, [r2, #20]
- ldr r3, [r2, #-88]
- str r3, [r2, #28]
- ldr r3, [r2, #-372]
- str r3, [r2, #32]
- ldr r3, [r2, #-128]
- str r3, [r2, #36]
- ldr r3, [r2, #-120]
- str r3, [r2, #40]
- ldr r3, [r2, #-80]
- str r3, [r2, #44]
- ldr r3, [r2, #-76]
- str r3, [r2, #48]
- ldr r3, [r2, #-4]
- str r3, [r2, #60]
- ldr r3, [r2, #2668]
- str r3, [r2, #64]
+ mov r0, #0
+ str r2, [r3, #-3232]
+ ldr r2, [r3, #-3340]
+ str r2, [r3, #-3148]
+ ldr r2, [r3, #-3336]
+ str r2, [r3, #-3144]
+ ldr r2, [r3, #-3344]
+ str r2, [r3, #-3228]
+ ldr r2, [r3, #-3356]
+ str r2, [r3, #-3224]
+ ldr r2, [r3, #-3364]
+ str r2, [r3, #-3220]
+ ldr r2, [r3, #-3348]
+ str r2, [r3, #-3216]
+ ldr r2, [r3, #-3320]
+ str r2, [r3, #-3208]
+ ldr r2, [r3, #-3600]
+ str r2, [r3, #-3204]
+ ldr r2, [r3, #-3360]
+ str r2, [r3, #-3200]
+ ldr r2, [r3, #-3352]
+ str r2, [r3, #-3196]
+ ldr r2, [r3, #-3312]
+ str r2, [r3, #-3192]
+ ldr r2, [r3, #-3308]
+ str r2, [r3, #-3188]
+ ldr r2, [r3, #-2724]
+ str r2, [r3, #-3176]
+ ldr r2, [r3, #-564]
+ str r2, [r3, #-3172]
+ ldr r2, .L2706+12
b FtlVendorPartWrite
-.L2773:
+.L2707:
.align 2
-.L2772:
+.L2706:
.word .LANCHOR2
.word 1179929683
.word 1342177379
+ .word .LANCHOR2-3236
.fnend
.size Ftl_save_ext_data, .-Ftl_save_ext_data
.align 2
.global FtlEctTblFlush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlEctTblFlush, %function
FtlEctTblFlush:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
- ldr r3, .L2782
- ldr r3, [r3, #2244]
+ ldr r3, .L2718
+ ldr r3, [r3, #2248]
cmp r3, #0
- ldr r3, .L2782+4
+ ldr r3, .L2718+4
moveq r2, #32
- beq .L2775
+ beq .L2709
ldr r2, [r3, #-3308]
cmp r2, #39
movhi r2, #32
movls r2, #4
-.L2775:
- movw ip, #1836
+.L2709:
+ movw ip, #1844
ldrh r1, [r3, ip]
cmp r1, #31
addls r1, r1, #1
- ldrls r2, .L2782+4
- strlsh r1, [r2, ip] @ movhi
movls r2, #1
+ strhls r1, [r3, ip] @ movhi
cmp r0, #0
- bne .L2777
+ bne .L2711
ldr r1, [r3, #-480]
ldr r0, [r1, #20]
ldr r1, [r1, #16]
add r2, r2, r0
cmp r1, r2
- bcc .L2778
-.L2777:
- ldr r2, [r3, #-480]
+ bcc .L2716
+.L2711:
+ push {r4, lr}
+ .save {r4, lr}
mov r0, #64
+ ldr r2, [r3, #-480]
ldr r1, [r2, #16]
str r1, [r2, #20]
- ldr r1, .L2782+8
+ ldr r1, .L2718+8
str r1, [r2]
ldr r2, [r3, #-480]
- ldr r3, .L2782+12
+ ldr r3, .L2718+12
ldrh r1, [r3]
- mov r3, r1, asl #9
+ lsl r3, r1, #9
str r3, [r2, #12]
ldr r3, [r2, #8]
add r3, r3, #1
@@ -16570,12 +17054,14 @@
str r3, [r2, #4]
bl FtlVendorPartWrite
bl Ftl_save_ext_data
-.L2778:
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L2783:
+ pop {r4, pc}
+.L2716:
+ mov r0, #0
+ bx lr
+.L2719:
.align 2
-.L2782:
+.L2718:
.word .LANCHOR0
.word .LANCHOR2
.word 1112818501
@@ -16584,404 +17070,411 @@
.size FtlEctTblFlush, .-FtlEctTblFlush
.align 2
.global FtlVendorPartRead
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlVendorPartRead, %function
FtlVendorPartRead:
.fnstart
@ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L2731
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2396
- ldr r4, .L2796
- mov r8, r2
- add r2, r0, r1
- mov r7, r0
+ mov r10, r2
+ movw r2, #2386
+ mov r6, r1
+ add r1, r0, r1
.pad #60
sub sp, sp, #60
- mov r6, r1
- ldrh r5, [r4, r3]
- add r4, r4, #2384
- ldrh r3, [r4]
- cmp r2, r3
- mvnhi r0, #0
- bhi .L2785
- ldr r9, .L2796+4
- mov r5, r7, lsr r5
- mov r3, r5, asl #2
- str r3, [sp, #4]
- mov r10, r9
- mov r3, #0
- str r3, [sp]
-.L2786:
+ ldrh r2, [r3, r2]
+ cmp r1, r2
+ mvnhi r9, #0
+ bhi .L2720
+ movw r2, #2398
+ ldr r8, .L2731+4
+ ldrh r5, [r3, r2]
+ mov r7, r0
+ mov r9, #0
+ lsr r5, r0, r5
+ lsl fp, r5, #2
+.L2722:
cmp r6, #0
- beq .L2795
- ldr r2, [sp, #4]
+ bne .L2728
+.L2720:
+ mov r0, r9
+ add sp, sp, #60
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2728:
+ ldr r3, [r8, #-456]
mov r0, r7
- ldr r3, [r9, #-456]
- ldr r3, [r3, r2]
- str r3, [sp, #12]
- ldr r3, .L2796+8
+ ldr r3, [r3, fp]
+ str r3, [sp, #8]
+ ldr r3, .L2731+8
ldrh r4, [r3]
mov r1, r4
bl __aeabi_uidivmod
- rsb r4, r1, r4
- ldr r3, [sp, #12]
- str r1, [sp, #8]
+ sub r4, r4, r1
+ ldr r3, [sp, #8]
uxth r4, r4
- cmp r4, r6
- uxthhi r4, r6
+ str r1, [sp, #4]
+ cmp r6, r4
+ uxthcc r4, r6
cmp r3, #0
- mov fp, r4, asl #9
- beq .L2788
- ldr r2, [r10, #-516]
- mov r1, #1
+ lsl r2, r4, #9
+ str r2, [sp, #8]
+ beq .L2724
+ ldr r2, [r8, #-516]
add r0, sp, #20
str r3, [sp, #24]
str r3, [sp, #12]
str r2, [sp, #28]
mov r2, #0
str r2, [sp, #32]
- mov r2, r1
+ mov r2, #1
+ mov r1, r2
bl FlashReadPages
ldr r2, [sp, #20]
- ldr r3, [sp]
- cmn r2, #1
- ldr r2, [r10, #1752]
- mvneq r3, #0
- cmp r2, #256
- str r3, [sp]
ldr r3, [sp, #12]
- bne .L2790
- mov r1, r5
+ cmn r2, #1
+ ldr r2, [r8, #1760]
+ mvneq r9, #0
+ cmp r2, #256
+ bne .L2726
mov r2, r3
- ldr r0, .L2796+12
- bl printk
- ldr r0, .L2796+16
mov r1, r5
- ldr r2, [r9, #-516]
+ ldr r0, .L2731+12
+ bl printk
+ ldr r2, [r8, #-516]
+ mov r1, r5
+ ldr r0, .L2731+16
bl FtlMapWritePage
-.L2790:
- ldrh r3, [sp, #8]
- mov r0, r8
- ldr r1, [r10, #-516]
- mov r2, fp
- add r1, r1, r3, asl #9
- bl ftl_memcpy
- b .L2791
-.L2788:
- mov r0, r8
- mov r1, r3
- mov r2, fp
- bl ftl_memset
-.L2791:
+.L2726:
+ ldr r1, [r8, #-516]
+ lsl r2, r4, #9
ldr r3, [sp, #4]
+ mov r0, r10
+ add r1, r1, r3, lsl #9
+ bl ftl_memcpy
+.L2727:
+ ldr r3, [sp, #8]
add r5, r5, #1
- rsb r6, r4, r6
+ sub r6, r6, r4
add r7, r7, r4
- add r3, r3, #4
- add r8, r8, fp
- str r3, [sp, #4]
- b .L2786
-.L2795:
- ldr r0, [sp]
-.L2785:
- add sp, sp, #60
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2797:
+ add fp, fp, #4
+ add r10, r10, r3
+ b .L2722
+.L2724:
+ lsl r2, r4, #9
+ mov r1, r3
+ mov r0, r10
+ bl ftl_memset
+ b .L2727
+.L2732:
.align 2
-.L2796:
+.L2731:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2394
+ .word .LANCHOR0+2396
.word .LC136
- .word .LANCHOR2+1792
+ .word .LANCHOR2+1800
.fnend
.size FtlVendorPartRead, .-FtlVendorPartRead
.align 2
.global FtlLoadEctTbl
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLoadEctTbl, %function
FtlLoadEctTbl:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r0, #64
- ldr r4, .L2801
+ ldr r4, .L2736
sub r5, r4, #488
ldr r2, [r4, #-480]
ldrh r1, [r5]
bl FtlVendorPartRead
ldr r3, [r4, #-480]
ldr r2, [r3]
- ldr r3, .L2801+4
+ ldr r3, .L2736+4
cmp r2, r3
- beq .L2799
- ldr r1, .L2801+8
- ldr r0, .L2801+12
+ beq .L2734
+ ldr r1, .L2736+8
+ ldr r0, .L2736+12
bl printk
ldrh r2, [r5]
- ldr r0, [r4, #-480]
mov r1, #0
- mov r2, r2, asl #9
+ ldr r0, [r4, #-480]
+ lsl r2, r2, #9
bl ftl_memset
-.L2799:
+.L2734:
mov r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L2802:
+ pop {r4, r5, r6, pc}
+.L2737:
.align 2
-.L2801:
+.L2736:
.word .LANCHOR2
.word 1112818501
.word .LC137
- .word .LC76
+ .word .LC77
.fnend
.size FtlLoadEctTbl, .-FtlLoadEctTbl
.align 2
.global Ftl_load_ext_data
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_load_ext_data, %function
Ftl_load_ext_data:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r0, #0
- ldr r4, .L2809
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r1, #1
- ldr r5, .L2809+4
- sub r2, r4, #3232
+ ldr r4, .L2744
+ mov r0, #0
+ ldr r5, .L2744+4
+ sub r6, r4, #3232
+ sub r6, r6, #4
+ mov r2, r6
bl FtlVendorPartRead
- ldr r3, [r4, #-3232]
+ ldr r3, [r4, #-3236]
cmp r3, r5
- beq .L2804
- sub r0, r4, #3232
- mov r1, #0
+ beq .L2739
mov r2, #512
+ mov r1, #0
+ mov r0, r6
bl ftl_memset
- str r5, [r4, #-3232]
-.L2804:
- ldr r2, [r4, #-3232]
- ldr r3, .L2809
- cmp r2, r5
- bne .L2805
- ldr r2, [r3, #-3144]
- str r2, [r3, #-3340]
- ldr r2, [r3, #-3140]
- str r2, [r3, #-3336]
- ldr r2, [r3, #-3224]
- str r2, [r3, #-3344]
- ldr r2, [r3, #-3220]
- str r2, [r3, #-3356]
- ldr r2, [r3, #-3216]
- str r2, [r3, #-3364]
- ldr r2, [r3, #-3212]
- str r2, [r3, #-3348]
- ldr r2, [r3, #-3204]
- str r2, [r3, #-3320]
- ldr r2, [r3, #-3200]
- str r2, [r3, #-3604]
- ldr r2, [r3, #-3196]
- str r2, [r3, #-3360]
- ldr r2, [r3, #-3192]
- str r2, [r3, #-3352]
- ldr r2, [r3, #-3188]
- str r2, [r3, #-3312]
- ldr r2, [r3, #-3184]
- str r2, [r3, #-3308]
- ldr r2, [r3, #-3172]
- str r2, [r3, #-3236]
-.L2805:
- ldr r1, [r4, #-3164]
+ str r5, [r4, #-3236]
+.L2739:
+ ldr r3, [r4, #-3236]
+ cmp r3, r5
+ bne .L2740
+ ldr r3, [r4, #-3148]
+ str r3, [r4, #-3340]
+ ldr r3, [r4, #-3144]
+ str r3, [r4, #-3336]
+ ldr r3, [r4, #-3228]
+ str r3, [r4, #-3344]
+ ldr r3, [r4, #-3224]
+ str r3, [r4, #-3356]
+ ldr r3, [r4, #-3220]
+ str r3, [r4, #-3364]
+ ldr r3, [r4, #-3216]
+ str r3, [r4, #-3348]
+ ldr r3, [r4, #-3208]
+ str r3, [r4, #-3320]
+ ldr r3, [r4, #-3204]
+ str r3, [r4, #-3600]
+ ldr r3, [r4, #-3200]
+ str r3, [r4, #-3360]
+ ldr r3, [r4, #-3196]
+ str r3, [r4, #-3352]
+ ldr r3, [r4, #-3192]
+ str r3, [r4, #-3312]
+ ldr r3, [r4, #-3188]
+ str r3, [r4, #-3308]
+ ldr r3, [r4, #-3176]
+ str r3, [r4, #-2724]
+.L2740:
+ ldr r1, [r4, #-3168]
mov r3, #0
- ldr r2, .L2809+8
+ ldr r2, .L2744+8
str r3, [r4, #-564]
+ ldr r5, .L2744+12
cmp r1, r2
- ldr r5, .L2809+12
- bne .L2806
- ldrb r2, [r5, #144] @ zero_extendqisi2
+ bne .L2741
+ ldrb r2, [r5, #152] @ zero_extendqisi2
cmp r2, r3
- beq .L2807
- ldr r2, .L2809
- str r3, [r2, #-3164]
+ beq .L2742
+ str r3, [r4, #-3168]
bl Ftl_save_ext_data
- b .L2806
-.L2807:
- ldr r0, .L2809+16
- mov r3, #1
- ldr r1, .L2809+20
- str r3, [r5, #2244]
- bl printk
-.L2806:
- movw r3, #2380
+.L2741:
+ movw r3, #2382
ldr r0, [r4, #-3324]
ldrh r2, [r5, r3]
+ movw r1, #2332
ldr r3, [r4, #-3320]
+ ldrh r1, [r5, r1]
mla r0, r0, r2, r3
- movw r3, #2328
- ldrh r1, [r5, r3]
bl __aeabi_uidiv
str r0, [r4, #-3316]
- ldmfd sp!, {r3, r4, r5, pc}
-.L2810:
+ pop {r4, r5, r6, pc}
+.L2742:
+ mov r3, #1
+ ldr r1, .L2744+16
+ ldr r0, .L2744+20
+ str r3, [r5, #2248]
+ bl printk
+ b .L2741
+.L2745:
.align 2
-.L2809:
+.L2744:
.word .LANCHOR2
.word 1179929683
.word 305432421
.word .LANCHOR0
- .word .LC76
.word .LC138
+ .word .LC77
.fnend
.size Ftl_load_ext_data, .-Ftl_load_ext_data
.align 2
.global FtlMapBlkWriteDumpData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlMapBlkWriteDumpData, %function
FtlMapBlkWriteDumpData:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ ldr r3, [r0, #36]
+ cmp r3, #0
+ bxeq lr
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- ldr r2, [r0, #36]
- ldrh r5, [r0, #6]
- cmp r2, #0
- ldr r3, [r0, #24]
- ldmeqfd sp!, {r4, r5, r6, pc}
- ldr r4, .L2818
mov r2, #0
+ ldr r4, .L2756
str r2, [r0, #36]
- ldr r2, [r4, #-3616]
+ ldr r2, [r4, #-3612]
+ ldrh r5, [r0, #6]
+ ldr r3, [r0, #24]
cmp r2, #0
- ldmnefd sp!, {r4, r5, r6, pc}
- sub r5, r5, #1
+ popne {r4, r5, r6, pc}
mov r6, r0
ldr r2, [r4, #-500]
ldr r0, [r4, #-520]
+ sub r5, r5, #1
uxth r5, r5
- str r2, [r4, #1764]
- str r0, [r4, #1760]
- ldr r3, [r3, r5, asl #2]
+ str r2, [r4, #1772]
+ str r0, [r4, #1768]
+ ldr r3, [r3, r5, lsl #2]
cmp r3, #0
- str r3, [r4, #1756]
- beq .L2815
- mov r1, #1
- ldr r0, .L2818+4
- mov r2, r1
+ str r3, [r4, #1764]
+ beq .L2750
+ mov r2, #1
+ add r0, r4, #1760
+ mov r1, r2
bl FlashReadPages
- b .L2816
-.L2815:
- ldr r2, .L2818+8
- movw r3, #2398
- mov r1, #255
- ldrh r2, [r2, r3]
- bl ftl_memset
-.L2816:
- mov r0, r6
+.L2751:
+ ldr r2, [r4, #1768]
mov r1, r5
- ldr r2, [r4, #1760]
- ldmfd sp!, {r4, r5, r6, lr}
+ mov r0, r6
+ pop {r4, r5, r6, lr}
b FtlMapWritePage
-.L2819:
+.L2750:
+ ldr r3, .L2756+4
+ mov r1, #255
+ ldrh r2, [r3]
+ bl ftl_memset
+ b .L2751
+.L2757:
.align 2
-.L2818:
+.L2756:
.word .LANCHOR2
- .word .LANCHOR2+1752
- .word .LANCHOR0
+ .word .LANCHOR0+2400
.fnend
.size FtlMapBlkWriteDumpData, .-FtlMapBlkWriteDumpData
.align 2
.global FlashReadFacBbtData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashReadFacBbtData, %function
FlashReadFacBbtData:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L2835
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r8, r2
- ldrh r2, [r3, #128]
+ ldr r2, .L2771
.pad #40
sub sp, sp, #40
- ldrh r3, [r3, #130]
mov r5, r0
- ldr r9, .L2835+4
mov r7, r1
- smulbb r3, r2, r3
- ldr r2, [r9, #1688]
- str r2, [sp, #12]
- ldr r2, [r9, #1720]
+ ldr r9, .L2771+4
+ ldrh r3, [r2, #138]
+ ldrh r2, [r2, #136]
+ smulbb r3, r3, r2
+ ldr r2, [r9, #1696]
uxth r3, r3
+ str r2, [sp, #12]
+ ldr r2, [r9, #1728]
sub r6, r3, #1
- sub r4, r3, #16
- mul r10, r3, r1
+ mul r10, r1, r3
uxth r6, r6
+ sub r4, r3, #16
str r2, [sp, #16]
-.L2821:
+.L2759:
cmp r6, r4
- ble .L2834
- mov r1, #1
+ mvnle r0, #0
+ ble .L2758
+.L2765:
add r3, r6, r10
+ mov r2, #1
+ lsl r3, r3, #10
+ mov r1, r2
add r0, sp, #4
- mov r2, r1
- mov r3, r3, asl #10
str r3, [sp, #8]
bl FlashReadPages
ldr r3, [sp, #4]
cmn r3, #1
- beq .L2822
- ldr r3, [r9, #1720]
+ beq .L2760
+ ldr r3, [r9, #1728]
ldrh r2, [r3]
movw r3, #61664
cmp r2, r3
- bne .L2822
+ bne .L2760
cmp r5, #0
moveq r0, r5
- beq .L2823
+ beq .L2758
cmp r7, #0
- ldreq ip, .L2835+4
+ moveq r1, r7
moveq lr, #1
- beq .L2824
-.L2826:
- ldr r1, [r9, #1688]
+ beq .L2763
+.L2762:
mov r2, r8
+ ldr r1, [r9, #1696]
mov r0, r5
bl ftl_memcpy
- mov r2, #4
- ldr r0, .L2835+8
+ mov r3, #4
+ ldr r0, .L2771+8
+ mov r2, r3
mov r1, r5
- mov r3, r2
bl rknand_print_hex
mov r0, #0
- b .L2823
-.L2824:
- ldr r2, [r9, #1708]
- uxth r3, r7
- add r7, r7, #1
- cmp r3, r2
- bcs .L2826
- ldr r1, [ip, #1688]
- mov r0, r3, lsr #5
- and r4, r3, #31
- ldr r2, [r1, r0, asl #2]
- orr r4, r2, lr, asl r4
- str r4, [r1, r0, asl #2]
- b .L2824
-.L2822:
- sub r6, r6, #1
- uxth r6, r6
- b .L2821
-.L2834:
- mvn r0, #0
-.L2823:
+.L2758:
add sp, sp, #40
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L2836:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L2764:
+ ldr r0, [r9, #1696]
+ lsr ip, r3, #5
+ and r3, r3, #31
+ ldr r2, [r0, ip, lsl #2]
+ orr r3, r2, lr, lsl r3
+ str r3, [r0, ip, lsl #2]
+.L2763:
+ ldr r0, [r9, #1716]
+ uxth r3, r1
+ add r1, r1, #1
+ cmp r3, r0
+ bcc .L2764
+ b .L2762
+.L2760:
+ sub r6, r6, #1
+ uxth r6, r6
+ b .L2759
+.L2772:
.align 2
-.L2835:
+.L2771:
.word .LANCHOR0
.word .LANCHOR2
.word .LC139
@@ -16989,378 +17482,371 @@
.size FlashReadFacBbtData, .-FlashReadFacBbtData
.align 2
.global FlashGetBadBlockList
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashGetBadBlockList, %function
FlashGetBadBlockList:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L2848
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ ldr r3, .L2784
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
mov r5, r0
- ldr r3, [r3, #44]
- ldr r6, .L2848+4
+ ldr r6, .L2784+4
+ ldr r3, [r3, #48]
+ ldr r0, [r6, #1724]
ldrb r4, [r3, #13] @ zero_extendqisi2
ldrh r3, [r3, #14]
- ldr r0, [r6, #1716]
smulbb r4, r4, r3
uxth r4, r4
add r2, r4, #7
- mov r2, r2, asr #3
+ asr r2, r2, #3
bl FlashReadFacBbtData
cmn r0, #1
- bne .L2838
-.L2842:
+ bne .L2774
+.L2778:
mov r3, #0
- b .L2839
-.L2838:
- mov lr, r4, lsr #4
- mov ip, #0
- sub r4, r4, #1
- mov r3, ip
- mov r7, #1
-.L2840:
- uxth r0, ip
- cmp r0, r4
- bge .L2839
- ldr r8, [r6, #1716]
- mov r1, r0, lsr #5
- and r2, r0, #31
- add ip, ip, #1
- ldr r1, [r8, r1, asl #2]
- ands r2, r1, r7, asl r2
- addne r2, r3, #1
- movne r3, r3, asl #1
- strneh r0, [r5, r3] @ movhi
- uxthne r3, r2
- cmp r3, lr
- bcc .L2840
- b .L2842
-.L2839:
- mov r3, r3, asl #1
+.L2775:
+ lsl r3, r3, #1
mvn r2, #0
mov r0, #0
strh r2, [r5, r3] @ movhi
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L2849:
+ pop {r4, r5, r6, r7, r8, pc}
+.L2774:
+ mov r2, #0
+ lsr lr, r4, #4
+ mov r3, r2
+ sub r4, r4, #1
+ mov r7, #1
+.L2776:
+ uxth r1, r2
+ cmp r1, r4
+ bge .L2775
+ ldr r8, [r6, #1724]
+ lsr ip, r1, #5
+ and r0, r1, #31
+ add r2, r2, #1
+ ldr ip, [r8, ip, lsl #2]
+ ands r0, ip, r7, lsl r0
+ addne r0, r3, #1
+ lslne r3, r3, #1
+ strhne r1, [r5, r3] @ movhi
+ uxthne r3, r0
+ cmp r3, lr
+ bcc .L2776
+ b .L2778
+.L2785:
.align 2
-.L2848:
+.L2784:
.word .LANCHOR0
.word .LANCHOR2
.fnend
.size FlashGetBadBlockList, .-FlashGetBadBlockList
.align 2
.global FtlMakeBbt
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlMakeBbt, %function
FtlMakeBbt:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- ldr r4, .L2874
- ldr r5, [r4, #-3616]
- cmp r5, #0
- bne .L2851
+ ldr r4, .L2807
+ ldr r8, [r4, #-3612]
+ cmp r8, #0
+ bne .L2787
+ ldr r9, .L2807+4
bl FtlBbtMemInit
- ldr r7, .L2874+4
bl FtlLoadFactoryBbt
- sub r9, r7, #18
- sub r10, r7, #94
-.L2852:
- ldr r3, .L2874+8
- ldr r6, .L2874+12
+ sub r10, r9, #18
+ sub r5, r9, #28
+.L2788:
+ ldr r3, .L2807+8
+ ldr r6, .L2807+12
ldrh r3, [r3]
- cmp r5, r3
- bcs .L2871
- ldrh r3, [r9, #2]!
+ cmp r8, r3
+ bcc .L2794
+ ldr r8, .L2807+16
+ mov r7, #0
+.L2795:
+ ldrh r3, [r8]
+ uxth r0, r7
+ add r7, r7, #1
+ cmp r3, r0
+ bhi .L2796
+ ldrh r7, [r5, #12]
+ movw r8, #65535
+ sub r7, r7, #1
+ uxth r7, r7
+.L2797:
+ ldrh r3, [r5, #12]
+ sub r3, r3, #48
+ cmp r7, r3
+ ble .L2801
+ mov r0, r7
+ bl FtlBbmIsBadBlock
+ cmp r0, #1
+ beq .L2798
+ mov r0, r7
+ bl FlashTestBlk
+ cmp r0, #0
+ beq .L2799
+ mov r0, r7
+ bl FtlBbmMapBadBlock
+.L2798:
+ sub r7, r7, #1
+ uxth r7, r7
+ b .L2797
+.L2794:
+ ldr r3, [r4, #-500]
movw r2, #65535
ldr r0, [r4, #-524]
- ldr fp, [r4, #-500]
+ ldr fp, .L2807+20
+ str r3, [sp, #4]
+ str r3, [r4, #1772]
+ ldrh r3, [r10, #2]!
+ str r0, [r4, #1768]
cmp r3, r2
- ldr r8, .L2874
- str r0, [r4, #1760]
- str fp, [r4, #1764]
- beq .L2853
- ldrh ip, [r10]
- mov r1, #1
- mov r2, r1
- ldr r0, .L2874+16
- mla ip, ip, r5, r3
- mov r3, ip, asl #10
- str ip, [sp, #4]
- str r3, [r8, #1756]
+ beq .L2789
+ ldrh r7, [fp]
+ mov r2, #1
+ mov r1, r2
+ ldr r0, .L2807+24
+ mla r7, r8, r7, r3
+ lsl r3, r7, #10
+ str r3, [r4, #1764]
bl FlashReadPages
- ldrh r2, [r10]
- ldr r0, [r7]
+ ldrh r2, [fp]
+ ldr r1, [r4, #1768]
+ ldr r0, [r9]
add r2, r2, #7
- ldr r1, [r8, #1760]
- mov r2, r2, asr #3
+ asr r2, r2, #3
bl ftl_memcpy
- ldr ip, [sp, #4]
- b .L2854
-.L2853:
- mov r1, r5
- sub r8, r8, #436
+.L2790:
+ uxth r0, r7
+ add r8, r8, #1
+ add r9, r9, #4
+ bl FtlBbmMapBadBlock
+ b .L2788
+.L2789:
+ mov r1, r8
bl FlashGetBadBlockList
- ldr r0, [r8, #2196]
- ldr r1, [r7]
+ ldr r1, [r9]
+ ldr r0, [r4, #1768]
bl FtlBbt2Bitmap
- ldrh r6, [r10]
+ ldrh r6, [fp]
+.L2792:
sub r6, r6, #1
uxth r6, r6
-.L2855:
- ldrh r0, [r10]
- smlabb r0, r0, r5, r6
+.L2791:
+ ldrh r0, [fp]
+ smlabb r0, r0, r8, r6
uxth r0, r0
bl FtlBbmIsBadBlock
cmp r0, #1
- subeq r6, r6, #1
- uxtheq r6, r6
- beq .L2855
-.L2872:
- mov r1, #0
+ beq .L2792
mov r2, #16
- strh r6, [r9] @ movhi
+ mov r1, #0
+ strh r6, [r10] @ movhi
ldr r0, [r4, #-500]
bl ftl_memset
- ldr r3, .L2874+20
- strh r3, [fp] @ movhi
+ ldr r3, [sp, #4]
+ movw r2, 61664 @ movhi
+ strh r2, [r3] @ movhi
mov r3, #0
- str r3, [fp, #4]
- ldrh r3, [r9]
- ldrh ip, [r10]
- ldrh r2, [r8]
- strh r3, [fp, #2] @ movhi
- ldrh r3, [r9]
- ldr r1, [r7]
- mov r2, r2, asl #2
- ldr r0, [r4, #1760]
- mla ip, ip, r5, r3
- mov r3, ip, asl #10
- str r3, [r4, #1756]
- str ip, [sp, #4]
+ ldr r2, [sp, #4]
+ ldrh r7, [fp]
+ str r3, [r2, #4]
+ ldrh r3, [r10]
+ strh r3, [r2, #2] @ movhi
+ ldrh r3, [r10]
+ ldr r1, [r9]
+ ldr r0, [r4, #1768]
+ mla r7, r8, r7, r3
+ lsl r3, r7, #10
+ str r3, [r4, #1764]
+ ldr r3, .L2807+28
+ ldrh r2, [r3]
+ lsl r2, r2, #2
bl ftl_memcpy
- mov r1, #1
- ldr r0, .L2874+16
- mov r2, r1
+ mov r2, #1
+ ldr r0, .L2807+24
+ mov r1, r2
bl FlashEraseBlocks
- mov r1, #1
- mov r3, r1
- ldr r0, .L2874+16
- mov r2, r1
+ mov r3, #1
+ ldr r0, .L2807+24
+ mov r2, r3
+ mov r1, r3
bl FlashProgPages
- ldr r3, [r4, #1752]
+ ldr r3, [r4, #1760]
cmn r3, #1
- ldr ip, [sp, #4]
- bne .L2854
- uxth r0, ip
+ bne .L2790
+ uxth r0, r7
bl FtlBbmMapBadBlock
- b .L2855
-.L2854:
- uxth r0, ip
- add r5, r5, #1
+ b .L2791
+.L2796:
bl FtlBbmMapBadBlock
- add r7, r7, #4
- b .L2852
-.L2871:
- ldr r7, .L2874+24
- mov r5, #0
-.L2859:
- ldrh r3, [r7]
- uxth r0, r5
- add r5, r5, #1
- cmp r3, r0
- bls .L2873
- bl FtlBbmMapBadBlock
- b .L2859
-.L2873:
- ldr r7, .L2874+28
- movw r9, #65535
- ldrh r5, [r7, #12]
- mov r8, r7
- sub r5, r5, #1
- uxth r5, r5
-.L2861:
- ldrh r3, [r7, #12]
- sub r3, r3, #48
- cmp r5, r3
- ble .L2865
- mov r0, r5
- bl FtlBbmIsBadBlock
- cmp r0, #1
- beq .L2862
- mov r0, r5
- bl FlashTestBlk
- cmp r0, #0
- beq .L2863
- mov r0, r5
- bl FtlBbmMapBadBlock
- b .L2862
-.L2863:
- ldrh r3, [r8]
- cmp r3, r9
- streqh r5, [r8] @ movhi
-.L2864:
- ldrne r3, .L2874+28
- strneh r5, [r3, #4] @ movhi
- bne .L2865
-.L2862:
- sub r5, r5, #1
- uxth r5, r5
- b .L2861
-.L2865:
- movw r5, #2452
- ldr r0, [r4, #-3612]
- ldrh r3, [r6, r5]
+ b .L2795
+.L2799:
+ ldrh r3, [r5]
+ cmp r3, r8
+ strheq r7, [r5] @ movhi
+ beq .L2798
+.L2800:
+ strh r7, [r5, #4] @ movhi
+.L2801:
+ movw r7, #2456
+ ldr r0, [r4, #-3608]
+ ldrh r3, [r6, r7]
mov r8, #0
- str r8, [r6, #2460]
+ str r8, [r6, #2464]
mov r2, #2
mov r1, #1
- strh r8, [r7, #2] @ movhi
- mov r3, r3, asl #10
+ strh r8, [r5, #2] @ movhi
+ lsl r3, r3, #10
str r3, [r0, #4]
- ldrh r3, [r7, #4]
- mov r3, r3, asl #10
+ ldrh r3, [r5, #4]
+ lsl r3, r3, #10
str r3, [r0, #40]
bl FlashEraseBlocks
- ldrh r0, [r6, r5]
+ ldrh r0, [r6, r7]
bl FtlBbmMapBadBlock
- ldrh r0, [r7, #4]
+ ldrh r0, [r5, #4]
bl FtlBbmMapBadBlock
bl FtlBbmTblFlush
- ldr r3, [r6, #2460]
- ldrh r2, [r7, #4]
+ ldr r3, [r6, #2464]
+ ldrh r2, [r5, #4]
+ strh r8, [r5, #2] @ movhi
add r3, r3, #1
- str r3, [r6, #2460]
- ldrh r3, [r6, r5]
- strh r8, [r7, #2] @ movhi
- strh r2, [r6, r5] @ movhi
- strh r3, [r7, #4] @ movhi
+ str r3, [r6, #2464]
+ ldrh r3, [r6, r7]
+ strh r2, [r6, r7] @ movhi
+ strh r3, [r5, #4] @ movhi
bl FtlBbmTblFlush
-.L2851:
+.L2787:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2875:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2808:
.align 2
-.L2874:
+.L2807:
.word .LANCHOR2
- .word .LANCHOR0+2480
- .word .LANCHOR0+2342
+ .word .LANCHOR0+2484
+ .word .LANCHOR0+2346
.word .LANCHOR0
- .word .LANCHOR2+1752
- .word -3872
- .word .LANCHOR0+2402
- .word .LANCHOR0+2452
+ .word .LANCHOR0+2404
+ .word .LANCHOR0+2388
+ .word .LANCHOR2+1760
+ .word .LANCHOR2-436
.fnend
.size FtlMakeBbt, .-FtlMakeBbt
.align 2
.global log2phys
+ .syntax unified
+ .arm
+ .fpu softvfp
.type log2phys, %function
log2phys:
.fnstart
- @ args = 0, pretend = 0, frame = 8
+ @ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #12
- movw r3, #2396
- ldr r7, .L2893
- ldrh r10, [r7, r3]
- ldr r3, [r7, #2448]
+ .pad #20
+ sub sp, sp, #20
+ ldr r8, .L2825
+ ldr r3, [r8, #2452]
cmp r0, r3
- bcs .L2877
- add r10, r10, #7
- ldr fp, .L2893+4
- mov r5, r0, lsr r10
- movw r3, #2426
- str r2, [sp, #4]
- mov r9, r1
- mov r6, r7
- str r0, [sp]
- uxth r5, r5
- ldrh r2, [r7, r3]
- ldr r8, [fp, #-3380]
- mov r4, #0
- mov r1, #12
- b .L2878
-.L2877:
+ bcs .L2810
+ movw r3, #2398
+ mov r10, r0
+ ldrh r0, [r8, r3]
+ mov r5, #12
+ ldr r4, .L2825+4
+ str r1, [sp, #8]
+ add r3, r0, #7
+ str r2, [sp, #12]
+ lsr r6, r10, r3
+ ldr fp, [r4, #-3376]
+ str r3, [sp, #4]
+ movw r3, #2430
+ uxth r9, r6
+ ldrh r1, [r8, r3]
+ mov r3, #0
+.L2811:
+ uxth r7, r3
+ cmp r7, r1
+ bcc .L2816
+ bl select_l2p_ram_region
+ mul r5, r5, r0
+ movw r2, #65535
+ mov r7, r0
+ ldrh r1, [fp, r5]
+ add r3, fp, r5
+ cmp r1, r2
+ beq .L2817
+ ldr r3, [r3, #4]
+ cmp r3, #0
+ bge .L2817
+ bl flush_l2p_region
+.L2817:
+ ldr r3, [r4, #-452]
+ uxth r6, r6
+ ldr fp, [r3, r6, lsl #2]
+ cmp fp, #0
+ bne .L2818
+ ldr r0, [r4, #-3376]
+ mov r1, #255
+ ldr r2, .L2825+8
+ add r0, r0, r5
+ ldrh r2, [r2]
+ ldr r0, [r0, #8]
+ bl ftl_memset
+ ldr r2, [r4, #-3376]
+ strh r9, [r2, r5] @ movhi
+ ldr r2, [r4, #-3376]
+ add r5, r2, r5
+ str fp, [r5, #4]
+ b .L2813
+.L2810:
cmp r2, #0
mvn r0, #0
streq r0, [r1]
- b .L2879
-.L2883:
- add r4, r4, #1
- mla r0, r1, r4, r8
+.L2809:
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2816:
+ add r3, r3, #1
+ mla r0, r5, r3, fp
ldrh r0, [r0, #-12]
- cmp r0, r5
- beq .L2880
-.L2878:
- uxth r7, r4
- cmp r7, r2
- bcc .L2883
- bl select_l2p_ram_region
- mov r4, #12
- movw r3, #65535
- mul r4, r4, r0
- mov r7, r0
- add r2, r8, r4
- ldrh r1, [r8, r4]
- cmp r1, r3
- bne .L2892
-.L2884:
- ldr r3, [fp, #-452]
- ldr r8, .L2893+4
- ldr fp, [r3, r5, asl #2]
- cmp fp, #0
- bne .L2885
- ldr r3, [r8, #-3380]
- mov r1, #255
- add r3, r3, r4
- ldr r0, [r3, #8]
- movw r3, #2398
- ldrh r2, [r6, r3]
- bl ftl_memset
- ldr r3, [r8, #-3380]
- strh r5, [r3, r4] @ movhi
- ldr r3, [r8, #-3380]
- add r4, r3, r4
- str fp, [r4, #4]
-.L2880:
- ldr r2, [sp]
- mvn r3, #0
- mov r6, #12
- bic r10, r2, r3, asl r10
+ cmp r0, r9
+ bne .L2811
+.L2813:
ldr r3, [sp, #4]
- ldr r2, .L2893+4
- cmp r3, #0
+ mvn r0, #0
+ ldr r1, .L2825+4
+ bic r10, r10, r0, lsl r3
+ ldr r3, [sp, #12]
uxth r10, r10
- bne .L2881
- ldr r3, [r2, #-3380]
- mla r6, r6, r7, r3
- ldr r3, [r6, #8]
- ldr r3, [r3, r10, asl #2]
- str r3, [r9]
- b .L2882
-.L2881:
- mul r6, r6, r7
- ldr r3, [r2, #-3380]
- ldr r1, [r9]
- add r3, r3, r6
+ cmp r3, #0
+ mov r3, #12
+ bne .L2814
+ ldr r2, [r1, #-3376]
+ mla r3, r3, r7, r2
+ ldr r2, [sp, #8]
ldr r3, [r3, #8]
- str r1, [r3, r10, asl #2]
- ldr r3, [r2, #-3380]
- add r6, r3, r6
- ldr r3, [r6, #4]
- orr r3, r3, #-2147483648
- str r3, [r6, #4]
- sub r3, r2, #3376
- strh r5, [r3] @ movhi
-.L2882:
- ldr r2, [r2, #-3380]
+ ldr r3, [r3, r10, lsl #2]
+ str r3, [r2]
+.L2815:
+ ldr r2, [r1, #-3376]
mov r3, #12
mov r0, #0
mla r7, r3, r7, r2
@@ -17368,1841 +17854,1868 @@
cmn r3, #1
addne r3, r3, #1
strne r3, [r7, #4]
- b .L2879
-.L2892:
- ldr r3, [r2, #4]
- cmp r3, #0
- bge .L2884
- bl flush_l2p_region
- b .L2884
-.L2885:
- ldr r3, [r8, #-3380]
- mov r1, #1
- ldr r0, .L2893+8
- mov r2, r1
- add r3, r3, r4
- str fp, [r8, #1756]
- ldr r3, [r3, #8]
- str r3, [r8, #1760]
- ldr r3, [r8, #-500]
- str r3, [r8, #1764]
+ b .L2809
+.L2814:
+ ldr r2, [sp, #8]
+ mul r3, r3, r7
+ ldr r0, [r2]
+ ldr r2, [r4, #-3376]
+ add r2, r2, r3
+ ldr r2, [r2, #8]
+ str r0, [r2, r10, lsl #2]
+ ldr r2, [r4, #-3376]
+ add r3, r2, r3
+ ldr r2, [r3, #4]
+ orr r2, r2, #-2147483648
+ str r2, [r3, #4]
+ sub r3, r1, #3360
+ strh r9, [r3, #-12] @ movhi
+ b .L2815
+.L2818:
+ ldr r2, [r4, #-3376]
+ ldr r0, .L2825+12
+ str fp, [r4, #1764]
+ add r2, r2, r5
+ ldr r2, [r2, #8]
+ str r2, [r4, #1768]
+ ldr r2, [r4, #-500]
+ str r2, [r4, #1772]
+ mov r2, #1
+ mov r1, r2
bl FlashReadPages
- ldr r3, [r8, #1764]
- ldrh r3, [r3, #8]
- cmp r3, r5
- beq .L2886
- mov r1, r5
+ ldr r2, [r4, #1772]
+ ldrh r2, [r2, #8]
+ cmp r2, r9
+ beq .L2819
mov r2, fp
- ldr r0, .L2893+12
+ mov r1, r6
+ ldr r0, .L2825+16
bl printk
- mov r2, #4
- mov r3, r2
- ldr r0, .L2893+16
- ldr r1, [r8, #1764]
+ mov r3, #4
+ ldr r1, [r4, #1772]
+ mov r2, r3
+ ldr r0, .L2825+20
bl rknand_print_hex
- movw r3, #2424
- ldrh r3, [r6, r3]
+ movw r3, #2428
mov r2, #4
- ldr r0, .L2893+20
- ldr r1, [r8, #-452]
+ ldrh r3, [r8, r3]
+ ldr r1, [r4, #-452]
+ ldr r0, .L2825+24
bl rknand_print_hex
mov r3, #1
- str r3, [r8, #-3616]
- b .L2887
-.L2886:
- ldr r3, [r8, #1752]
- cmp r3, #256
- bne .L2887
- mov r1, r5
+ str r3, [r4, #-3612]
+.L2820:
+ ldr r3, .L2825+4
+ mov r1, #0
+ ldr r3, [r3, #-3376]
+ add r2, r3, r5
+ str r1, [r2, #4]
+ strh r9, [r3, r5] @ movhi
+ b .L2813
+.L2819:
+ ldr r2, [r4, #1760]
+ cmp r2, #256
+ bne .L2820
mov r2, fp
- ldr r0, .L2893+24
+ mov r1, r6
+ ldr r0, .L2825+28
bl printk
- ldr r3, [r8, #-3380]
- sub r0, r8, #432
- mov r1, r5
- add r3, r3, r4
+ ldr r3, [r4, #-3376]
+ mov r1, r6
+ ldr r0, .L2825+32
+ add r3, r3, r5
ldr r2, [r3, #8]
bl FtlMapWritePage
-.L2887:
- ldr r3, .L2893+4
- mov r1, #0
- ldr r3, [r3, #-3380]
- add r2, r3, r4
- str r1, [r2, #4]
- strh r5, [r3, r4] @ movhi
- b .L2880
-.L2879:
- add sp, sp, #12
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2894:
+ b .L2820
+.L2826:
.align 2
-.L2893:
+.L2825:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2400
+ .word .LANCHOR2+1760
.word .LC140
.word .LC101
.word .LC141
.word .LC142
+ .word .LANCHOR2-432
.fnend
.size log2phys, .-log2phys
.align 2
.global FtlWriteDumpData
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlWriteDumpData, %function
FtlWriteDumpData:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #44
sub sp, sp, #44
- ldr r4, .L2915
- ldr r3, [r4, #-3616]
+ ldr r4, .L2846
+ ldr r3, [r4, #-3612]
cmp r3, #0
- bne .L2895
- ldr r3, .L2915+4
- ldrh r2, [r3, #4]
+ bne .L2827
+ sub r6, r4, #3520
+ ldrh r2, [r6, #4]
cmp r2, #0
- beq .L2897
- ldrb r3, [r4, #-3516] @ zero_extendqisi2
+ beq .L2829
+ ldrb r3, [r4, #-3512] @ zero_extendqisi2
cmp r3, #0
- bne .L2897
- ldr r8, .L2915+8
- movw r3, #2388
- ldrb r1, [r4, #-3517] @ zero_extendqisi2
+ bne .L2829
+ ldr r8, .L2846+4
+ movw r3, #2390
+ ldrb r1, [r4, #-3513] @ zero_extendqisi2
ldrh r3, [r8, r3]
mul r3, r3, r1
cmp r2, r3
- beq .L2897
- ldrb r9, [r4, #-3514] @ zero_extendqisi2
- add r3, r8, #2320
- ldr r6, [r8, #2448]
- cmp r9, #0
- ldrh r7, [r3]
- bne .L2895
- sub r6, r6, #1
+ beq .L2829
+ ldrb r10, [r4, #-3510] @ zero_extendqisi2
+ cmp r10, #0
+ bne .L2827
+ ldr r7, [r8, #2452]
+ movw r3, #2324
+ mov r2, r10
mov r1, sp
- mov r2, r9
- mov r0, r6
+ ldrh r9, [r8, r3]
+ sub r7, r7, #1
+ mov r0, r7
bl log2phys
+ ldr r3, [sp]
ldr r5, [r4, #-500]
ldr r0, [r4, #-524]
- ldr r3, [sp]
- str r6, [sp, #20]
cmn r3, #1
- str r0, [sp, #12]
str r3, [sp, #8]
+ str r7, [sp, #20]
+ str r0, [sp, #12]
str r5, [sp, #16]
- str r9, [r5, #4]
- beq .L2899
+ str r10, [r5, #4]
+ beq .L2831
+ mov r2, r10
mov r1, #1
- mov r2, r9
add r0, sp, #4
bl FlashReadPages
- b .L2900
-.L2899:
- movw r3, #2398
- mov r1, #255
- ldrh r2, [r8, r3]
- bl ftl_memset
-.L2900:
- ldr fp, .L2915+4
- mov r7, r7, asl #2
- ldr r3, .L2915+12
+.L2832:
+ ldr r10, .L2846+8
mov r8, #0
- ldr r9, .L2915
- mov r10, fp
+ ldr r3, .L2846+12
+ lsl r9, r9, #2
+ mov fp, r8
strh r3, [r5] @ movhi
-.L2901:
- cmp r8, r7
- beq .L2902
- ldrh r3, [fp, #4]
+.L2833:
+ cmp r9, r8
+ bne .L2837
+.L2834:
+ mov r3, #1
+.L2845:
+ strb r3, [r4, #-3510]
+.L2827:
+ add sp, sp, #44
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2831:
+ add r8, r8, #2400
+ mov r1, #255
+ ldrh r2, [r8]
+ bl ftl_memset
+ b .L2832
+.L2837:
+ ldrh r3, [r6, #4]
cmp r3, #0
- beq .L2902
+ beq .L2834
ldr r3, [sp, #8]
+ mov r0, r10
+ str r7, [r5, #8]
add r8, r8, #1
- str r6, [r5, #8]
- ldr r0, .L2915+4
str r3, [r5, #12]
- ldrh r3, [fp]
+ ldrh r3, [r6]
strh r3, [r5, #2] @ movhi
bl get_new_active_ppa
- ldr r3, [r9, #-3328]
- mov r2, #0
+ ldr r3, [r4, #-3328]
mov r1, #1
str r0, [sp, #8]
add r0, sp, #4
str r3, [r5, #4]
add r3, r3, #1
cmn r3, #1
- moveq r3, #0
- str r3, [r9, #-3328]
- mov r3, r2
- bl FlashProgPages
- ldrh r0, [r10]
- bl decrement_vpc_count
- b .L2901
-.L2902:
- mov r3, #1
- b .L2914
-.L2897:
+ moveq r3, fp
+ str r3, [r4, #-3328]
mov r3, #0
-.L2914:
- strb r3, [r4, #-3514]
-.L2895:
- add sp, sp, #44
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L2916:
+ mov r2, r3
+ bl FlashProgPages
+ ldrh r0, [r6]
+ bl decrement_vpc_count
+ b .L2833
+.L2829:
+ mov r3, #0
+ b .L2845
+.L2847:
.align 2
-.L2915:
+.L2846:
.word .LANCHOR2
- .word .LANCHOR2-3524
.word .LANCHOR0
+ .word .LANCHOR2-3520
.word -3947
.fnend
.size FtlWriteDumpData, .-FtlWriteDumpData
.align 2
.global l2p_flush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type l2p_flush, %function
l2p_flush:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- bl FtlWriteDumpData
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mov r4, #0
- ldr r5, .L2923
+ ldr r5, .L2853
mov r7, #12
- ldr r6, .L2923+4
-.L2918:
+ ldr r6, .L2853+4
+ bl FtlWriteDumpData
+.L2849:
ldrh r3, [r5]
uxth r0, r4
cmp r3, r0
- bls .L2922
- ldr r3, [r6, #-3380]
- mla r3, r7, r0, r3
+ bhi .L2851
+ mov r0, #0
+ pop {r4, r5, r6, r7, r8, pc}
+.L2851:
+ ldr r2, [r6, #-3376]
+ uxth r3, r4
+ mla r3, r7, r3, r2
ldr r3, [r3, #4]
cmp r3, #0
- bge .L2919
+ bge .L2850
bl flush_l2p_region
-.L2919:
+.L2850:
add r4, r4, #1
- b .L2918
-.L2922:
- mov r0, #0
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L2924:
+ b .L2849
+.L2854:
.align 2
-.L2923:
- .word .LANCHOR0+2426
+.L2853:
+ .word .LANCHOR0+2430
.word .LANCHOR2
.fnend
.size l2p_flush, .-l2p_flush
.align 2
.global allocate_new_data_superblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type allocate_new_data_superblock, %function
allocate_new_data_superblock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
- .save {r4, r5, r6, lr}
- ldr r5, .L2952
- ldrh r6, [r0]
- ldr r3, [r5, #-3616]
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ ldr r4, .L2882
+ ldr r3, [r4, #-3612]
cmp r3, #0
- bne .L2926
+ bne .L2856
+ ldrh r5, [r0]
movw r3, #65535
- cmp r6, r3
- mov r4, r0
- beq .L2927
- ldr r2, [r5, #-3544]
- mov r3, r6, asl #1
- mov r0, r6
+ mov r7, r0
+ cmp r5, r3
+ beq .L2857
+ ldr r2, [r4, #-3540]
+ lsl r3, r5, #1
+ mov r0, r5
ldrh r3, [r2, r3]
cmp r3, #0
- beq .L2928
+ beq .L2858
bl INSERT_DATA_LIST
- b .L2927
-.L2928:
- bl INSERT_FREE_LIST
-.L2927:
+.L2857:
+ ldr r2, .L2882+4
mov r3, #0
- strb r3, [r4, #8]
- ldr r3, .L2952+4
- cmp r4, r3
- beq .L2929
- ldr r3, .L2952+8
- movw r2, #2340
- ldrh r2, [r3, r2]
- cmp r2, #1
- beq .L2929
- ldrb r1, [r3, #144] @ zero_extendqisi2
- cmp r1, #0
- beq .L2930
-.L2929:
+ strb r3, [r7, #8]
+ cmp r7, r2
+ beq .L2859
+ ldr r3, .L2882+8
+ movw r1, #2344
+ ldrh r1, [r3, r1]
+ cmp r1, #1
+ beq .L2859
+ ldrb r0, [r3, #152] @ zero_extendqisi2
+ cmp r0, #0
+ beq .L2860
+.L2859:
mov r3, #1
- strb r3, [r4, #8]
- b .L2931
-.L2930:
- ldr r1, .L2952+12
- cmp r4, r1
- bne .L2931
- cmp r2, #3
- beq .L2933
- ldr r2, .L2952
- ldr r2, [r2, #-3236]
- cmp r2, #1
- bne .L2934
-.L2933:
- mov r2, #1
- strb r2, [r5, #-3516]
-.L2934:
- ldr r3, [r3, #2244]
- cmp r3, #0
- beq .L2931
- ldr r3, [r5, #-3308]
- cmp r3, #39
- ldrls r3, .L2952
- movls r2, #1
- strlsb r2, [r3, #-3516]
-.L2931:
- ldr r2, .L2952
- movw r1, #65535
- sub r3, r2, #380
+ strb r3, [r7, #8]
+.L2861:
+ ldr r3, .L2882+12
+ movw r2, #65535
ldrh r0, [r3]
- mov r5, r3
- cmp r0, r1
- beq .L2936
- cmp r6, r0
- bne .L2937
- ldr r2, [r2, #-3544]
- mov r3, r0, asl #1
+ mov r6, r3
+ cmp r0, r2
+ beq .L2866
+ cmp r5, r0
+ bne .L2867
+ ldr r2, [r4, #-3540]
+ lsl r3, r0, #1
ldrh r3, [r2, r3]
cmp r3, #0
- beq .L2938
-.L2937:
+ beq .L2868
+.L2867:
bl update_vpc_list
-.L2938:
+.L2868:
mvn r3, #0
- strh r3, [r5] @ movhi
-.L2936:
- mov r0, r4
+ strh r3, [r6] @ movhi
+.L2866:
+ mov r0, r7
bl allocate_data_superblock
bl l2p_flush
mov r0, #0
bl FtlEctTblFlush
bl FtlVpcTblFlush
-.L2926:
+.L2856:
mov r0, #0
- ldmfd sp!, {r4, r5, r6, pc}
-.L2953:
+ pop {r4, r5, r6, r7, r8, pc}
+.L2858:
+ bl INSERT_FREE_LIST
+ b .L2857
+.L2860:
+ sub r2, r2, #48
+ cmp r7, r2
+ bne .L2861
+ cmp r1, #3
+ beq .L2863
+ ldr r2, [r4, #-2724]
+ cmp r2, #1
+ bne .L2864
+.L2863:
+ mov r2, #1
+ strb r2, [r4, #-3512]
+.L2864:
+ ldr r3, [r3, #2248]
+ cmp r3, #0
+ beq .L2861
+ ldr r3, [r4, #-3308]
+ cmp r3, #39
+ movls r3, #1
+ strbls r3, [r4, #-3512]
+ b .L2861
+.L2883:
.align 2
-.L2952:
+.L2882:
.word .LANCHOR2
- .word .LANCHOR2-3476
+ .word .LANCHOR2-3472
.word .LANCHOR0
- .word .LANCHOR2-3524
+ .word .LANCHOR2-380
.fnend
.size allocate_new_data_superblock, .-allocate_new_data_superblock
.align 2
.global FtlCheckVpc
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlCheckVpc, %function
FtlCheckVpc:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
- .save {r4, r5, r6, r7, r8, r9, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
mov r4, #0
- ldr r1, .L2977
- ldr r0, .L2977+4
+ ldr r6, .L2905
+ ldr r5, .L2905+4
+ ldr r1, .L2905+8
+ ldr r0, .L2905+12
bl printk
- ldr r0, .L2977+8
- mov r1, #0
mov r2, #8192
+ mov r1, #0
+ ldr r0, .L2905+4
bl memset
- ldr r6, .L2977+12
- ldr r5, .L2977+8
-.L2955:
- ldr r3, [r6, #2448]
+.L2885:
+ ldr r3, [r6, #2452]
cmp r4, r3
- bcs .L2975
- mov r0, r4
- add r1, sp, #4
- mov r2, #0
- bl log2phys
- ldr r0, [sp, #4]
- cmn r0, #1
- beq .L2956
- ubfx r0, r0, #10, #16
- bl P2V_block_in_plane
- mov r0, r0, asl #1
- ldrh r3, [r5, r0]
- add r3, r3, #1
- strh r3, [r5, r0] @ movhi
-.L2956:
- add r4, r4, #1
- b .L2955
-.L2975:
- ldr r7, .L2977+16
+ bcc .L2887
+ ldr r9, .L2905+16
mov r4, #0
- ldr r9, .L2977+20
+ ldr r5, .L2905+20
mov r6, r4
- add r8, r7, #1840
-.L2958:
- ldrh r3, [r9]
- uxth r1, r4
- ldr r5, .L2977+16
- cmp r3, r1
- bls .L2976
- ldr r3, [r7, #-3544]
- mov r5, r1, asl #1
- ldrh r2, [r3, r5]
- ldrh r3, [r8, r5]
+ ldr r8, .L2905+4
+.L2888:
+ ldrh r2, [r9]
+ uxth r3, r4
cmp r2, r3
- beq .L2959
- ldr r0, .L2977+24
- bl printk
- ldr r3, [r7, #-3544]
- movw r2, #65535
- ldrh r3, [r3, r5]
- cmp r3, r2
- beq .L2959
- ldrh r2, [r8, r5]
- cmp r2, r3
- movhi r6, #1
-.L2959:
- add r4, r4, #1
- b .L2958
-.L2976:
- ldr r3, [r5, #-3532]
- cmp r3, #0
- beq .L2961
- sub r2, r5, #3520
- add r9, r5, #1840
- mov r8, #0
- ldrh r7, [r2, #-8]
- ldr r2, [r5, #-3552]
- rsb r3, r2, r3
- ldr r2, .L2977+28
- mov r3, r3, asr #1
- mul r3, r2, r3
- uxth r4, r3
-.L2962:
- uxth r3, r8
- cmp r3, r7
- bcs .L2961
- ldr r2, [r5, #-3544]
- mov r3, r4, asl #1
+ bhi .L2890
+ ldr r4, [r5, #-3528]
+ cmp r4, #0
+ beq .L2891
+ ldr r3, .L2905+24
+ mov r7, #0
+ ldr r9, .L2905+4
+ mov fp, #6
+ ldr r10, .L2905+28
+ ldrh r8, [r3, #-4]
+ ldr r3, [r5, #-3548]
+ sub r4, r4, r3
+ ldr r3, .L2905+32
+ asr r4, r4, #1
+ mul r4, r3, r4
+ uxth r4, r4
+.L2892:
+ uxth r3, r7
+ cmp r8, r3
+ bls .L2891
+ ldr r2, [r5, #-3540]
+ lsl r3, r4, #1
ldrh r2, [r2, r3]
cmp r2, #0
- beq .L2963
- ldr r0, .L2977+32
- mov r1, r4
- ldrh r3, [r9, r3]
+ beq .L2893
mov r6, #1
+ ldrh r3, [r9, r3]
+ mov r1, r4
+ mov r0, r10
bl printk
-.L2963:
- mov r3, #6
- ldr r2, [r5, #-3552]
- mul r4, r3, r4
+.L2893:
+ mul r4, fp, r4
+ ldr r3, [r5, #-3548]
+ add r7, r7, #1
+ ldrh r4, [r3, r4]
movw r3, #65535
- add r8, r8, #1
- ldrh r4, [r2, r4]
cmp r4, r3
- bne .L2962
-.L2961:
+ bne .L2892
+.L2891:
mov r1, r6
- ldr r0, .L2977+36
+ ldr r0, .L2905+36
bl printk
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L2978:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2887:
+ mov r2, #0
+ add r1, sp, #4
+ mov r0, r4
+ bl log2phys
+ ldr r0, [sp, #4]
+ cmn r0, #1
+ beq .L2886
+ ubfx r0, r0, #10, #16
+ bl P2V_block_in_plane
+ lsl r0, r0, #1
+ ldrh r3, [r5, r0]
+ add r3, r3, #1
+ strh r3, [r5, r0] @ movhi
+.L2886:
+ add r4, r4, #1
+ b .L2885
+.L2890:
+ uxth r1, r4
+ ldr r3, [r5, #-3540]
+ lsl r7, r1, #1
+ ldrh r2, [r3, r7]
+ ldrh r3, [r8, r7]
+ cmp r2, r3
+ beq .L2889
+ ldr r0, .L2905+40
+ bl printk
+ ldr r3, [r5, #-3540]
+ movw r2, #65535
+ ldrh r3, [r3, r7]
+ cmp r3, r2
+ beq .L2889
+ ldrh r2, [r8, r7]
+ cmp r2, r3
+ movhi r6, #1
+.L2889:
+ add r4, r4, #1
+ b .L2888
+.L2906:
.align 2
-.L2977:
- .word .LANCHOR3+204
- .word .LC110
- .word .LANCHOR2+1840
+.L2905:
.word .LANCHOR0
+ .word check_valid_page_count_table
+ .word .LANCHOR3+191
+ .word .LC110
+ .word .LANCHOR0+2332
.word .LANCHOR2
- .word .LANCHOR0+2328
- .word .LC143
- .word -1431655765
+ .word .LANCHOR2-3520
.word .LC144
+ .word -1431655765
.word .LC145
+ .word .LC143
.fnend
.size FtlCheckVpc, .-FtlCheckVpc
.align 2
.global Ftlscanalldata
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftlscanalldata, %function
Ftlscanalldata:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
- mov r1, #0
+ mov r5, #0
+ ldr r4, .L2916
.pad #32
sub sp, sp, #32
- ldr r0, .L2989
+ mov r1, #0
+ ldr r7, .L2916+4
+ add r8, r4, #1760
+ ldr r0, .L2916+8
bl printk
- ldr r5, .L2989+4
- ldr r8, .L2989+8
- mov r4, #0
- mov r6, r5
-.L2980:
- ldr r3, [r8, #2448]
- cmp r4, r3
- bcs .L2988
- mov r0, r4
- add r1, sp, #28
- mov r2, #0
- bl log2phys
- ubfx r3, r4, #0, #11
- cmp r3, #0
- bne .L2981
- ldr r0, .L2989+12
- mov r1, r4
- ldr r2, [sp, #28]
- bl printk
-.L2981:
- ldr r3, [sp, #28]
- cmn r3, #1
- beq .L2983
- str r3, [r5, #1756]
- mov r2, #0
- ldr r3, [r5, #-524]
- mov r1, #1
- ldr r7, [r5, #-500]
- ldr r0, .L2989+16
- str r3, [r5, #1760]
- str r4, [r5, #1768]
- str r7, [r5, #1764]
- str r2, [r5, #1752]
- bl FlashReadPages
- ldr r3, [r5, #1752]
- cmn r3, #1
- cmpne r3, #256
- beq .L2984
- ldr r3, [r7, #8]
- cmp r3, r4
- beq .L2983
-.L2984:
- ldr r3, [r6, #1764]
- ldr r2, [r6, #1760]
- ldr r0, .L2989+20
- ldr r1, [r3, #4]
- str r1, [sp]
- ldr r1, [r3, #8]
- str r1, [sp, #4]
- ldr r1, [r3, #12]
- str r1, [sp, #8]
- ldr r1, [r2]
- str r1, [sp, #12]
- mov r1, r4
- ldr r2, [r2, #4]
- str r2, [sp, #16]
- ldr r2, [r6, #1756]
- ldr r3, [r3]
- bl printk
-.L2983:
- add r4, r4, #1
- b .L2980
-.L2988:
+.L2908:
+ ldr r3, [r7, #2452]
+ cmp r5, r3
+ bcc .L2914
add sp, sp, #32
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L2990:
+ pop {r4, r5, r6, r7, r8, pc}
+.L2914:
+ mov r2, #0
+ add r1, sp, #28
+ mov r0, r5
+ bl log2phys
+ ubfx r3, r5, #0, #11
+ cmp r3, #0
+ bne .L2909
+ ldr r2, [sp, #28]
+ mov r1, r5
+ ldr r0, .L2916+12
+ bl printk
+.L2909:
+ ldr r3, [sp, #28]
+ cmn r3, #1
+ beq .L2911
+ str r3, [r4, #1764]
+ mov r2, #0
+ ldr r3, [r4, #-524]
+ mov r1, #1
+ ldr r6, [r4, #-500]
+ mov r0, r8
+ str r5, [r4, #1776]
+ str r3, [r4, #1768]
+ str r6, [r4, #1772]
+ str r2, [r4, #1760]
+ bl FlashReadPages
+ ldr r3, [r4, #1760]
+ cmn r3, #1
+ cmpne r3, #256
+ beq .L2912
+ ldr r3, [r6, #8]
+ cmp r5, r3
+ beq .L2911
+.L2912:
+ ldr r2, [r4, #1768]
+ ldr r3, [r4, #1772]
+ ldr r0, .L2916+16
+ ldr r1, [r2, #4]
+ str r1, [sp, #16]
+ mov r1, r5
+ ldr r2, [r2]
+ str r2, [sp, #12]
+ ldr r2, [r3, #12]
+ str r2, [sp, #8]
+ ldr r2, [r3, #8]
+ str r2, [sp, #4]
+ ldr r2, [r3, #4]
+ str r2, [sp]
+ ldr r2, [r4, #1764]
+ ldr r3, [r3]
+ bl printk
+.L2911:
+ add r5, r5, #1
+ b .L2908
+.L2917:
.align 2
-.L2989:
- .word .LC146
+.L2916:
.word .LANCHOR2
.word .LANCHOR0
+ .word .LC146
.word .LC147
- .word .LANCHOR2+1752
.word .LC148
.fnend
.size Ftlscanalldata, .-Ftlscanalldata
.align 2
.global FtlReUsePrevPpa
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlReUsePrevPpa, %function
FtlReUsePrevPpa:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
.save {r4, r5, r6, r7, r8, r9, lr}
.pad #12
mov r5, r0
+ ldr r6, .L2928
ubfx r0, r1, #10, #16
str r1, [sp, #4]
bl P2V_block_in_plane
- ldr r6, .L3001
- ldr r4, [r6, #-3544]
- mov r7, r0, asl #1
- ldrh r3, [r4, r7]
+ ldr r2, [r6, #-3540]
+ lsl r7, r0, #1
+ ldrh r3, [r2, r7]
cmp r3, #0
- addne r3, r3, #1
- strneh r3, [r4, r7] @ movhi
- bne .L2993
- ldr r4, [r6, #-3532]
+ bne .L2919
+ ldr r4, [r6, #-3528]
cmp r4, #0
- beq .L2993
- ldr r1, [r6, #-3552]
- sub r2, r6, #3520
- ldr lr, .L3001+4
- movw r9, #65535
- rsb r4, r1, r4
- ldrh ip, [r2, #-8]
- mov r8, r2
- mov r4, r4, asr #1
- mul r4, lr, r4
+ beq .L2920
+ ldr r2, [r6, #-3548]
+ sub r8, r6, #3520
+ ldr ip, .L2928+4
mov lr, #6
+ ldrh r1, [r8, #-4]
+ movw r9, #65535
+ sub r4, r4, r2
+ asr r4, r4, #1
+ mul r4, ip, r4
uxth r4, r4
-.L2994:
- uxth r2, r3
- cmp r2, ip
- bcs .L2993
+.L2921:
+ uxth ip, r3
+ cmp r1, ip
+ bls .L2920
cmp r4, r0
- bne .L2995
+ bne .L2922
mov r1, r4
- ldr r0, .L3001+8
+ sub r0, r8, #8
bl List_remove_node
- ldrh r3, [r8, #-8]
+ ldrh r3, [r8, #-4]
mov r0, r4
sub r3, r3, #1
- strh r3, [r8, #-8] @ movhi
+ strh r3, [r8, #-4] @ movhi
bl INSERT_DATA_LIST
- ldr r2, [r6, #-3544]
+ ldr r2, [r6, #-3540]
ldrh r3, [r2, r7]
+.L2919:
add r3, r3, #1
strh r3, [r2, r7] @ movhi
- b .L2993
-.L2995:
+ b .L2920
+.L2922:
mul r4, lr, r4
add r3, r3, #1
- ldrh r4, [r1, r4]
+ ldrh r4, [r2, r4]
cmp r4, r9
- bne .L2994
-.L2993:
- mov r0, r5
- add r1, sp, #4
+ bne .L2921
+.L2920:
mov r2, #1
+ add r1, sp, #4
+ mov r0, r5
bl log2phys
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L3002:
+ pop {r4, r5, r6, r7, r8, r9, pc}
+.L2929:
.align 2
-.L3001:
+.L2928:
.word .LANCHOR2
.word -1431655765
- .word .LANCHOR2-3532
.fnend
.size FtlReUsePrevPpa, .-FtlReUsePrevPpa
.align 2
.global FtlRecoverySuperblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlRecoverySuperblock, %function
FtlRecoverySuperblock:
.fnstart
- @ args = 0, pretend = 0, frame = 64
+ @ args = 0, pretend = 0, frame = 48
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldrh r2, [r0]
+ movw r1, #65535
+ cmp r2, r1
+ beq .L3075
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r2, #65535
- ldrh r3, [r0]
- .pad #68
- sub sp, sp, #68
- mov r4, r0
- cmp r3, r2
- beq .L3144
+ movw r2, #2390
+ ldr r6, .L3087
+ .pad #52
+ sub sp, sp, #52
+ mov r10, r0
ldrh r3, [r0, #2]
- ldr r5, .L3161
+ ldrh r2, [r6, r2]
str r3, [sp, #8]
- ldrb r3, [r0, #6] @ zero_extendqisi2
- ldr r1, [sp, #8]
- str r3, [sp, #16]
- movw r3, #2388
- ldrh r3, [r5, r3]
- cmp r3, r1
- mov r3, #0
- streqh r3, [r0, #4] @ movhi
- streqb r3, [r0, #6]
- ldrneh r0, [r0, #16]
- beq .L3144
-.L3007:
- cmp r0, r2
- add r3, r3, #1
- uxtheq r1, r3
- addeq r1, r4, r1, asl #1
- ldreqh r0, [r1, #16]
- beq .L3007
-.L3156:
- ldrb r1, [r4, #8] @ zero_extendqisi2
- mov r9, r4
+ cmp r2, r3
+ mov r2, #0
+ strheq r2, [r0, #4] @ movhi
+ strbeq r2, [r0, #6]
+ ldrhne r0, [r0, #16]
+ bne .L2934
+.L3073:
+ mov r0, #0
+ add sp, sp, #52
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L2935:
+ uxth r0, r2
+ add r0, r10, r0, lsl #1
+ ldrh r0, [r0, #16]
+.L2934:
+ cmp r0, r1
+ add r2, r2, #1
+ beq .L2935
+ ldrb r1, [r10, #8] @ zero_extendqisi2
+ ldrb r3, [r10, #6] @ zero_extendqisi2
cmp r1, #1
- bne .L3009
+ str r3, [sp, #12]
+ bne .L2936
bl FtlGetLastWrittenPage
cmn r0, #1
mov r4, r0
- beq .L3010
- ldrb r3, [r5, #144] @ zero_extendqisi2
+ beq .L2937
+ ldrb r3, [r6, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L3147
- ldr r3, .L3161
- add r3, r3, r0, asl #1
- ldrh r6, [r3, #148]
- b .L3081
-.L3009:
+ addeq r3, r6, r0, lsl #1
+ ldrheq r5, [r3, #156]
+ beq .L2938
+.L3008:
+ mov r5, r4
+.L2938:
+ movw r3, #2324
+ mov r2, #0
+ ldrh r3, [r6, r3]
+ movw r8, #65535
+ mov r9, #36
+ str r3, [sp]
+ ldr r3, .L3087+4
+ ldr r0, [r3, #-536]
+ ldr lr, [r3, #-2692]
+ movw r3, #2402
+ ldrh r7, [r6, r3]
+ add r3, r10, #16
+ mov ip, r3
+ mov r6, r2
+ str r3, [sp, #20]
+.L2939:
+ ldr r1, [sp]
+ uxth r3, r2
+ cmp r1, r3
+ bhi .L2941
+ ldrb r3, [r10, #8] @ zero_extendqisi2
+ cmp r3, #1
+ movne r3, #0
+ bne .L3078
+ ldr r3, .L3087
+ ldrb r3, [r3, #152] @ zero_extendqisi2
+ adds r3, r3, #0
+ movne r3, #1
+.L3078:
+ ldr r7, .L3087+4
+ mov r1, r6
+ str r3, [sp, #24]
+ mov r8, #0
+ ldr r2, [sp, #24]
+ movw r9, #65535
+ bl FlashReadPages
+ ldr r3, [r7, #-3328]
+ mov fp, r7
+ str r3, [sp, #16]
+.L2943:
+ uxth r3, r8
+ cmp r6, r3
+ bhi .L2948
+ bne .L2946
+ add r4, r4, #1
+ uxth r3, r4
+ str r3, [sp]
+ ldr r3, [r7, #-536]
+ ldr r0, [r3, #4]
+.L3079:
+ ubfx r0, r0, #10, #16
+ bl P2V_plane
+ ldrb r2, [r10, #8] @ zero_extendqisi2
+ str r0, [sp, #4]
+ ldr r3, .L3087
+ cmp r2, #1
+ bne .L2950
+ ldrb r1, [r3, #152] @ zero_extendqisi2
+ cmp r1, #0
+ ldreq r1, [sp]
+ addeq r4, r3, r1, lsl #1
+ ldrheq r1, [r4, #156]
+ streq r1, [sp]
+.L2950:
+ movw r1, #2390
+ ldrh r3, [r3, r1]
+ ldr r1, [sp]
+ cmp r3, r1
+ ldmib sp, {r0, r1}
+ ldrheq r3, [sp]
+ strheq r3, [r10, #2] @ movhi
+ moveq r3, #0
+ strbeq r3, [r10, #6]
+ strheq r3, [r10, #4] @ movhi
+ ldrh r3, [sp, #12]
+ str r3, [sp, #28]
+ ldr ip, [sp, #28]
+ ldr r3, [sp]
+ cmp r3, r1
+ cmpeq r0, ip
+ moveq r2, r0
+ moveq r1, r3
+ beq .L3085
+ ldr r3, [sp, #16]
+ sub fp, r3, #1
+ movw r3, #65535
+ subs r9, r9, r3
+ movne r9, #1
+ cmp r2, #0
+ orreq r9, r9, #1
+ cmp r9, #0
+ beq .L2954
+ ldr r3, [r7, #-368]
+ uxth r8, r5
+ uxth r5, r5
+ cmn r3, #1
+ streq fp, [r7, #-368]
+ ldr r3, [r7, #-368]
+ mvn r7, #0
+ mov r6, r7
+ str r3, [sp, #12]
+ ldr r3, [sp, #8]
+ add r3, r3, #7
+ cmp r5, r3
+ subgt r4, r8, #7
+ ldrle r4, [sp, #8]
+ uxthgt r4, r4
+.L2957:
+ cmp r4, r8
+ ldr r3, .L3087+4
+ bhi .L2970
+ ldr r2, .L3087+8
+ mov ip, #36
+ ldr r0, [r3, #-536]
+ mov r3, #0
+ ldr r1, [sp, #20]
+ mov r5, r3
+ ldrh r9, [r2]
+ b .L2971
+.L2936:
mov r1, #0
bl FtlGetLastWrittenPage
cmn r0, #1
mov r4, r0
- beq .L3010
-.L3147:
- mov r6, r4
-.L3081:
- ldr r3, .L3161+4
- movw r8, #65535
- ldrh r2, [r3], #80
- str r2, [sp, #4]
- ldr r2, .L3161+8
- ldrh r7, [r3]
- add r3, r9, #14
- str r3, [sp, #20]
- ldr ip, [r2, #-536]
- mov r0, r3
- ldr lr, [r2, #-2692]
- mov r2, #0
- mov r5, r2
- mov r10, r2
- b .L3012
-.L3010:
+ bne .L3008
+.L2937:
mov r3, #0
- strh r3, [r9, #2] @ movhi
- strb r3, [r9, #6]
- b .L3144
-.L3014:
- ldrh r3, [r0, #2]!
+ strh r3, [r10, #2] @ movhi
+.L3084:
+ strb r3, [r10, #6]
+ b .L3073
+.L2941:
+ ldrh r3, [ip], #2
cmp r3, r8
- beq .L3013
- mov r1, #36
- orr r3, r6, r3, asl #10
- mla r1, r1, r5, ip
- stmib r1, {r3, r10}
- mul r3, r7, r5
- add r5, r5, #1
- uxth r5, r5
+ beq .L2940
+ mla r1, r9, r6, r0
+ orr r3, r5, r3, lsl #10
+ str r3, [r1, #4]
+ mov r3, #0
+ str r3, [r1, #8]
+ mul r3, r7, r6
+ add r6, r6, #1
+ uxth r6, r6
add fp, r3, #3
cmp r3, #0
movlt r3, fp
bic r3, r3, #3
add r3, lr, r3
str r3, [r1, #12]
-.L3013:
+.L2940:
add r2, r2, #1
-.L3012:
- ldr r1, [sp, #4]
- uxth r3, r2
- cmp r3, r1
- bcc .L3014
- ldrb r3, [r9, #8] @ zero_extendqisi2
- cmp r3, #1
- movne r3, #0
- bne .L3148
- ldr r3, .L3161
- ldrb lr, [r3, #144] @ zero_extendqisi2
- adds r3, lr, #0
- movne r3, #1
-.L3148:
- ldr r7, .L3161+8
- mov r1, r5
- str r3, [sp, #24]
- mov fp, #0
- ldr r2, [sp, #24]
- movw r10, #65535
- ldr r0, [r7, #-536]
- bl FlashReadPages
- ldr r3, [r7, #-3328]
- str r7, [sp, #12]
- str r3, [sp, #28]
-.L3016:
- uxth r8, fp
- cmp r8, r5
- bcs .L3023
- mov r1, #36
- ldr r0, [r7, #-536]
- mul r1, r1, fp
- add ip, r0, r1
- ldr r1, [r0, r1]
- cmp r1, #0
- bne .L3017
- ldr ip, [ip, #12]
- ldr r3, [ip, #4]
+ b .L2939
+.L2948:
+ mov r3, #36
+ ldr r1, [fp, #-536]
+ mul r3, r3, r8
+ add r2, r1, r3
+ ldr r3, [r1, r3]
+ cmp r3, #0
+ bne .L2944
+ ldr r2, [r2, #12]
+ ldr r3, [r2, #4]
cmn r3, #1
- beq .L3018
+ beq .L2945
+ ldr r1, [fp, #-3328]
mov r0, r3
- ldr r1, [r7, #-3328]
- str ip, [sp, #32]
- str r3, [sp, #4]
bl ftl_cmp_data_ver
- ldr r3, [sp, #4]
cmp r0, #0
- ldr ip, [sp, #32]
addne r3, r3, #1
- strne r3, [r7, #-3328]
-.L3018:
- ldr r1, [ip]
- cmn r1, #1
- bne .L3019
-.L3023:
- cmp r8, r5
- ldr r5, .L3161+8
- bne .L3145
- add fp, r4, #1
- uxth r3, fp
- str r3, [sp, #4]
- ldr r3, [r5, #-536]
- ldr r0, [r3, #4]
- b .L3149
-.L3017:
- ldr r1, [ip, #4]
- uxth r10, r6
- ldr r0, .L3161+12
- bl printk
- ldrh r1, [r9]
- ldr r3, .L3161+16
- strh r1, [r3] @ movhi
-.L3019:
- add fp, fp, #1
- b .L3016
-.L3145:
+ strne r3, [fp, #-3328]
+.L2945:
+ ldr r3, [r2]
+ cmn r3, #1
+ bne .L2947
+.L2946:
uxth r3, r4
- str r3, [sp, #4]
- ldr r3, [sp, #12]
+ uxth r8, r8
+ str r3, [sp]
mov r2, #36
- ldr r3, [r3, #-536]
+ ldr r3, [r7, #-536]
mla r8, r2, r8, r3
ldr r0, [r8, #4]
-.L3149:
- ubfx r0, r0, #10, #16
- bl P2V_plane
- ldr r2, .L3161
- str r0, [sp, #12]
- ldrb r0, [r9, #8] @ zero_extendqisi2
- cmp r0, #1
- bne .L3025
- ldrb r3, [r2, #144] @ zero_extendqisi2
- cmp r3, #0
- ldreq r3, [sp, #4]
- addeq fp, r2, r3, asl #1
- ldreqh r3, [fp, #148]
- streq r3, [sp, #4]
-.L3025:
- movw r3, #2388
- ldr r1, [sp, #12]
- ldrh r3, [r2, r3]
- ldr r2, [sp, #4]
- cmp r3, r2
- ldr r2, [sp, #8]
- ldreqh r3, [sp, #4]
- streqh r3, [r9, #2] @ movhi
- moveq r3, #0
- streqb r3, [r9, #6]
- streqh r3, [r9, #4] @ movhi
- ldrh r3, [sp, #16]
- str r3, [sp, #32]
- ldr ip, [sp, #32]
- ldr r3, [sp, #4]
- cmp r3, r2
- cmpeq r1, ip
- moveq r0, r9
- moveq r1, r3
- beq .L3154
- ldr r3, [sp, #28]
- movw r2, #65535
- sub fp, r3, #1
- clz r3, r0
- mov r3, r3, lsr #5
- cmp r10, r2
- orrne r3, r3, #1
- cmp r3, #0
- beq .L3029
- ldr r3, [r5, #-368]
- uxth r10, r6
- ldr r7, .L3161+8
- mvn r8, #0
- cmn r3, #1
- mov r6, r8
- ldreq r3, .L3161+8
- streq fp, [r3, #-368]
- ldr r3, [r5, #-368]
- str r3, [sp, #16]
- ldr r3, [sp, #8]
- add r3, r3, #7
- cmp r10, r3
- subgt r4, r10, #7
- ldrle r4, [sp, #8]
- uxthgt r4, r4
-.L3032:
- cmp r4, r10
- bhi .L3045
- ldr r3, .L3161+4
- mov r0, #36
- ldr lr, [r7, #-536]
- ldr r1, [sp, #20]
- ldrh r3, [r3]
- str r3, [sp, #28]
- mov r3, #0
- mov r5, r3
-.L3046:
- ldr ip, [sp, #28]
- uxth r2, r3
- cmp r2, ip
- bcs .L3157
- ldrh r2, [r1, #2]!
- movw ip, #65535
+ b .L3079
+.L2944:
+ ldr r1, [r2, #4]
+ uxth r9, r5
+ ldr r0, .L3087+12
+ bl printk
+ ldrh r3, [r10]
+ ldr r2, .L3087+16
+ strh r3, [r2] @ movhi
+.L2947:
+ add r8, r8, #1
+ b .L2943
+.L2959:
+ ldrh r2, [r1], #2
+ movw lr, #65535
add r3, r3, #1
- cmp r2, ip
- orrne r2, r4, r2, asl #10
- mlane ip, r0, r5, lr
+ cmp r2, lr
+ mlane lr, ip, r5, r0
addne r5, r5, #1
+ orrne r2, r4, r2, lsl #10
uxthne r5, r5
- strne r2, [ip, #4]
- b .L3046
-.L3157:
+ strne r2, [lr, #4]
+.L2971:
+ uxth r2, r3
+ cmp r2, r9
+ bcc .L2959
mov r1, r5
ldr r2, [sp, #24]
- ldr r0, [r7, #-536]
bl FlashReadPages
- ldr r3, .L3161
- mov r2, #36
+ ldr r3, .L3087
+ mov r1, #36
+ ldr r2, .L3087+4
+ ldr r0, .L3087+20
+ ldrb ip, [r3, #152] @ zero_extendqisi2
+ ldr r3, [r2, #-536]
+ add lr, r0, r4, lsl #1
+ mla r5, r1, r5, r3
movw r1, #65535
- ldrb ip, [r3, #144] @ zero_extendqisi2
- ldr r3, [r7, #-536]
- mla r5, r2, r5, r3
- ldr r2, .L3161+20
- add r2, r2, r4, asl #1
-.L3035:
- cmp r3, r5
- beq .L3158
+.L2960:
+ cmp r5, r3
+ addeq r4, r4, #1
+ uxtheq r4, r4
+ beq .L2957
+.L2969:
ldr r0, [r3]
cmp r0, #0
- bne .L3036
+ bne .L2961
ldr r0, [r3, #12]
- ldrh lr, [r0]
- cmp lr, r1
- beq .L3037
+ ldrh r9, [r0]
+ cmp r9, r1
+ beq .L2962
ldr r0, [r0, #4]
cmn r0, #1
- beq .L3037
- cmn r8, #1
- ldr r6, [r7, #-368]
- str r0, [r7, #-368]
- bne .L3037
- ldrh r0, [r2]
+ beq .L2962
+ cmn r7, #1
+ ldr r6, [r2, #-368]
+ str r0, [r2, #-368]
+ bne .L2962
+ ldrh r0, [lr]
cmp r0, r1
- bne .L3038
+ bne .L2963
cmp ip, #0
- beq .L3037
-.L3038:
- cmp r6, fp
- mvneq r8, #0
- movne r8, r6
- b .L3037
-.L3036:
- ldrh r1, [r9]
- movw r3, #1848
- ldr r2, .L3161+24
- strh r1, [r2, r3] @ movhi
- ldrb r3, [r9, #8] @ zero_extendqisi2
- cmp r3, #0
- bne .L3029
- ldr r2, .L3161+20
- mov r4, r4, asl #1
- ldr r3, .L3161+8
+ beq .L2962
+.L2963:
+ cmp fp, r6
+ movne r7, r6
+.L2962:
+ add r3, r3, #36
+ b .L2960
+.L2961:
+ ldrh r1, [r10]
+ movw r2, #1846
+ ldr r3, .L3087+4
+ strh r1, [r3, r2] @ movhi
+ ldrb r2, [r10, #8] @ zero_extendqisi2
+ cmp r2, #0
+ bne .L2954
+ ldr r2, .L3087+20
+ lsl r4, r4, #1
ldrh r1, [r2, r4]
movw r2, #65535
cmp r1, r2
- bne .L3040
- cmn r8, #1
- strne r8, [r3, #-368]
- bne .L3029
- ldr r2, [sp, #16]
- cmp r2, fp
- bne .L3150
+ bne .L2965
+ cmn r7, #1
+ strne r7, [r3, #-368]
+ bne .L2954
+ ldr r2, [sp, #12]
+ cmp fp, r2
+ beq .L2967
+.L3080:
+ str r2, [r3, #-368]
+ b .L2954
+.L2967:
ldr r2, [r3, #-368]
- b .L3155
-.L3040:
+.L3086:
+ sub r2, r2, #1
+ b .L3080
+.L2965:
cmp r6, fp
- beq .L3043
+ beq .L2968
cmn r6, #1
strne r6, [r3, #-368]
- b .L3029
-.L3043:
- ldr r2, [r3, #-368]
- cmp r2, fp
- beq .L3029
-.L3155:
- sub r2, r2, #1
- b .L3150
-.L3037:
- add r3, r3, #36
- b .L3035
-.L3158:
- add r4, r4, #1
- uxth r4, r4
- b .L3032
-.L3045:
- ldr r3, .L3161+8
- mvn r2, #0
-.L3150:
- str r2, [r3, #-368]
-.L3029:
- ldr r2, .L3161+24
- movw r3, #1850
- ldr r10, [sp, #8]
- mov r1, #1
- ldr r4, .L3161+8
- strh r1, [r2, r3] @ movhi
-.L3047:
- ldr r3, .L3161+4
- movw r1, #65535
- ldr r8, [r4, #-536]
- mov r0, #36
- ldr r6, [sp, #20]
- mov r5, #0
- ldrh r7, [r3]
- ldrb lr, [r3, #-2176] @ zero_extendqisi2
- str r5, [sp, #16]
-.L3048:
- uxth r3, r5
- cmp r3, r7
- bcs .L3159
- ldrh r3, [r6, #2]!
- cmp r3, r1
- beq .L3049
- ldr r2, [sp, #16]
- orr r3, r10, r3, asl #10
- mla r2, r0, r2, r8
- str r3, [r2, #4]
- ldrb ip, [r9, #8] @ zero_extendqisi2
- cmp ip, #1
- bne .L3050
- cmp lr, #0
- orrne r3, r3, #-2147483648
- strne r3, [r2, #4]
-.L3050:
- ldr r3, [sp, #16]
- add r3, r3, #1
- uxth r3, r3
- str r3, [sp, #16]
-.L3049:
- add r5, r5, #1
- b .L3048
-.L3159:
+.L2954:
+ ldr r9, [sp, #8]
+ mov r2, #1
+ ldr r4, .L3087+4
+ movw r3, #1848
+ strh r2, [r4, r3] @ movhi
+.L2972:
+ ldr r3, .L3087+8
+ movw r6, #65535
ldr r0, [r4, #-536]
- ldr r1, [sp, #16]
+ mov r7, #36
+ ldr r1, [sp, #20]
+ mov r2, #0
+ ldrh lr, [r3]
+ ldr r3, .L3087
+ str r2, [sp, #12]
+ ldrb r5, [r3, #152] @ zero_extendqisi2
+.L2973:
+ uxth r3, r2
+ cmp lr, r3
+ bhi .L2976
ldr r2, [sp, #24]
+ ldr r1, [sp, #12]
bl FlashReadPages
mov r3, #0
-.L3153:
- str r3, [sp, #28]
- ldr r2, [sp, #16]
- ldrh r3, [sp, #28]
- cmp r3, r2
- bcs .L3160
- ldr r3, [sp, #28]
- mov r5, #36
+.L3083:
+ str r3, [sp, #16]
+ ldr r2, [sp, #12]
+ ldrh r3, [sp, #16]
+ cmp r2, r3
+ bhi .L3002
+ ldrb r3, [r10, #8] @ zero_extendqisi2
+ add r9, r9, #1
+ uxth r9, r9
+ cmp r3, #1
+ bne .L3003
+ ldr r3, .L3087
+ ldrb r3, [r3, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L3003
+ ldr r3, .L3087+24
+ ldr r2, [sp]
+ ldrh r3, [r3]
+ cmp r3, r9
+ cmpeq r2, r9
+ beq .L2979
+.L3003:
+ ldr r3, .L3087+28
+ ldrh r3, [r3]
+ cmp r3, r9
+ bne .L2972
+ ldr r1, .L3087
+ movw r2, #2324
+ movw r0, #65535
+ mov r3, #0
+ strh r9, [r10, #2] @ movhi
+ ldrh r2, [r1, r2]
+ strh r3, [r10, #4] @ movhi
+.L3004:
+ uxth r1, r3
+ cmp r1, r2
+ bcs .L3073
+ ldr r1, [sp, #20]
+ ldrh ip, [r1], #2
+ cmp ip, r0
+ str r1, [sp, #20]
+ add r1, r3, #1
+ bne .L3084
+ mov r3, r1
+ b .L3004
+.L2968:
+ ldr r2, [r3, #-368]
+ cmp fp, r2
+ bne .L3086
+ b .L2954
+.L2970:
+ mvn r2, #0
+ b .L3080
+.L2976:
+ ldrh r3, [r1], #2
+ cmp r3, r6
+ beq .L2974
+ ldr ip, [sp, #12]
+ orr r3, r9, r3, lsl #10
+ mla ip, r7, ip, r0
+ str r3, [ip, #4]
+ ldrb r8, [r10, #8] @ zero_extendqisi2
+ cmp r8, #1
+ bne .L2975
+ cmp r5, #0
+ orrne r3, r3, #-2147483648
+ strne r3, [ip, #4]
+.L2975:
+ ldr r3, [sp, #12]
+ add r3, r3, #1
+ uxth r3, r3
+ str r3, [sp, #12]
+.L2974:
+ add r2, r2, #1
+ b .L2973
+.L3002:
+ ldr r3, [sp, #16]
+ mov r6, #36
ldr r8, [r4, #-536]
- mul r5, r5, r3
- add r7, r8, r5
- ldr r6, [r7, #4]
- ubfx r0, r6, #10, #16
- str r6, [sp, #60]
+ mul r6, r6, r3
+ add r7, r8, r6
+ ldr r5, [r7, #4]
+ ubfx r0, r5, #10, #16
+ str r5, [sp, #44]
bl P2V_plane
ldr r3, [sp, #8]
- cmp r10, r3
- bcc .L3053
- ldr r3, [sp, #32]
- ldr r2, [sp, #8]
- cmp r0, r3
- movcs r3, #0
- movcc r3, #1
- cmp r10, r2
+ cmp r9, r3
+ bcc .L2978
+ ldr r2, [sp, #28]
+ moveq r3, #1
movne r3, #0
+ cmp r2, r0
+ movls r3, #0
+ andhi r3, r3, #1
cmp r3, #0
- bne .L3053
- ldr r3, [sp, #12]
+ bne .L2978
+ ldr r3, [sp]
ldr r2, [sp, #4]
- cmp r0, r3
- cmpeq r10, r2
- beq .L3054
- ldr r3, [r8, r5]
+ cmp r9, r3
+ cmpeq r2, r0
+ beq .L2979
+ ldr r3, [r8, r6]
cmn r3, #1
- beq .L3055
- ldr r7, [r7, #12]
- movw r3, #61589
- ldrh r2, [r7]
- cmp r2, r3
- ldrneh r0, [r9]
- bne .L3151
- ldr fp, [r7, #4]
+ beq .L2980
+ ldr r3, [r7, #12]
+ movw r2, #61589
+ ldrh r1, [r3]
+ cmp r1, r2
+ ldrhne r0, [r10]
+ bne .L3081
+ ldr fp, [r3, #4]
cmn fp, #1
- beq .L3057
+ beq .L2982
ldr r1, [r4, #-3328]
mov r0, fp
bl ftl_cmp_data_ver
cmp r0, #0
- addne r3, fp, #1
- strne r3, [r4, #-3328]
-.L3057:
- ldr r6, [r7, #8]
- add r1, sp, #56
- ldr r3, [r7, #12]
+ addne r2, fp, #1
+ strne r2, [r4, #-3328]
+.L2982:
+ ldr r5, [r3, #8]
+ add r1, sp, #40
+ ldr r3, [r3, #12]
mov r2, #0
- mov r0, r6
- str r3, [sp, #52]
+ mov r0, r5
+ str r3, [sp, #36]
bl log2phys
ldr r1, [r4, #-368]
cmn r1, #1
- beq .L3058
+ beq .L2983
mov r0, fp
bl ftl_cmp_data_ver
cmp r0, #0
- beq .L3058
- ldr r3, [sp, #52]
+ beq .L2983
+ ldr r3, [sp, #36]
cmn r3, #1
- beq .L3059
+ beq .L2984
ldr r0, [r4, #-536]
mov r2, #0
mov r1, #1
- add r0, r0, r5
+ add r0, r0, r6
str r3, [r0, #4]
- ldr r8, [r0, #12]
- bl FlashReadPages
- ldr r2, [r4, #-536]
- ldr r3, [r8, #4]
- add ip, r2, r5
- str r3, [sp, #36]
- ldr r3, [r2, r5]
- cmn r3, #1
- bne .L3060
- b .L3061
-.L3059:
- ldr r3, [sp, #60]
- ldr r2, [sp, #56]
- cmp r2, r3
- bne .L3053
- mov r0, r6
- add r1, sp, #52
- mov r2, #1
- bl log2phys
- b .L3053
-.L3060:
- ldr r7, [r8, #8]
- cmp r7, r6
- bne .L3061
- ldr r0, [r4, #-368]
- ldr r1, [sp, #36]
- str r2, [sp, #44]
- str ip, [sp, #40]
- bl ftl_cmp_data_ver
- cmp r0, #0
- ldr ip, [sp, #40]
- ldr r2, [sp, #44]
- beq .L3061
- ldr r3, [sp, #56]
- ldr r1, [sp, #60]
- cmp r3, r1
- beq .L3066
- ldr r1, [sp, #52]
- cmp r3, r1
- beq .L3061
- cmn r3, #1
- streq r3, [r2, r5]
- beq .L3065
- str r3, [ip, #4]
- mov r0, ip
- mov r1, #1
- mov r2, #0
- ldr r8, [ip, #12]
- bl FlashReadPages
-.L3065:
- ldr r3, [r4, #-536]
- ldr r3, [r3, r5]
- cmn r3, #1
- beq .L3066
- ldr r5, [r8, #4]
- ldr r0, [r4, #-368]
- mov r1, r5
- bl ftl_cmp_data_ver
- cmp r0, #0
- beq .L3066
- ldr r0, [sp, #36]
- mov r1, r5
- bl ftl_cmp_data_ver
- cmp r0, #0
- beq .L3061
-.L3066:
- mov r0, r7
- ldr r1, [sp, #52]
- bl FtlReUsePrevPpa
-.L3061:
- mvn r3, #0
- str r3, [sp, #52]
- b .L3068
-.L3058:
- ldr r3, [sp, #60]
- ldr r2, [sp, #56]
- cmp r2, r3
- beq .L3068
- ldr r3, [sp, #52]
- cmn r3, #1
- beq .L3070
- ldr r2, .L3161
- ubfx r3, r3, #10, #21
- ldr r2, [r2, #2336]
- cmp r3, r2
- bcs .L3053
-.L3070:
- mov r0, r6
- add r1, sp, #60
- mov r2, #1
- bl log2phys
- ldr r5, [sp, #56]
- cmn r5, #1
- beq .L3068
- ldr r3, [sp, #52]
- cmp r5, r3
- beq .L3068
- ubfx r0, r5, #10, #16
- bl P2V_block_in_plane
- ldr r3, .L3161+28
- ldrh r2, [r3]
- cmp r2, r0
- beq .L3072
- ldrh r2, [r3, #48]
- cmp r2, r0
- beq .L3072
- ldrh r3, [r3, #96]
- cmp r3, r0
- bne .L3068
-.L3072:
- ldr r0, [r4, #-536]
- mov r1, #1
- mov r2, #0
- str r5, [r0, #4]
ldr r7, [r0, #12]
bl FlashReadPages
- ldr r3, [r4, #-536]
- ldr r1, [r7, #4]
- ldr r3, [r3]
- cmn r3, #1
- beq .L3068
- mov r0, fp
- bl ftl_cmp_data_ver
- cmp r0, #0
- bne .L3068
- mov r0, r6
- add r1, sp, #56
- mov r2, #1
- bl log2phys
-.L3068:
- ldr r0, [sp, #52]
- cmn r0, #1
- beq .L3053
- ubfx r0, r0, #10, #16
+ ldr r2, [r4, #-536]
+ ldr r1, [r2, r6]
+ add r3, r2, r6
+ cmn r1, #1
+ bne .L2985
+.L2986:
+ mvn r3, #0
+ str r3, [sp, #36]
+.L2993:
+ ldr r8, [sp, #36]
+ cmn r8, #1
+ beq .L2978
+.L3007:
+ ubfx r0, r8, #10, #16
bl P2V_block_in_plane
- ldr r2, [r4, #-3544]
- mov r3, r0, asl #1
+ ldr r2, [r4, #-3540]
+ lsl r3, r0, #1
mov r1, r0
ldrh r3, [r2, r3]
cmp r3, #0
- beq .L3073
-.L3151:
+ beq .L2999
+.L3081:
bl decrement_vpc_count
- b .L3053
-.L3073:
- ldr r0, .L3161+32
+ b .L2978
+.L2984:
+ ldr r3, [sp, #44]
+ ldr r2, [sp, #40]
+ cmp r2, r3
+ bne .L2978
+ mov r2, #1
+ add r1, sp, #36
+ mov r0, r5
+ bl log2phys
+.L2978:
+ ldr r3, [sp, #16]
+ add r3, r3, #1
+ b .L3083
+.L2985:
+ ldr r1, [r7, #8]
+ cmp r5, r1
+ bne .L2986
+ ldr r8, [r7, #4]
+ ldr r0, [r4, #-368]
+ mov r1, r8
+ bl ftl_cmp_data_ver
+ cmp r0, #0
+ beq .L2986
+ ldr r1, [sp, #40]
+ ldr r0, [sp, #44]
+ cmp r1, r0
+ bne .L2988
+.L2991:
+ ldr r1, [sp, #36]
+ mov r0, r5
+ bl FtlReUsePrevPpa
+ b .L2986
+.L2988:
+ ldr r0, [sp, #36]
+ cmp r1, r0
+ beq .L2986
+ cmn r1, #1
+ streq r1, [r2, r6]
+ beq .L2990
+ str r1, [r3, #4]
+ mov r2, #0
+ mov r1, #1
+ mov r0, r3
+ ldr r7, [r3, #12]
+ bl FlashReadPages
+.L2990:
+ ldr r3, [r4, #-536]
+ ldr r3, [r3, r6]
+ cmn r3, #1
+ beq .L2991
+ ldr r3, [r7, #4]
+ ldr r0, [r4, #-368]
+ mov r1, r3
+ bl ftl_cmp_data_ver
+ cmp r0, #0
+ beq .L2991
+ mov r1, r3
+ mov r0, r8
+ bl ftl_cmp_data_ver
+ cmp r0, #0
+ beq .L2986
+ b .L2991
+.L2983:
+ ldr r3, [sp, #44]
+ ldr r2, [sp, #40]
+ cmp r2, r3
+ beq .L2993
+ ldr r3, [sp, #36]
+ cmn r3, #1
+ beq .L2995
+ ldr r2, .L3087
+ ubfx r3, r3, #10, #21
+ ldr r2, [r2, #2340]
+ cmp r3, r2
+ bcs .L2978
+.L2995:
+ mov r2, #1
+ add r1, sp, #44
+ mov r0, r5
+ bl log2phys
+ ldr r8, [sp, #40]
+ cmn r8, #1
+ beq .L2993
+ ldr r3, [sp, #36]
+ cmp r8, r3
+ beq .L3007
+ ldr r6, .L3087+32
+ ubfx r0, r8, #10, #16
+ bl P2V_block_in_plane
+ ldrh r3, [r6]
+ cmp r3, r0
+ beq .L2998
+ add r2, r6, #48
+ ldrh r2, [r2]
+ cmp r2, r0
+ beq .L2998
+ add r3, r6, #96
+ ldrh r3, [r3]
+ cmp r3, r0
+ bne .L2993
+.L2998:
+ ldr r0, [r6, #2984]
+ mov r2, #0
+ mov r1, #1
+ str r8, [r0, #4]
+ ldr r7, [r0, #12]
+ bl FlashReadPages
+ ldr r3, [r6, #2984]
+ ldr r3, [r3]
+ cmn r3, #1
+ beq .L2993
+ ldr r1, [r7, #4]
+ mov r0, fp
+ bl ftl_cmp_data_ver
+ cmp r0, #0
+ bne .L2993
+ mov r2, #1
+ add r1, sp, #40
+ mov r0, r5
+ bl log2phys
+ b .L2993
+.L2999:
+ ldr r0, .L3087+36
bl printk
- b .L3053
-.L3055:
- ldrh r3, [r9]
- mov r1, r6
- ldr r2, .L3161+16
- ldr r0, .L3161+36
+ b .L2978
+.L2980:
+ ldrh r3, [r10]
+ mov r1, r5
+ ldr r2, .L3087+16
+ ldr r0, .L3087+40
strh r3, [r2] @ movhi
mov r2, fp
bl printk
- ldr r3, .L3161+24
- ldr r3, [r3, #1852]
+ ldr r3, [r4, #1852]
cmp r3, #31
- bhi .L3074
- ldr r2, .L3161+24
- ldr r1, [sp, #60]
- add r2, r2, r3, asl #2
- add r3, r3, #1
- str r1, [r2, #1856]
- ldr r2, .L3161+24
- str r3, [r2, #1852]
-.L3074:
- ldrh r0, [r9]
+ ldrls r1, [sp, #44]
+ addls r2, r4, r3, lsl #2
+ addls r3, r3, #1
+ strls r3, [r4, #1852]
+ strls r1, [r2, #1856]
+ ldrh r0, [r10]
bl decrement_vpc_count
ldr r3, [r4, #-368]
cmn r3, #1
- beq .L3152
- cmp r3, fp
- bls .L3053
-.L3152:
+ bne .L3001
+.L3082:
str fp, [r4, #-368]
-.L3053:
- ldr r3, [sp, #28]
- add r3, r3, #1
- b .L3153
-.L3160:
- ldrb r3, [r9, #8] @ zero_extendqisi2
- add r10, r10, #1
- cmp r3, #1
- uxth r10, r10
- bne .L3077
- ldr r3, .L3161
- ldrb r3, [r3, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L3077
- ldr r3, .L3161+40
- ldr r2, [sp, #4]
- ldrh r3, [r3]
- cmp r2, r10
- cmpeq r3, r10
- beq .L3054
-.L3077:
- ldr r2, .L3161+44
- ldrh r3, [r2]
- cmp r10, r3
- bne .L3047
- ldrh r1, [r2, #-68]
- movw r0, #65535
- mov r3, #0
- strh r10, [r9, #2] @ movhi
- strh r3, [r9, #4] @ movhi
-.L3078:
- uxth r2, r3
- cmp r2, r1
- bcs .L3144
- ldr lr, [sp, #20]
- add r3, r3, #1
- ldrh ip, [lr, #2]!
- cmp ip, r0
- str lr, [sp, #20]
- beq .L3078
- strb r2, [r9, #6]
- b .L3144
-.L3054:
- ldrb r3, [sp, #12] @ zero_extendqisi2
- mov r0, r9
- ldr r1, [sp, #4]
- strb r3, [r9, #6]
- ldrh r3, [sp, #4]
- strh r3, [r9, #2] @ movhi
-.L3154:
- ldr r2, [sp, #12]
+ b .L2978
+.L3001:
+ cmp fp, r3
+ bcs .L2978
+ b .L3082
+.L2979:
+ ldrb r3, [sp, #4] @ zero_extendqisi2
+ ldm sp, {r1, r2}
+ strb r3, [r10, #6]
+ ldrh r3, [sp]
+ strh r3, [r10, #2] @ movhi
+.L3085:
+ mov r0, r10
bl ftl_sb_update_avl_pages
-.L3144:
+ b .L3073
+.L3075:
mov r0, #0
- add sp, sp, #68
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3162:
+ bx lr
+.L3088:
.align 2
-.L3161:
+.L3087:
.word .LANCHOR0
- .word .LANCHOR0+2320
.word .LANCHOR2
+ .word .LANCHOR0+2324
.word .LC149
- .word .LANCHOR4+1848
+ .word .LANCHOR2+1846
.word .LANCHOR2-2620
- .word .LANCHOR4
- .word .LANCHOR2-3524
+ .word .LANCHOR0+2392
+ .word .LANCHOR0+2390
+ .word .LANCHOR2-3520
.word .LC150
.word .LC151
- .word .LANCHOR0+2390
- .word .LANCHOR0+2388
.fnend
.size FtlRecoverySuperblock, .-FtlRecoverySuperblock
.align 2
.global FtlVpcCheckAndModify
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlVpcCheckAndModify, %function
FtlVpcCheckAndModify:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r0, r1, r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
.pad #8
- mov r4, #0
- ldr r5, .L3180
- ldr r1, .L3180+4
- ldr r0, .L3180+8
+ mov r5, #0
+ ldr r6, .L3104
+ ldr r1, .L3104+4
+ ldr r0, .L3104+8
bl printk
- movw r3, #2330
- ldrh r2, [r5, r3]
+ movw r3, #2334
+ ldr r4, .L3104+12
+ ldrh r2, [r6, r3]
mov r1, #0
- ldr r6, .L3180+12
- mov r2, r2, asl #1
- ldr r0, [r6, #-476]
+ ldr r0, [r4, #-476]
+ lsl r2, r2, #1
bl ftl_memset
-.L3164:
- ldr r3, [r5, #2448]
- cmp r4, r3
- bcs .L3178
- mov r0, r4
- add r1, sp, #4
- mov r2, #0
- bl log2phys
- ldr r0, [sp, #4]
- cmn r0, #1
- beq .L3165
- ubfx r0, r0, #10, #16
- bl P2V_block_in_plane
- ldr r2, [r6, #-476]
- mov r0, r0, asl #1
- ldrh r3, [r2, r0]
- add r3, r3, #1
- strh r3, [r2, r0] @ movhi
-.L3165:
- add r4, r4, #1
- b .L3164
-.L3178:
- ldr r8, .L3180+16
+.L3090:
+ ldr r3, [r6, #2452]
+ cmp r5, r3
+ bcc .L3092
+ ldr r8, .L3104+16
mov r7, #0
- ldr r10, .L3180+12
- ldr r9, .L3180+20
-.L3167:
- ldrh r3, [r8]
- uxth r4, r7
- cmp r3, r4
- bls .L3179
- ldr r3, [r6, #-3544]
- mov r5, r4, asl #1
- movw r1, #65535
- ldrh r2, [r3, r5]
- ldr r3, [r6, #-476]
- ldrh r3, [r3, r5]
- cmp r2, r1
- cmpne r2, r3
- beq .L3168
- ldrh r1, [r9]
- cmp r1, r4
- beq .L3168
- ldr r1, .L3180+24
- ldrh r0, [r1]
- cmp r0, r4
- beq .L3168
- ldrh r1, [r1, #-48]
- cmp r1, r4
- beq .L3168
- ldr r0, .L3180+28
- mov r1, r4
- bl printk
- ldr r3, [r10, #-3544]
- ldrh r2, [r3, r5]
- cmp r2, #0
- ldr r2, [r10, #-476]
- ldrh r2, [r2, r5]
- strh r2, [r3, r5] @ movhi
- beq .L3168
- mov r0, r4
- bl update_vpc_list
-.L3168:
- add r7, r7, #1
- b .L3167
-.L3179:
+ ldr r9, .L3104+20
+ add r10, r8, #96
+.L3093:
+ ldrh r3, [r9]
+ uxth r6, r7
+ cmp r3, r6
+ bhi .L3096
bl l2p_flush
bl FtlVpcTblFlush
add sp, sp, #8
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L3181:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3092:
+ mov r2, #0
+ add r1, sp, #4
+ mov r0, r5
+ bl log2phys
+ ldr r0, [sp, #4]
+ cmn r0, #1
+ beq .L3091
+ ubfx r0, r0, #10, #16
+ bl P2V_block_in_plane
+ ldr r2, [r4, #-476]
+ lsl r0, r0, #1
+ ldrh r3, [r2, r0]
+ add r3, r3, #1
+ strh r3, [r2, r0] @ movhi
+.L3091:
+ add r5, r5, #1
+ b .L3090
+.L3096:
+ uxth r1, r7
+ ldr r3, [r4, #-3540]
+ movw r0, #65535
+ lsl r5, r1, #1
+ ldrh r2, [r3, r5]
+ ldr r3, [r4, #-476]
+ ldrh r3, [r3, r5]
+ cmp r2, r0
+ cmpne r2, r3
+ beq .L3094
+ ldrh r0, [r8]
+ cmp r0, r6
+ beq .L3094
+ ldrh r0, [r10]
+ cmp r0, r6
+ beq .L3094
+ ldr r0, .L3104+24
+ ldrh r0, [r0]
+ cmp r0, r6
+ beq .L3094
+ ldr r0, .L3104+28
+ bl printk
+ ldr r3, [r4, #-3540]
+ ldrh r2, [r3, r5]
+ cmp r2, #0
+ ldr r2, [r4, #-476]
+ ldrh r2, [r2, r5]
+ strh r2, [r3, r5] @ movhi
+ bne .L3095
+.L3094:
+ add r7, r7, #1
+ b .L3093
+.L3095:
+ mov r0, r6
+ bl update_vpc_list
+ b .L3094
+.L3105:
.align 2
-.L3180:
+.L3104:
.word .LANCHOR0
- .word .LANCHOR3+216
+ .word .LANCHOR3+203
.word .LC110
.word .LANCHOR2
- .word .LANCHOR0+2328
- .word .LANCHOR2-3524
- .word .LANCHOR2-3428
+ .word .LANCHOR2-3520
+ .word .LANCHOR0+2332
+ .word .LANCHOR2-3472
.word .LC152
.fnend
.size FtlVpcCheckAndModify, .-FtlVpcCheckAndModify
.align 2
.global FtlGcScanTempBlk
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcScanTempBlk, %function
FtlGcScanTempBlk:
.fnstart
@ args = 0, pretend = 0, frame = 64
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r2, .L3235
- movw r3, #3448
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r2, .L3154
+ movw r3, #3444
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #68
sub sp, sp, #68
- ldrh r5, [r2, r3]
- movw r3, #65535
mov r4, r0
str r1, [sp, #12]
- cmp r5, r3
- beq .L3216
- cmp r5, #0
- bne .L3183
- b .L3184
-.L3216:
- mov r5, #0
-.L3183:
- ldr r2, .L3235+4
- movw r3, #2388
+ ldrh r6, [r2, r3]
+ movw r3, #65535
+ cmp r6, r3
+ beq .L3138
+ cmp r6, #0
+ bne .L3107
+.L3108:
+ bl FtlGcPageVarInit
+ b .L3109
+.L3138:
+ mov r6, #0
+.L3107:
+ ldr r2, .L3154+4
+ movw r3, #2390
ldrh r3, [r2, r3]
ldr r2, [sp, #12]
- cmp r2, r3
- bne .L3185
-.L3184:
- bl FtlGcPageVarInit
-.L3185:
- ldr r6, .L3235+8
+ cmp r3, r2
+ beq .L3108
+.L3109:
+ ldr r5, .L3154+8
mvn r3, #0
str r3, [sp, #8]
mov r3, #0
str r3, [sp]
-.L3186:
+.L3110:
ldrh r1, [r4]
movw r3, #65535
mov r2, #0
strb r2, [r4, #8]
cmp r1, r3
- beq .L3187
-.L3188:
-.L3213:
- ldr r3, .L3235+12
- mov r7, #0
- ldr ip, [r6, #-2692]
- add r1, r4, #14
- mov r8, r7
+ beq .L3111
+.L3135:
+ ldr r3, .L3154+12
+ add ip, r4, #16
+ ldr r0, [r5, #-536]
movw r9, #65535
- ldrh r3, [r3]
+ ldr lr, [r5, #-2692]
mov r10, #36
+ ldrh r3, [r3]
str r3, [sp, #4]
- ldr r3, [r6, #-536]
+ ldr r3, [r5, #-2696]
str r3, [sp, #16]
- ldr r3, [r6, #-2696]
- str r3, [sp, #20]
- ldr r3, .L3235+16
- ldrh r0, [r3]
- ldrh lr, [r3, #2]
-.L3189:
- ldr r2, [sp, #4]
- uxth r3, r7
+ ldr r3, .L3154+16
+ ldrh r2, [r3]
+ ldrh r8, [r3, #2]
+ str r2, [sp, #20]
+ mov r2, #0
+ mov r7, r2
+.L3112:
+ ldr r1, [sp, #4]
+ uxth r3, r2
+ cmp r1, r3
+ bhi .L3114
+ ldr r10, .L3154+4
+ mov fp, #0
+ mov r2, #0
+ mov r1, r7
+ bl FlashReadPages
+.L3115:
+ uxth r3, fp
+ cmp r7, r3
+ bhi .L3133
+ ldr r3, [sp]
+ add r6, r6, #1
+ uxth r6, r6
+ add r3, r3, #1
+ str r3, [sp]
+ ldr r2, [sp]
+ ldr r3, [sp, #12]
cmp r3, r2
- bcs .L3233
- ldrh r3, [r1, #2]!
+ ldr r2, .L3154+20
+ bls .L3134
+.L3136:
+ ldrh r3, [r2]
+ cmp r3, r6
+ bhi .L3135
+ mov r2, #0
+ b .L3111
+.L3114:
+ ldrh r3, [ip], #2
cmp r3, r9
- beq .L3190
- ldr r2, [sp, #16]
- orr r3, r5, r3, asl #10
- mla r2, r10, r8, r2
- str r3, [r2, #4]
- mul r3, r0, r8
+ beq .L3113
+ mla r1, r10, r7, r0
+ orr r3, r6, r3, lsl #10
+ str r3, [r1, #4]
+ ldr r3, [sp, #20]
+ mul r3, r3, r7
add fp, r3, #3
cmp r3, #0
movlt r3, fp
- ldr fp, [sp, #20]
+ ldr fp, [sp, #16]
bic r3, r3, #3
add r3, fp, r3
- str r3, [r2, #8]
- mul r3, lr, r8
- add r8, r8, #1
- uxth r8, r8
+ str r3, [r1, #8]
+ mul r3, r8, r7
+ add r7, r7, #1
+ uxth r7, r7
add fp, r3, #3
cmp r3, #0
movlt r3, fp
bic r3, r3, #3
- add r3, ip, r3
- str r3, [r2, #12]
-.L3190:
- add r7, r7, #1
- b .L3189
-.L3233:
- ldr r0, [r6, #-536]
- mov r1, r8
- mov r2, #0
- mov fp, #0
- bl FlashReadPages
-.L3192:
- uxth r3, fp
- cmp r3, r8
- bcs .L3234
- ldr r3, .L3235+8
+ add r3, lr, r3
+ str r3, [r1, #12]
+.L3113:
+ add r2, r2, #1
+ b .L3112
+.L3133:
mov r9, #36
+ ldr r8, [r5, #-536]
mul r9, r9, fp
- ldr r7, [r3, #-536]
- add r10, r7, r9
- ldr r3, [r10, #4]
- ubfx r0, r3, #10, #16
- str r3, [sp, #4]
+ add r3, r8, r9
+ ldr r2, [r3, #4]
+ str r3, [sp, #16]
+ ubfx r0, r2, #10, #16
+ str r2, [sp, #4]
bl P2V_plane
- ldr r7, [r7, r9]
- ldr r10, [r10, #12]
- cmp r7, #0
- ldr ip, .L3235+4
- ldr r3, .L3235+8
+ ldr r8, [r8, r9]
mov r2, r0
- bne .L3193
- ldrh r0, [r10]
+ ldr r3, [sp, #16]
+ cmp r8, #0
+ ldr r3, [r3, #12]
+ bne .L3116
+ ldrh r0, [r3]
movw r1, #65535
cmp r0, r1
- bne .L3194
-.L3197:
- ldrb r1, [ip, #144] @ zero_extendqisi2
+ bne .L3117
+.L3120:
+ ldrb r1, [r10, #152] @ zero_extendqisi2
cmp r1, #0
- beq .L3228
- mov r1, #1
- str r1, [r3, #-372]
- b .L3187
-.L3194:
- ldr r1, .L3235+4
- ldr r0, [r10, #8]
- ldr r1, [r1, #2448]
+ beq .L3150
+ mov r3, #1
+ str r3, [r5, #-372]
+.L3111:
+ ldr r1, .L3154
+ mvn r0, #0
+ movw r3, #3444
+ strh r6, [r4, #2] @ movhi
+ strb r2, [r4, #6]
+ strh r0, [r1, r3] @ movhi
+ mov r1, r6
+ mov r0, r4
+ bl ftl_sb_update_avl_pages
+ b .L3106
+.L3117:
+ ldr r0, [r3, #8]
+ ldr r1, [r10, #2452]
cmp r0, r1
- bls .L3229
- b .L3197
-.L3228:
+ bhi .L3120
+ ldrb r2, [r10, #36] @ zero_extendqisi2
+ cmp r2, #0
+ bne .L3123
+.L3124:
+ ldr r2, [r3, #8]
+ add fp, fp, #1
+ ldr r1, [sp, #4]
+ ldr r0, [r3, #12]
+ bl FtlGcUpdatePage
+ b .L3115
+.L3150:
ldrh r3, [r4]
- ldr r2, .L3235+8
- mov r3, r3, asl #1
- ldr r2, [r2, #-3544]
- b .L3232
-.L3229:
- ldr r3, .L3235+4
- ldrb r3, [r3] @ zero_extendqisi2
- cmp r3, #0
- beq .L3201
- add r1, sp, #24
- mov r2, r7
- bl log2phys
- ldr r3, [r10, #12]
- ldr r2, [sp, #24]
- rsb r1, r3, r2
- cmn r2, #1
- clz r1, r1
- mov r1, r1, lsr #5
- moveq r1, #0
- cmp r1, #0
- beq .L3201
- str r3, [sp, #32]
- mov r2, r7
- ldr r3, [r6, #-504]
- add r0, sp, #28
- mov r1, #1
- str r3, [sp, #36]
- ldr r3, [r6, #-496]
- str r3, [sp, #40]
- bl FlashReadPages
- ldr r3, .L3235+20
- ldr r2, [r6, #-536]
- ldrh r3, [r3]
- add r9, r2, r9
- mov r3, r3, asl #7
- ldr r2, [sp, #36]
- b .L3203
-.L3204:
- add r7, r7, #1
-.L3203:
- cmp r7, r3
- beq .L3201
- ldr r1, [r9, #8]
- ldr r0, [r1, r7, asl #2]
- ldr r1, [r2, r7, asl #2]
- cmp r0, r1
- beq .L3204
- ldrh r1, [r4]
- ldr r2, [sp, #32]
- ldr r0, .L3235+24
- bl printk
- ldrh r3, [r4]
- ldr r2, [r6, #-3544]
- mov r1, #0
- mov r3, r3, asl #1
-.L3232:
+ ldr r2, [r5, #-3540]
+ lsl r3, r3, #1
strh r1, [r2, r3] @ movhi
ldrh r0, [r4]
bl INSERT_FREE_LIST
- ldr r2, .L3235+28
+ ldr r2, .L3154+24
mvn r3, #0
strh r3, [r4] @ movhi
strh r3, [r2] @ movhi
- b .L3231
-.L3201:
- ldr r0, [r10, #12]
- add fp, fp, #1
- ldr r1, [sp, #4]
- ldr r2, [r10, #8]
- bl FtlGcUpdatePage
- b .L3192
-.L3193:
- ldr r2, [sp, #4]
- ldr r0, .L3235+32
+.L3153:
+ bl FtlGcPageVarInit
+ mov r6, #0
+ b .L3110
+.L3123:
+ mov r2, r8
+ add r1, sp, #24
+ str r3, [sp, #16]
+ bl log2phys
+ ldr r3, [sp, #16]
+ ldr r1, [sp, #24]
+ ldr r2, [r3, #12]
+ cmn r1, #1
+ sub r0, r2, r1
+ clz r0, r0
+ lsr r0, r0, #5
+ moveq r0, #0
+ cmp r0, #0
+ beq .L3124
+ str r2, [sp, #32]
+ mov r1, #1
+ ldr r2, [r5, #-504]
+ add r0, sp, #28
+ str r2, [sp, #36]
+ ldr r2, [r5, #-496]
+ str r2, [sp, #40]
+ mov r2, r8
+ bl FlashReadPages
+ ldr r2, .L3154+28
+ ldr r1, [r5, #-536]
+ ldr r3, [sp, #16]
+ ldrh r2, [r2]
+ add r9, r1, r9
+ ldr r1, [sp, #36]
+ lsl r2, r2, #7
+.L3125:
+ cmp r8, r2
+ beq .L3124
+ ldr r0, [r9, #8]
+ ldr ip, [r0, r8, lsl #2]
+ ldr r0, [r1, r8, lsl #2]
+ cmp ip, r0
+ beq .L3126
+ ldr r2, [sp, #32]
ldrh r1, [r4]
- str r3, [sp, #20]
- str ip, [sp, #16]
+ ldr r0, .L3154+32
bl printk
- ldrh r5, [r4]
- ldr ip, [sp, #16]
- ldr r3, [sp, #20]
- ldr r2, [ip, #2244]
+ ldrh r3, [r4]
+ mov r1, #0
+ ldr r2, [r5, #-3540]
+ lsl r3, r3, #1
+ strh r1, [r2, r3] @ movhi
+ ldrh r0, [r4]
+ bl INSERT_FREE_LIST
+ ldr r2, .L3154+36
+ mvn r3, #0
+ strh r3, [r4] @ movhi
+ strh r3, [r2, #-4] @ movhi
+ b .L3153
+.L3126:
+ add r8, r8, #1
+ b .L3125
+.L3116:
+ ldr r2, [sp, #4]
+ ldrh r1, [r4]
+ ldr r0, .L3154+40
+ bl printk
+ ldr r3, [r10, #2248]
+ cmp r3, #0
+ ldrh r3, [r4]
+ bne .L3129
+ ldrb r2, [r10, #152] @ zero_extendqisi2
cmp r2, #0
- bne .L3207
- ldrb r2, [ip, #144] @ zero_extendqisi2
- cmp r2, #0
- beq .L3208
-.L3207:
- ldr r1, [r3, #-3608]
- mov r2, r5, asl #1
+ beq .L3130
+.L3129:
+ ldr r1, [r5, #-3604]
+ lsl r2, r3, #1
ldrh r2, [r1, r2]
cmp r2, #159
- bls .L3209
-.L3208:
- ldr r2, [r3, #-536]
+ bls .L3131
+.L3130:
+ ldr r2, [r5, #-536]
ldr r2, [r2, r9]
cmn r2, #1
- bne .L3210
-.L3209:
- ldr r3, [r3, #-536]
- add r9, r3, r9
- ldr r3, [r9, #4]
- str r3, [sp, #8]
-.L3210:
- ldr r3, .L3235+8
- mov r5, r5, asl #1
- mov r2, #0
- ldr r3, [r3, #-3544]
- strh r2, [r3, r5] @ movhi
+ bne .L3132
+.L3131:
+ ldr r2, [r5, #-536]
+ add r9, r2, r9
+ ldr r2, [r9, #4]
+ str r2, [sp, #8]
+.L3132:
+ ldr r2, [r5, #-3540]
+ lsl r3, r3, #1
+ mov r1, #0
+ strh r1, [r2, r3] @ movhi
ldrh r0, [r4]
bl INSERT_FREE_LIST
mvn r3, #0
strh r3, [r4] @ movhi
-.L3231:
- bl FtlGcPageVarInit
- mov r5, #0
- b .L3186
-.L3234:
- ldr r3, [sp]
- add r5, r5, #1
- ldr r2, [sp, #12]
- add r3, r3, #1
- uxth r5, r5
- cmp r3, r2
- str r3, [sp]
- ldr r2, .L3235+36
- bcs .L3212
-.L3214:
- ldrh r3, [r2]
- cmp r3, r5
- bhi .L3213
- mov r2, #0
- b .L3187
-.L3212:
- ldr r1, .L3235+40
+ b .L3153
+.L3134:
+ ldr r1, .L3154+44
movw r0, #65535
ldrh r3, [r1]
cmp r3, r0
- beq .L3214
+ beq .L3136
ldr r0, [sp]
add r3, r3, r0
strh r3, [r1] @ movhi
ldrh r3, [r2]
- cmp r3, r5
- bls .L3214
- b .L3215
-.L3187:
- ldr r1, .L3235
- movw r3, #3448
- mvn r0, #0
- strh r5, [r4, #2] @ movhi
- strb r2, [r4, #6]
- strh r0, [r1, r3] @ movhi
- mov r0, r4
- mov r1, r5
- bl ftl_sb_update_avl_pages
-.L3215:
+ cmp r3, r6
+ bls .L3136
+.L3106:
ldr r0, [sp, #8]
add sp, sp, #68
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3236:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3155:
.align 2
-.L3235:
+.L3154:
.word .LANCHOR1
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2320
- .word .LANCHOR0+2398
- .word .LANCHOR0+2394
- .word .LC153
+ .word .LANCHOR0+2324
+ .word .LANCHOR0+2400
+ .word .LANCHOR0+2390
.word .LANCHOR2-3284
+ .word .LANCHOR0+2396
+ .word .LC153
+ .word .LANCHOR2-3280
.word .LC154
- .word .LANCHOR0+2388
- .word .LANCHOR1+3448
+ .word .LANCHOR1+3444
.fnend
.size FtlGcScanTempBlk, .-FtlGcScanTempBlk
.align 2
.global FtlReadRefresh
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlReadRefresh, %function
FtlReadRefresh:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
.pad #40
sub sp, sp, #40
- ldr r5, .L3254
- ldr r4, .L3254+4
- ldr r9, [r5, #-3152]
+ ldr r5, .L3173
+ ldr r9, [r5, #-3156]
mov r6, r5
cmp r9, #0
- beq .L3238
- ldr r2, [r5, #-3148]
- ldr r3, [r4, #2448]
- cmp r2, r3
- bcs .L3239
+ beq .L3157
+ ldr r3, .L3173+4
+ ldr r1, [r5, #-3152]
+ ldr r2, [r3, #2452]
+ mov r4, r3
+ cmp r1, r2
+ bcs .L3158
mov r5, #2048
- mov r7, r6
-.L3244:
- ldr r0, [r6, #-3148]
- ldr r3, [r4, #2448]
+.L3163:
+ ldr r0, [r6, #-3152]
+ ldr r3, [r4, #2452]
cmp r0, r3
- bcs .L3243
+ bcc .L3159
+.L3162:
+ mvn r0, #0
+.L3156:
+ add sp, sp, #40
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3159:
mov r2, #0
mov r1, sp
bl log2phys
- ldr r3, [r7, #-3148]
- add r3, r3, #1
- str r3, [r7, #-3148]
ldr r2, [sp]
+ ldr r3, [r6, #-3152]
cmn r2, #1
- beq .L3242
- add r0, sp, #40
+ add r3, r3, #1
+ str r3, [r6, #-3152]
+ beq .L3161
str r2, [sp, #8]
- mov r1, #1
+ add r0, sp, #40
mov r2, #0
+ mov r1, #1
str r2, [r0, #-36]!
str r3, [sp, #20]
str r2, [sp, #12]
@@ -19210,357 +19723,352 @@
bl FlashReadPages
ldr r3, [sp, #4]
cmp r3, #256
- bne .L3243
+ bne .L3162
ldr r0, [sp]
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
bl FtlGcRefreshBlock
-.L3243:
- mvn r0, #0
- b .L3246
-.L3242:
+ b .L3162
+.L3161:
subs r5, r5, #1
- bne .L3244
- b .L3243
-.L3239:
+ bne .L3163
+ b .L3162
+.L3158:
ldr r3, [r5, #-3364]
mov r0, #0
+ str r0, [r5, #-3156]
str r0, [r5, #-3152]
- str r0, [r5, #-3148]
- str r3, [r5, #-3156]
- b .L3246
-.L3238:
+ str r3, [r5, #-3160]
+ b .L3156
+.L3157:
ldr r1, [r5, #-3312]
- sub r10, r5, #3600
- ldr r8, [r5, #-3364]
- ldr r3, [r4, #2448]
movw r4, #10000
- ldr r7, [r5, #-3156]
+ ldr r8, [r5, #-3364]
+ sub r10, r5, #3584
+ ldr r7, [r5, #-3160]
cmp r1, r4
- add r2, r8, #1048576
+ add r3, r8, #1048576
movhi r4, #31
movls r4, #63
- cmp r7, r2
- bhi .L3248
- mov r1, r1, lsr #10
+ cmp r7, r3
+ bhi .L3167
+ ldr r3, .L3173+4
+ lsr r1, r1, #10
mov r0, #1000
- mul r0, r0, r3
add r1, r1, #1
+ ldr r3, [r3, #2452]
+ mul r0, r0, r3
bl __aeabi_uidiv
add r0, r0, r7
- cmp r0, r8
- bcc .L3248
- ldrh r3, [r10, #28]
+ cmp r8, r0
+ bhi .L3167
+ ldrh r3, [r10, #16]
ands r0, r4, r3
movne r0, r9
- bne .L3246
- ldr r2, [r5, #-3132]
- cmp r2, r3
- beq .L3246
-.L3248:
- ldrh r3, [r10, #28]
+ bne .L3156
+ ldr r2, [r5, #-3136]
+ cmp r3, r2
+ beq .L3156
+.L3167:
+ ldrh r3, [r10, #16]
mov r0, #0
- str r8, [r6, #-3156]
- str r0, [r6, #-3148]
- str r3, [r6, #-3132]
+ str r0, [r6, #-3152]
+ str r8, [r6, #-3160]
+ str r3, [r6, #-3136]
mov r3, #1
- str r3, [r6, #-3152]
-.L3246:
- add sp, sp, #40
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L3255:
+ str r3, [r6, #-3156]
+ b .L3156
+.L3174:
.align 2
-.L3254:
+.L3173:
.word .LANCHOR2
.word .LANCHOR0
.fnend
.size FtlReadRefresh, .-FtlReadRefresh
.align 2
.global FtlGcFreeTempBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcFreeTempBlock, %function
FtlGcFreeTempBlock:
.fnstart
- @ args = 0, pretend = 0, frame = 24
+ @ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2388
- ldr r4, .L3295
- .pad #28
- sub sp, sp, #28
- ldr r6, .L3295+4
- ldr ip, [r4, #-3616]
+ movw r3, #2390
+ ldr r4, .L3213
+ .pad #20
+ sub sp, sp, #20
+ ldr r6, .L3213+4
+ ldr ip, [r4, #-3612]
ldrh r1, [r6, r3]
cmp ip, #0
- bne .L3293
- sub r7, r4, #3424
+ beq .L3176
+.L3212:
+ mov r0, #0
+.L3175:
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3176:
+ sub r5, r4, #3424
movw lr, #65535
- ldrh r5, [r7, #-4]
- cmp r5, lr
- bne .L3259
-.L3268:
- ldrh r2, [r7, #-4]
+ ldrh r7, [r5]
+ cmp r7, lr
+ bne .L3178
+.L3187:
+ ldrh r2, [r5]
movw r3, #65535
- ldr r5, .L3295
- mov r8, #0
+ mov r7, #0
+ str r7, [r4, #-372]
cmp r2, r3
- str r8, [r4, #-372]
- sub r9, r5, #3424
- beq .L3293
+ beq .L3212
bl FtlCacheWriteBack
- movw r2, #2388
- ldrb r0, [r5, #-3421] @ zero_extendqisi2
- ldrh r2, [r6, r2]
- ldrh r3, [r9, #-4]
- ldr r1, [r5, #-3544]
- smulbb r2, r0, r2
- mov r3, r3, asl #1
+ movw r0, #2390
+ ldrb r2, [r4, #-3417] @ zero_extendqisi2
+ ldrh r0, [r6, r0]
+ mov fp, #12
+ ldrh r3, [r5]
+ ldr r1, [r4, #-3540]
+ ldr r8, .L3213+8
+ smulbb r2, r2, r0
+ lsl r3, r3, #1
strh r2, [r1, r3] @ movhi
- sub r2, r5, #2656
- ldr r3, [r5, #-3344]
- sub fp, r2, #12
- ldrh ip, [r2, #-12]
- sub r10, r2, #772
- add r3, ip, r3
- str r3, [r5, #-3344]
- stmib sp, {r2, r5}
- b .L3269
-.L3259:
+ ldr r2, [r4, #-3344]
+ ldrh r3, [r8, #-12]
+ add r3, r3, r2
+ str r3, [r4, #-3344]
+.L3188:
+ ldrh r2, [r8, #-12]
+ uxth r3, r7
+ cmp r2, r3
+ bhi .L3192
+ movw r0, #65535
+ bl decrement_vpc_count
+ ldrb r3, [r6, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L3193
+ ldrh r1, [r5]
+ ldr r0, .L3213+12
+ bl printk
+.L3193:
+ ldrh r0, [r5]
+ ldr r2, [r4, #-3540]
+ lsl r3, r0, #1
+ ldrh r3, [r2, r3]
+ cmp r3, #0
+ beq .L3194
+ bl INSERT_DATA_LIST
+.L3195:
+ ldr r7, .L3213+16
+ mvn r9, #0
+ strh r9, [r5] @ movhi
+ mov r5, #0
+ strh r5, [r8, #-12] @ movhi
+ strh r5, [r7, #-4] @ movhi
+ bl l2p_flush
+ bl FtlVpcTblFlush
+ sub r3, r7, #608
+ sub r2, r7, #848
+ strh r9, [r3, #-4] @ movhi
+ ldr r3, [r6, #2248]
+ ldrh r2, [r2, #-4]
+ cmp r3, r5
+ sub r3, r7, #624
+ ldrh r3, [r3, #-8]
+ beq .L3196
+ ldr r1, [r4, #-3308]
+ cmp r1, #39
+ bhi .L3196
+ cmp r2, r3
+ lslcc r3, r3, #1
+ strhcc r3, [r7, #-48] @ movhi
+ b .L3212
+.L3178:
cmp r0, #0
- beq .L3262
- ldr r2, .L3295+8
- movw r3, #3448
+ beq .L3181
+ ldr r2, .L3213+20
+ movw r3, #3444
ldrh r0, [r2, r3]
cmp r0, lr
- beq .L3263
-.L3264:
+ beq .L3182
+.L3183:
mov r1, #2
- b .L3262
-.L3263:
- strh ip, [r2, r3] @ movhi
- sub r3, r4, #3520
- ldrh r3, [r3, #-8]
- cmp r3, #17
- bhi .L3264
-.L3262:
- ldr r0, .L3295+12
+.L3181:
+ ldr r0, .L3213+24
bl FtlGcScanTempBlk
cmn r0, #1
- str r0, [sp, #20]
- beq .L3265
- ldr r3, .L3295
- mov r5, r5, asl #1
- ldr r2, [r3, #-3608]
- ldrh r3, [r2, r5]
+ str r0, [sp, #12]
+ beq .L3184
+ ldr r2, [r4, #-3604]
+ lsl r7, r7, #1
+ ldrh r3, [r2, r7]
cmp r3, #4
- bls .L3266
+ bls .L3185
sub r3, r3, #5
mov r0, #1
- strh r3, [r2, r5] @ movhi
+ strh r3, [r2, r7] @ movhi
bl FtlEctTblFlush
-.L3266:
+.L3185:
ldr r3, [r4, #-372]
- ldr r2, .L3295
cmp r3, #0
- bne .L3267
- ldr r0, [sp, #20]
- ldr r3, [r2, #-3136]
- ubfx r0, r0, #10, #16
+ bne .L3186
+ ldr r3, [r4, #-3140]
+ ldr r0, [sp, #12]
add r3, r3, #1
- str r3, [r2, #-3136]
+ ubfx r0, r0, #10, #16
+ str r3, [r4, #-3140]
bl FtlBbmMapBadBlock
bl FtlBbmTblFlush
-.L3267:
+.L3186:
mov r3, #0
str r3, [r4, #-372]
- b .L3279
-.L3265:
- ldr r2, .L3295+8
- movw r3, #3448
+.L3198:
+ mov r0, #1
+ b .L3175
+.L3182:
+ strh ip, [r2, r3] @ movhi
+ sub r3, r4, #3520
+ ldrh r3, [r3, #-4]
+ cmp r3, #17
+ bhi .L3183
+ b .L3181
+.L3184:
+ ldr r2, .L3213+20
+ movw r3, #3444
ldrh r2, [r2, r3]
movw r3, #65535
cmp r2, r3
- bne .L3279
- b .L3268
-.L3272:
- ldr r3, [r5, #4]
- cmp r0, r3
- bne .L3291
-.L3271:
- add r8, r8, #1
-.L3269:
- ldrh r2, [fp]
- uxth r3, r8
- cmp r2, r3
- bls .L3294
- mov r9, #12
- ldr r2, [r6, #2448]
- mul r9, r9, r3
- ldr r3, [sp, #8]
- ldr ip, [r3, #-2672]
- add r5, ip, r9
- ldr r0, [r5, #8]
+ bne .L3198
+ b .L3187
+.L3192:
+ uxth r10, r7
+ ldr r3, [r4, #-2672]
+ ldr r2, [r6, #2452]
+ mul r10, fp, r10
+ add r9, r3, r10
+ ldr r0, [r9, #8]
cmp r0, r2
- bcs .L3291
+ bcc .L3189
+.L3210:
+ ldrh r0, [r5]
+ b .L3211
+.L3189:
mov r2, #0
- add r1, sp, #20
- str ip, [sp, #12]
+ add r1, sp, #12
+ str r3, [sp, #4]
bl log2phys
- ldr ip, [sp, #12]
- ldr r0, [sp, #20]
- ldr r2, [ip, r9]
+ ldr r3, [sp, #4]
+ ldr r2, [sp, #12]
+ ldr r0, [r3, r10]
cmp r0, r2
- bne .L3272
+ bne .L3191
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
- add r1, r5, #4
mov r2, #1
- mov r9, r0
- ldr r0, [r5, #8]
+ mov r10, r0
+ add r1, r9, #4
+ ldr r0, [r9, #8]
bl log2phys
- mov r0, r9
- b .L3292
-.L3291:
- ldrh r0, [r10]
-.L3292:
+ mov r0, r10
+.L3211:
bl decrement_vpc_count
- b .L3271
-.L3294:
- movw r0, #65535
- bl decrement_vpc_count
- ldrb r3, [r6, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L3274
- ldr r0, .L3295+16
- ldrh r1, [r7, #-4]
- bl printk
-.L3274:
- ldrh r0, [r7, #-4]
- ldr r2, [r4, #-3544]
- mov r3, r0, asl #1
- ldrh r3, [r2, r3]
- cmp r3, #0
- beq .L3275
- bl INSERT_DATA_LIST
- b .L3276
-.L3275:
- bl INSERT_FREE_LIST
-.L3276:
- ldr r3, [sp, #4]
- mvn r5, #0
- ldr r4, .L3295
- strh r5, [r7, #-4] @ movhi
- mov r7, #0
- strh r7, [r3, #-12] @ movhi
- sub r3, r4, #2672
- strh r7, [r3, #-4] @ movhi
- bl l2p_flush
- bl FtlVpcTblFlush
- sub r3, r4, #3280
- sub r2, r4, #3520
- strh r5, [r3, #-4] @ movhi
- ldr r3, [r6, #2244]
- ldrh r2, [r2, #-8]
- cmp r3, r7
- sub r3, r4, #3296
- ldrh r3, [r3, #-8]
- beq .L3277
- ldr r1, [r4, #-3308]
- cmp r1, #39
- bhi .L3277
+ b .L3190
+.L3191:
+ ldr r3, [r9, #4]
cmp r2, r3
- subcc r4, r4, #2720
- movcc r3, r3, asl #1
- strcch r3, [r4] @ movhi
- b .L3293
-.L3277:
- add r1, r3, r3, asl #1
+ bne .L3210
+.L3190:
+ add r7, r7, #1
+ b .L3188
+.L3194:
+ bl INSERT_FREE_LIST
+ b .L3195
+.L3196:
+ add r1, r3, r3, lsl #1
cmp r2, r1, asr #2
- ble .L3293
- ldrb r0, [r6, #144] @ zero_extendqisi2
- ldr r2, .L3295+20
+ ble .L3212
+ ldrb r0, [r6, #152] @ zero_extendqisi2
+ ldr r2, .L3213+28
cmp r0, #0
moveq r3, #20
- streqh r3, [r2] @ movhi
- beq .L3258
+ strheq r3, [r2] @ movhi
+ beq .L3175
sub r3, r3, #2
strh r3, [r2] @ movhi
-.L3293:
- mov r0, #0
- b .L3258
-.L3279:
- mov r0, #1
-.L3258:
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3296:
+ b .L3212
+.L3214:
.align 2
-.L3295:
+.L3213:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR1
- .word .LANCHOR2-3428
+ .word .LANCHOR2-2656
.word .LC155
+ .word .LANCHOR2-2672
+ .word .LANCHOR1
+ .word .LANCHOR2-3424
.word .LANCHOR2-2720
.fnend
.size FtlGcFreeTempBlock, .-FtlGcFreeTempBlock
.align 2
.global FtlGcPageRecovery
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlGcPageRecovery, %function
FtlGcPageRecovery:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- movw r5, #2388
- ldr r7, .L3300
- ldr r6, .L3300+4
- ldr r4, .L3300+8
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ movw r5, #2390
+ ldr r4, .L3218
+ ldr r6, .L3218+4
+ sub r7, r4, #3424
mov r0, r7
ldrh r1, [r6, r5]
bl FtlGcScanTempBlk
ldrh r2, [r7, #2]
ldrh r3, [r6, r5]
cmp r2, r3
- ldmccfd sp!, {r3, r4, r5, r6, r7, pc}
+ popcc {r4, r5, r6, r7, r8, pc}
sub r0, r4, #432
bl FtlMapBlkWriteDumpData
mov r0, #0
bl FtlGcFreeTempBlock
mov r3, #0
str r3, [r4, #-372]
- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
-.L3301:
+ pop {r4, r5, r6, r7, r8, pc}
+.L3219:
.align 2
-.L3300:
- .word .LANCHOR2-3428
- .word .LANCHOR0
+.L3218:
.word .LANCHOR2
+ .word .LANCHOR0
.fnend
.size FtlGcPageRecovery, .-FtlGcPageRecovery
.align 2
.global FtlPowerLostRecovery
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlPowerLostRecovery, %function
FtlPowerLostRecovery:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- mov r6, #0
- ldr r4, .L3304
- ldr r3, .L3304+4
- sub r5, r4, #3520
+ mov r5, #0
+ ldr r4, .L3222
+ sub r6, r4, #3520
+ str r5, [r4, #1852]
+ mov r0, r6
sub r4, r4, #3472
- sub r5, r5, #4
- sub r4, r4, #4
- str r6, [r3, #1852]
- mov r0, r5
bl FtlRecoverySuperblock
- mov r0, r5
+ mov r0, r6
bl FtlSlcSuperblockCheck
mov r0, r4
bl FtlRecoverySuperblock
@@ -19569,51 +20077,54 @@
bl FtlGcPageRecovery
movw r0, #65535
bl decrement_vpc_count
- mov r0, r6
- ldmfd sp!, {r4, r5, r6, pc}
-.L3305:
+ mov r0, r5
+ pop {r4, r5, r6, pc}
+.L3223:
.align 2
-.L3304:
+.L3222:
.word .LANCHOR2
- .word .LANCHOR4
.fnend
.size FtlPowerLostRecovery, .-FtlPowerLostRecovery
.align 2
.global FtlSysBlkInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlSysBlkInit, %function
FtlSysBlkInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- .save {r3, r4, r5, r6, r7, r8, r9, lr}
- movw r3, #1850
- ldr r4, .L3324
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r2, #0
- ldr r6, .L3324+4
- ldr r5, .L3324+8
- strh r2, [r4, r3] @ movhi
+ ldr r5, .L3242
movw r3, #1848
+ ldr r6, .L3242+4
+ strh r2, [r5, r3] @ movhi
mvn r2, #0
- strh r2, [r4, r3] @ movhi
- ldr r3, [r6, #2324]
- uxth r0, r3
+ movw r3, #1846
+ strh r2, [r5, r3] @ movhi
+ add r3, r6, #2320
+ add r3, r3, #8
+ ldrh r0, [r3]
bl FtlFreeSysBlkQueueInit
bl FtlScanSysBlk
sub r3, r5, #3296
ldrh r2, [r3, #-4]
movw r3, #65535
cmp r2, r3
- bne .L3307
-.L3309:
- mvn r8, #0
- b .L3308
-.L3307:
+ bne .L3225
+.L3227:
+ mvn r7, #0
+.L3224:
+ mov r0, r7
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3225:
bl FtlLoadSysInfo
- subs r8, r0, #0
- bne .L3309
+ subs r7, r0, #0
+ bne .L3227
bl FtlLoadMapInfo
- mov r7, r4
bl FtlLoadVonderInfo
bl Ftl_load_ext_data
bl FtlLoadEctTbl
@@ -19622,638 +20133,642 @@
bl FtlPowerLostRecovery
mov r0, #1
bl FtlUpdateVaildLpn
- ldr r2, [r5, #-3380]
- movw r3, #2426
- mov r0, #12
+ ldr r2, [r5, #-3376]
+ movw r3, #2430
ldrh r1, [r6, r3]
- mov r3, r8
-.L3310:
+ mov r0, #12
+ mov r3, r7
+.L3228:
cmp r3, r1
- bge .L3315
+ bge .L3233
mla ip, r0, r3, r2
ldr ip, [ip, #4]
cmp ip, #0
- bge .L3311
-.L3315:
- ldr r4, .L3324+12
+ bge .L3229
+.L3233:
+ ldr r4, .L3242+8
cmp r3, r1
- add r9, r4, #80
ldrh r2, [r4, #28]
+ add r8, r4, #12
+ add r4, r4, #76
add r2, r2, #1
- strh r2, [r4, #28] @ movhi
- bge .L3322
- b .L3312
-.L3311:
- add r3, r3, #1
- b .L3310
-.L3322:
- movw r3, #1850
- ldrh r3, [r7, r3]
- cmp r3, #0
- beq .L3316
-.L3312:
- ldrh r2, [r9, #-4]
- ldr r3, .L3324+16
- ldr r0, [r5, #-3544]
- mov r2, r2, asl #1
- ldrh ip, [r3, #4]
- ldrh r1, [r0, r2]
- rsb r1, ip, r1
- movw ip, #2388
- strh r1, [r0, r2] @ movhi
- add r1, r3, #48
- ldrh r2, [r6, ip]
- ldr lr, [r5, #-3544]
- ldrh r7, [r1, #4]
- strh r2, [r3, #2] @ movhi
+ strh r2, [r4, #-48] @ movhi
+ bge .L3240
+.L3230:
+ ldrh r3, [r4]
+ movw ip, #2390
+ ldr r1, [r5, #-3540]
+ ldrh r0, [r4, #4]
+ lsl r3, r3, #1
+ ldrh r2, [r1, r3]
+ sub r2, r2, r0
+ strh r2, [r1, r3] @ movhi
mov r2, #0
- strh r2, [r3, #4] @ movhi
- ldrh r3, [r3, #48]
- strb r2, [r5, #-3518]
- mov r3, r3, asl #1
- ldrh r0, [lr, r3]
- rsb r0, r7, r0
- strh r0, [lr, r3] @ movhi
ldrh r3, [r6, ip]
- strb r2, [r5, #-3470]
- strh r2, [r1, #4] @ movhi
- strh r3, [r1, #2] @ movhi
- ldrh r3, [r4, #30]
+ ldr lr, [r5, #-3540]
+ strb r2, [r5, #-3514]
+ strh r3, [r4, #2] @ movhi
+ ldr r3, .L3242+12
+ strh r2, [r4, #4] @ movhi
+ ldrh r1, [r3]
+ ldrh r9, [r3, #4]
+ lsl r1, r1, #1
+ ldrh r0, [lr, r1]
+ sub r0, r0, r9
+ strh r0, [lr, r1] @ movhi
+ ldrh r1, [r6, ip]
+ strh r2, [r3, #4] @ movhi
+ strb r2, [r5, #-3466]
+ strh r1, [r3, #2] @ movhi
+ ldrh r3, [r8, #18]
add r3, r3, #1
- strh r3, [r4, #30] @ movhi
+ strh r3, [r8, #18] @ movhi
bl l2p_flush
bl FtlVpcTblFlush
bl FtlVpcTblFlush
-.L3316:
- ldrh r0, [r9, #-4]
+ b .L3234
+.L3229:
+ add r3, r3, #1
+ b .L3228
+.L3240:
+ movw r3, #1848
+ ldrh r3, [r5, r3]
+ cmp r3, #0
+ bne .L3230
+.L3234:
+ ldrh r0, [r4]
movw r3, #65535
- ldr r5, .L3324+16
cmp r0, r3
- beq .L3317
- ldrh r3, [r5, #4]
+ beq .L3235
+ ldrh r3, [r4, #4]
cmp r3, #0
- bne .L3317
- ldrh r3, [r5, #52]
- add r9, r5, #52
- add r7, r5, #48
+ bne .L3235
+ ldr r4, .L3242+12
+ ldrh r3, [r4, #4]
cmp r3, #0
- bne .L3317
+ bne .L3235
bl FtlGcRefreshOpenBlock
- ldrh r0, [r5, #48]
+ ldrh r0, [r4]
bl FtlGcRefreshOpenBlock
bl FtlVpcTblFlush
- mov r0, r5
+ sub r0, r4, #48
bl allocate_new_data_superblock
- mov r0, r7
+ mov r0, r4
bl allocate_new_data_superblock
-.L3317:
- ldrb r3, [r6] @ zero_extendqisi2
+.L3235:
+ ldrb r3, [r6, #36] @ zero_extendqisi2
cmp r3, #0
- bne .L3318
- ldrh r3, [r4, #28]
+ bne .L3236
+ ldrh r3, [r8, #16]
tst r3, #31
- bne .L3308
-.L3318:
+ bne .L3224
+.L3236:
bl FtlVpcCheckAndModify
-.L3308:
- mov r0, r8
- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
-.L3325:
+ b .L3224
+.L3243:
.align 2
-.L3324:
- .word .LANCHOR4
- .word .LANCHOR0
+.L3242:
.word .LANCHOR2
- .word .LANCHOR2-3600
- .word .LANCHOR2-3524
+ .word .LANCHOR0
+ .word .LANCHOR2-3596
+ .word .LANCHOR2-3472
.fnend
.size FtlSysBlkInit, .-FtlSysBlkInit
.align 2
.global FtlLowFormat
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlLowFormat, %function
FtlLowFormat:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.pad #12
- ldr r4, .L3361
- ldr r6, [r4, #-3616]
+ ldr r4, .L3276
+ ldr r6, [r4, #-3612]
cmp r6, #0
- bne .L3328
- ldr r5, .L3361+4
- movw r7, #2424
+ bne .L3246
+ ldr r5, .L3276+4
+ movw r7, #2428
mov r1, r6
ldr r0, [r4, #-448]
ldrh r2, [r5, r7]
- mov r2, r2, asl #2
+ lsl r2, r2, #2
bl ftl_memset
ldrh r2, [r5, r7]
mov r1, r6
ldr r0, [r4, #-452]
- mov r2, r2, asl #2
+ lsl r2, r2, #2
bl ftl_memset
- ldr r3, [r5, #2324]
+ add r3, r5, #2320
str r6, [r4, #-3332]
+ add r3, r3, #8
+ ldrh r0, [r3]
str r6, [r4, #-3328]
- uxth r0, r3
bl FtlFreeSysBlkQueueInit
bl FtlLoadBbt
cmp r0, #0
- beq .L3329
+ beq .L3247
bl FtlMakeBbt
-.L3329:
- ldr r0, .L3361+8
+.L3247:
+ ldr r0, .L3276+8
mov r2, #0
- ldr ip, .L3361+12
-.L3330:
+ ldr ip, .L3276+12
+.L3248:
ldrh r1, [r0]
uxth r3, r2
add r2, r2, #1
- cmp r3, r1, asl #7
- bge .L3358
- ldr lr, [r4, #-508]
- mvn r1, r3
- orr r1, r3, r1, asl #16
- str r1, [lr, r3, asl #2]
- ldr r1, [r4, #-504]
- str ip, [r1, r3, asl #2]
- b .L3330
-.L3358:
- ldr r2, .L3361+4
- movw r3, #2328
- ldr r7, .L3361+16
- mov r8, #0
- ldrh r6, [r2, r3]
-.L3332:
- ldrh r3, [r7]
- ldr r10, .L3361+4
- cmp r3, r6
- ldr r9, .L3361+16
- bls .L3359
+ cmp r3, r1, lsl #7
+ blt .L3249
+ movw r3, #2332
+ ldr r9, .L3276+16
+ ldrh r7, [r5, r3]
+ mov r6, #0
+ mov r8, r9
+.L3250:
+ ldrh r3, [r9]
+ cmp r3, r7
+ bhi .L3251
+ movw r3, #2324
+ ldrh r1, [r5, r3]
+ sub r3, r6, #3
+ cmp r3, r1, lsl #1
+ blt .L3252
mov r0, r6
- mov r1, #1
- bl FtlLowFormatEraseBlock
- add r6, r6, #1
- uxth r6, r6
- add r0, r8, r0
- uxth r8, r0
- b .L3332
-.L3359:
- add r7, r10, #2320
- sub r3, r8, #3
- ldrh r1, [r7]
- cmp r3, r1, asl #1
- blt .L3334
- mov r0, r8
- mov r8, #0
+ mov r6, #0
bl __aeabi_uidiv
- ldr r3, [r10, #2420]
+ ldr r3, [r5, #2424]
add r0, r0, r3
uxth r0, r0
bl FtlSysBlkNumInit
- ldr r3, [r10, #2324]
- uxth r0, r3
+ add r3, r5, #2320
+ add r3, r3, #8
+ ldrh r0, [r3]
bl FtlFreeSysBlkQueueInit
- movw r3, #2328
- ldrh r6, [r10, r3]
-.L3335:
- ldrh r3, [r9]
- cmp r3, r6
- bls .L3334
- mov r0, r6
- mov r1, #1
- bl FtlLowFormatEraseBlock
- add r6, r6, #1
- uxth r6, r6
- add r0, r8, r0
- uxth r8, r0
- b .L3335
-.L3334:
- ldr r10, .L3361+20
- mov r9, #0
- mov r6, r9
-.L3337:
- ldrh r2, [r10]
- uxth r0, r9
- ldr r3, .L3361+4
- add r9, r9, #1
- cmp r2, r0
- bls .L3360
- mov r1, #0
- bl FtlLowFormatEraseBlock
- add r0, r6, r0
- uxth r6, r0
- b .L3337
-.L3360:
- movw r2, #2330
- ldrh r9, [r7]
- ldrh r2, [r3, r2]
- str r3, [sp, #4]
- mov r1, r9
- ldr r7, .L3361+24
- str r2, [r4, #-548]
- ldr r2, [r3, #2332]
+ movw r3, #2332
+ ldrh r7, [r5, r3]
+.L3253:
+ ldrh r3, [r8]
+ cmp r3, r7
+ bhi .L3254
+.L3252:
+ ldr r8, .L3276+20
+ mov r7, #0
+ mov r9, r7
+.L3255:
+ ldrh r3, [r8]
+ uxth r0, r7
+ add r7, r7, #1
+ cmp r3, r0
+ bhi .L3256
+ movw r3, #2334
+ ldr r2, [r5, #2336]
+ ldrh r3, [r5, r3]
+ ldr r8, .L3276+24
mov r0, r2
- str r2, [sp]
+ str r2, [sp, #4]
+ str r3, [r4, #-548]
+ movw r3, #2324
+ ldrh r7, [r5, r3]
+ mov r1, r7
bl __aeabi_uidiv
ubfx r10, r0, #5, #16
- ldr r3, [sp, #4]
- add r1, r10, #36
- strh r1, [r7, #-8] @ movhi
- mov r1, #24
mov fp, r0
- mul r1, r1, r9
- str r0, [r3, #2448]
- ldr r2, [sp]
- cmp r6, r1
- ble .L3339
- rsb r0, r6, r2
- mov r1, r9
- str r3, [sp]
+ add r3, r10, #36
+ str r0, [r5, #2452]
+ strh r3, [r8, #-8] @ movhi
+ mov r3, #24
+ mul r3, r3, r7
+ cmp r9, r3
+ ble .L3257
+ ldr r2, [sp, #4]
+ mov r1, r7
+ sub r0, r2, r9
bl __aeabi_uidiv
- ldr r3, [sp]
- str r0, [r3, #2448]
- mov r0, r0, lsr #5
+ str r0, [r5, #2452]
+ lsr r0, r0, #5
add r0, r0, #24
- strh r0, [r7, #-8] @ movhi
-.L3339:
- ldr r3, [r5, #2244]
+ strh r0, [r8, #-8] @ movhi
+.L3257:
+ ldr r3, [r5, #2248]
cmp r3, #1
- bne .L3340
- ldrh r3, [r7, #-8]
- mov r0, r6
- mov r1, r9
- str r3, [sp]
+ bne .L3258
+ ldrh r3, [r8, #-8]
+ mov r1, r7
+ mov r0, r9
+ str r3, [sp, #4]
bl __aeabi_uidiv
- ldr r3, [sp]
+ ldr r3, [sp, #4]
uxtah r0, r3, r0
add r3, r3, r0, asr #2
- strh r3, [r7, #-8] @ movhi
-.L3340:
- ldrb r3, [r5, #144] @ zero_extendqisi2
+ strh r3, [r8, #-8] @ movhi
+.L3258:
+ ldrb r3, [r5, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3341
- ldrh r3, [r7, #-8]
- mov r0, r6
- mov r1, r9
- str r3, [sp]
+ beq .L3259
+ ldrh r3, [r8, #-8]
+ mov r1, r7
+ mov r0, r9
+ str r3, [sp, #4]
bl __aeabi_uidiv
- ldr r3, [sp]
+ ldr r3, [sp, #4]
uxtah r0, r3, r0
add r3, r3, r0, asr #2
- strh r3, [r7, #-8] @ movhi
-.L3341:
- movw r3, #2382
- ldrh r3, [r5, r3]
+ strh r3, [r8, #-8] @ movhi
+.L3259:
+ ldr r3, .L3276+28
+ ldrh r3, [r3]
cmp r3, #0
- beq .L3343
- ldrh r2, [r7, #-8]
+ beq .L3261
+ ldrh r2, [r8, #-8]
add r2, r2, r3, lsr #1
- strh r2, [r7, #-8] @ movhi
- mul r2, r9, r3
- cmp r2, r6
- addgt r3, r3, #32
- ldrgt r2, .L3361+4
- addgt r3, r10, r3
- strgt fp, [r2, #2448]
- ldrgt r2, .L3361+24
- strgth r3, [r2, #-8] @ movhi
-.L3343:
- ldrh r2, [r7, #-8]
- ldr r3, [r5, #2448]
- rsb r3, r2, r3
- mul r9, r9, r3
- movw r3, #2388
+ strh r2, [r8, #-8] @ movhi
+ mul r2, r7, r3
+ cmp r9, r2
+ addlt r3, r3, #32
+ strlt fp, [r5, #2452]
+ addlt r3, r10, r3
+ strhlt r3, [r8, #-8] @ movhi
+.L3261:
+ ldrh r2, [r8, #-8]
+ ldr r3, [r5, #2452]
+ sub r3, r3, r2
+ mul r7, r7, r3
+ movw r3, #2390
ldrh r3, [r5, r3]
- str r9, [r4, #1788]
- mul r9, r3, r9
- movw r3, #2394
+ str r7, [r4, #1796]
+ mul r7, r7, r3
+ movw r3, #2396
ldrh r3, [r5, r3]
- str r9, [r5, #2448]
- mul r9, r3, r9
- str r9, [r5, #2428]
+ str r7, [r5, #2452]
+ mul r7, r7, r3
+ str r7, [r5, #2432]
bl FtlBbmTblFlush
- ldr r2, [r5, #2336]
- movw r3, #2402
+ movw r3, #2404
+ ldr r2, [r5, #2340]
ldrh r3, [r5, r3]
- add r1, r6, r8
+ add r1, r6, r9
add r3, r3, r2, lsr #3
cmp r1, r3
- bls .L3345
- ldr r0, .L3361+28
- mov r2, r2, lsr #5
+ bls .L3263
+ lsr r2, r2, #5
+ ldr r0, .L3276+32
bl printk
-.L3345:
- movw r3, #2330
- ldr r6, .L3361+32
+.L3263:
+ movw r3, #2334
+ ldr r6, .L3276+36
ldrh r2, [r5, r3]
mov r1, #0
- sub r8, r6, #244
- ldr r0, [r4, #-3544]
- mvn r9, #0
- mov r2, r2, asl #1
- mov fp, r8
+ ldr r0, [r4, #-3540]
+ mvn r7, #0
+ sub r6, r6, #240
+ lsl r2, r2, #1
bl ftl_memset
mov r3, #0
- strh r3, [r6, #-2] @ movhi
+ strh r7, [r6, #236] @ movhi
+ strh r3, [r6, #238] @ movhi
mov r1, #255
- strh r3, [r6, #-244] @ movhi
- str r3, [r4, #-3372]
+ str r3, [r4, #-3368]
strb r3, [r4, #-3278]
strb r3, [r4, #-3276]
- strh r3, [r8, #2] @ movhi
- strb r3, [r4, #-3518]
- mov r3, #1
- strb r3, [r4, #-3516]
- movw r3, #2328
- ldrh r2, [r5, r3]
- ldr r0, [r4, #-3368]
- strh r9, [r6, #-4] @ movhi
- add r6, r6, #3280
- mov r2, r2, lsr #3
- bl ftl_memset
-.L3346:
- ldr r10, .L3361+36
- ldr r5, .L3361
- mov r0, r10
- bl make_superblock
- ldrb r3, [r4, #-3517] @ zero_extendqisi2
- cmp r3, #0
- ldrh r3, [r8]
- bne .L3347
- ldr r2, [r6, #-3544]
- mov r3, r3, asl #1
- strh r9, [r2, r3] @ movhi
- ldrh r3, [fp]
- add r3, r3, #1
- strh r3, [fp] @ movhi
- b .L3346
-.L3347:
- ldr r2, [r5, #-3332]
- mov r3, r3, asl #1
- ldrh r1, [r10, #4]
- mov r9, r5
- str r2, [r5, #-3512]
- add r2, r2, #1
- str r2, [r5, #-3332]
- ldr r2, [r5, #-3544]
- strh r1, [r2, r3] @ movhi
- sub r2, r5, #3472
- sub r6, r2, #4
- mov r3, #0
- strb r3, [r5, #-3470]
strh r3, [r6, #2] @ movhi
- ldrh r3, [r10]
- mvn r10, #0
- add r3, r3, #1
- strh r3, [r2, #-4] @ movhi
- mov r3, #1
- strb r3, [r5, #-3468]
-.L3348:
- ldr r8, .L3361+40
- ldr r5, .L3361
- mov r0, r8
- bl make_superblock
- ldrb r3, [r4, #-3469] @ zero_extendqisi2
- cmp r3, #0
- ldrh r3, [r6]
- bne .L3349
- ldr r2, [r9, #-3544]
- mov r3, r3, asl #1
- strh r10, [r2, r3] @ movhi
- ldrh r3, [r6]
- add r3, r3, #1
+ strb r3, [r4, #-3514]
strh r3, [r6] @ movhi
- b .L3348
-.L3349:
- ldr r2, [r5, #-3332]
- mov r3, r3, asl #1
- ldrh r1, [r8, #4]
- mvn r4, #0
- str r2, [r5, #-3464]
- add r2, r2, #1
- str r2, [r5, #-3332]
- ldr r2, [r5, #-3544]
- strh r1, [r2, r3] @ movhi
- sub r3, r5, #3424
- strh r4, [r3, #-4] @ movhi
- bl FtlFreeSysBlkQueueOut
- ldr r3, .L3361+44
- mov r2, #0
- strh r2, [r3, #2] @ movhi
- ldr r2, [r5, #1788]
- strh r4, [r3, #4] @ movhi
- strh r2, [r3, #6] @ movhi
- ldr r3, [r5, #-3332]
- str r3, [r5, #-3292]
+ mov r3, #1
+ strb r3, [r4, #-3512]
+ movw r3, #2332
+ ldrh r2, [r5, r3]
+ ldr r0, [r5, #32]
+ mov r5, r6
+ lsr r2, r2, #3
+ bl ftl_memset
+.L3264:
+ mov r0, r6
+ bl make_superblock
+ ldrb r3, [r4, #-3513] @ zero_extendqisi2
+ cmp r3, #0
+ ldrh r3, [r5]
+ bne .L3265
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
+ strh r7, [r2, r3] @ movhi
+ ldrh r3, [r5]
add r3, r3, #1
- str r3, [r5, #-3332]
- strh r0, [r7, #-4] @ movhi
+ strh r3, [r5] @ movhi
+ b .L3264
+.L3249:
+ ldr lr, [r4, #-508]
+ mvn r1, r3
+ orr r1, r3, r1, lsl #16
+ str r1, [lr, r3, lsl #2]
+ ldr r1, [r4, #-504]
+ str ip, [r1, r3, lsl #2]
+ b .L3248
+.L3251:
+ mov r0, r7
+ mov r1, #1
+ bl FtlLowFormatEraseBlock
+ add r7, r7, #1
+ add r6, r6, r0
+ uxth r6, r6
+ uxth r7, r7
+ b .L3250
+.L3254:
+ mov r0, r7
+ mov r1, #1
+ bl FtlLowFormatEraseBlock
+ add r7, r7, #1
+ add r6, r6, r0
+ uxth r6, r6
+ uxth r7, r7
+ b .L3253
+.L3256:
+ mov r1, #0
+ bl FtlLowFormatEraseBlock
+ add r9, r9, r0
+ uxth r9, r9
+ b .L3255
+.L3265:
+ ldr r2, [r4, #-3332]
+ lsl r3, r3, #1
+ ldrh r1, [r5, #4]
+ mvn r6, #0
+ str r2, [r4, #-3508]
+ add r2, r2, #1
+ str r2, [r4, #-3332]
+ ldr r2, [r4, #-3540]
+ strh r1, [r2, r3] @ movhi
+ mov r2, #0
+ ldr r3, .L3276+40
+ strb r2, [r4, #-3466]
+ strh r2, [r3, #2] @ movhi
+ mov r7, r3
+ ldrh r2, [r5]
+ mov r5, r3
+ add r2, r2, #1
+ strh r2, [r3] @ movhi
+ mov r2, #1
+ strb r2, [r4, #-3464]
+.L3266:
+ mov r0, r7
+ bl make_superblock
+ ldrb r3, [r4, #-3465] @ zero_extendqisi2
+ cmp r3, #0
+ ldrh r3, [r5]
+ bne .L3267
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
+ strh r6, [r2, r3] @ movhi
+ ldrh r3, [r5]
+ add r3, r3, #1
+ strh r3, [r5] @ movhi
+ b .L3266
+.L3267:
+ ldr r2, [r4, #-3332]
+ lsl r3, r3, #1
+ ldrh r1, [r5, #4]
+ mvn r5, #0
+ str r2, [r4, #-3460]
+ add r2, r2, #1
+ str r2, [r4, #-3332]
+ ldr r2, [r4, #-3540]
+ strh r1, [r2, r3] @ movhi
+ ldr r3, .L3276+44
+ strh r5, [r3] @ movhi
+ bl FtlFreeSysBlkQueueOut
+ sub r3, r8, #4
+ mov r2, #0
+ strh r5, [r3, #4] @ movhi
+ ldr r3, [r4, #-3332]
+ strh r2, [r8, #-2] @ movhi
+ ldr r2, [r4, #1796]
+ str r3, [r4, #-3292]
+ add r3, r3, #1
+ str r3, [r4, #-3332]
+ strh r2, [r8, #2] @ movhi
+ strh r0, [r8, #-4] @ movhi
bl FtlVpcTblFlush
bl FtlSysBlkInit
cmp r0, #0
- ldreq r3, .L3361+48
+ ldreq r3, .L3276+48
moveq r2, #1
- streq r2, [r3, #504]
-.L3328:
+ streq r2, [r3, #500]
+.L3246:
mov r0, #0
add sp, sp, #12
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3362:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3277:
.align 2
-.L3361:
+.L3276:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR0+2394
+ .word .LANCHOR0+2396
.word 168778952
- .word .LANCHOR0+2330
- .word .LANCHOR0+2328
+ .word .LANCHOR0+2334
+ .word .LANCHOR0+2332
.word .LANCHOR2-3296
+ .word .LANCHOR0+2384
.word .LC156
.word .LANCHOR2-3280
- .word .LANCHOR2-3524
- .word .LANCHOR2-3476
- .word .LANCHOR2-3300
+ .word .LANCHOR2-3472
+ .word .LANCHOR2-3424
.word .LANCHOR1
.fnend
.size FtlLowFormat, .-FtlLowFormat
.align 2
.global FtlReInitForSDUpdata
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlReInitForSDUpdata, %function
FtlReInitForSDUpdata:
.fnstart
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, lr}
- .save {r4, r5, lr}
- .pad #20
- sub sp, sp, #20
- ldr r4, .L3392
- ldrb r3, [r4, #144] @ zero_extendqisi2
+ push {r0, r1, r2, r3, r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ .pad #16
+ ldr r4, .L3314
+ ldrb r3, [r4, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3364
-.L3366:
- mov r0, #0
- b .L3365
-.L3364:
- ldr r5, .L3392+4
+ beq .L3279
+.L3281:
+ mov r6, #0
+.L3278:
+ mov r0, r6
+ add sp, sp, #16
+ @ sp needed
+ pop {r4, r5, r6, pc}
+.L3279:
+ ldr r5, .L3314+4
ldr r0, [r5, #1684]
bl FlashInit
- cmp r0, #0
- bne .L3366
+ subs r6, r0, #0
+ bne .L3281
bl FlashLoadFactorBbt
cmp r0, #0
- beq .L3367
+ beq .L3282
bl FlashMakeFactorBbt
-.L3367:
- ldr r0, [r5, #1716]
+.L3282:
+ ldr r0, [r5, #1724]
bl FlashReadIdbDataRaw
cmp r0, #0
- beq .L3368
- mov r1, #0
+ beq .L3283
mov r2, #16
+ mov r1, #0
mov r0, sp
bl FlashReadFacBbtData
+ ldr r1, [sp]
mov r3, #0
mov r2, r3
- mov ip, #1
- ldr r1, [sp]
-.L3369:
- ands lr, r1, ip, asl r2
- add r0, r3, #1
+ mov r0, #1
+.L3285:
+ ands ip, r1, r0, lsl r2
add r2, r2, #1
- movne r3, r0
+ addne r3, r3, #1
cmp r2, #16
- bne .L3369
+ bne .L3285
cmp r3, #6
- bls .L3388
+ bhi .L3286
+.L3311:
+ strb r2, [r4, #37]
+ b .L3287
+.L3286:
mov r2, #0
- mov ip, #1
-.L3372:
- ands lr, r1, ip, asl r2
- add r0, r3, #1
+ mov r0, #1
+.L3289:
+ ands ip, r1, r0, lsl r2
add r2, r2, #1
- movne r3, r0
+ addne r3, r3, #1
cmp r2, #24
- bne .L3372
+ bne .L3289
cmp r3, #17
movhi r3, #36
- strhib r3, [r4, #1]
- bhi .L3371
-.L3388:
- strb r2, [r4, #1]
-.L3371:
- ldrb r3, [r4, #1] @ zero_extendqisi2
- strh r3, [r4, #142] @ movhi
-.L3368:
- ldr r1, .L3392+8
- ldr r0, .L3392+12
+ strbhi r3, [r4, #37]
+ bls .L3311
+.L3287:
+ ldrb r3, [r4, #37] @ zero_extendqisi2
+ strh r3, [r4, #150] @ movhi
+.L3283:
+ ldr r1, .L3314+8
+ ldr r0, .L3314+12
bl printk
- ldr r0, .L3392+16
+ ldr r0, .L3314+16
bl FtlConstantsInit
bl FtlVariablesInit
- ldr r0, [r4, #2324]
+ ldr r0, [r4, #2328]
mov r4, #1
uxth r0, r0
bl FtlFreeSysBlkQueueInit
-.L3374:
+.L3291:
bl FtlLoadBbt
cmp r0, #0
- beq .L3375
-.L3390:
+ beq .L3292
+.L3313:
bl FtlLowFormat
cmp r4, #3
- addls r4, r4, #1
- bls .L3374
-.L3391:
- mvn r0, #0
- b .L3365
-.L3375:
+ mvnhi r6, #0
+ bhi .L3278
+.L3293:
+ add r4, r4, #1
+ b .L3291
+.L3292:
bl FtlSysBlkInit
cmp r0, #0
- bne .L3390
- ldr r3, .L3392+20
+ bne .L3313
+ ldr r3, .L3314+20
mov r2, #1
- str r2, [r3, #504]
-.L3365:
- add sp, sp, #20
- @ sp needed
- ldmfd sp!, {r4, r5, pc}
-.L3393:
+ str r2, [r3, #500]
+ b .L3278
+.L3315:
.align 2
-.L3392:
+.L3314:
.word .LANCHOR0
.word .LANCHOR2
- .word .LC77
.word .LC76
- .word .LANCHOR0+116
+ .word .LC77
+ .word .LANCHOR0+124
.word .LANCHOR1
.fnend
.size FtlReInitForSDUpdata, .-FtlReInitForSDUpdata
.align 2
.global Ftl_gc_temp_data_write_back
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_gc_temp_data_write_back, %function
Ftl_gc_temp_data_write_back:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
- .save {r4, r5, r6, r7, r8, lr}
- ldr r5, .L3411
- ldr r3, [r5, #-3616]
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ ldr r4, .L3332
+ ldr r3, [r4, #-3612]
cmp r3, #0
- beq .L3395
-.L3398:
+ beq .L3317
+.L3320:
mov r0, #0
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L3395:
- ldr r3, .L3411+4
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ pop {r4, r5, r6, pc}
+.L3317:
+ ldr r3, .L3332+4
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3397
- ldr r3, [r5, #-2704]
+ beq .L3319
+ ldr r3, [r4, #-2704]
tst r3, #1
- beq .L3397
- ldr r3, .L3411+8
+ beq .L3319
+ sub r3, r4, #3424
ldrh r3, [r3, #4]
cmp r3, #0
- bne .L3398
-.L3397:
- mov r2, #0
- ldr r0, [r5, #-532]
- ldr r1, [r5, #-2704]
- mov r3, r2
+ bne .L3320
+.L3319:
+ mov r3, #0
+ mov r5, #0
+ mov r6, #36
+ mov r2, r3
+ ldr r1, [r4, #-2704]
+ ldr r0, [r4, #-532]
bl FlashProgPages
- ldr r7, .L3411
- mov r6, #0
- mov r8, #36
-.L3399:
- ldr r1, [r5, #-2704]
- uxth r3, r6
- ldr r4, .L3411
+.L3321:
+ ldr r1, [r4, #-2704]
+ uxth r3, r5
cmp r3, r1
- bcs .L3410
- mul r3, r8, r3
- ldr r0, [r7, #-532]
- add r6, r6, #1
- add r1, r0, r3
- ldr r0, [r0, r3]
- ldr r2, [r1, #12]
- cmn r0, #1
- bne .L3400
- sub r1, r4, #3424
- ldr ip, [r4, #-3544]
+ bcc .L3323
+ ldr r0, [r4, #-532]
+ bl FtlGcBufFree
+ mov r3, #0
+ str r3, [r4, #-2704]
+ ldr r3, .L3332+8
+ ldrh r3, [r3, #4]
+ cmp r3, #0
+ bne .L3320
+ mov r0, #1
+ bl FtlGcFreeTempBlock
+ b .L3331
+.L3323:
+ mul r3, r6, r3
+ ldr r2, [r4, #-532]
+ add r5, r5, #1
+ ldr ip, [r2, r3]
+ add r1, r2, r3
+ ldr r0, [r1, #12]
+ cmn ip, #1
+ bne .L3322
+ ldr r1, .L3332+8
mov lr, #0
- ldrh r2, [r1, #-4]
- mov r2, r2, asl #1
- strh lr, [ip, r2] @ movhi
- ldr r2, [r4, #-3136]
- strh r0, [r1, #-4] @ movhi
+ ldr r0, [r4, #-3540]
+ ldrh r2, [r1]
+ lsl r2, r2, #1
+ strh lr, [r0, r2] @ movhi
+ ldr r2, [r4, #-3140]
+ strh ip, [r1] @ movhi
add r2, r2, #1
- str r2, [r4, #-3136]
+ str r2, [r4, #-3140]
ldr r2, [r4, #-532]
add r3, r2, r3
ldr r0, [r3, #4]
@@ -20261,61 +20776,52 @@
bl FtlBbmMapBadBlock
bl FtlBbmTblFlush
bl FtlGcPageVarInit
- b .L3409
-.L3400:
- ldr r0, [r2, #12]
+.L3331:
+ mov r0, #1
+ pop {r4, r5, r6, pc}
+.L3322:
+ ldr r2, [r0, #8]
ldr r1, [r1, #4]
- ldr r2, [r2, #8]
+ ldr r0, [r0, #12]
bl FtlGcUpdatePage
- b .L3399
-.L3410:
- ldr r0, [r4, #-532]
- bl FtlGcBufFree
- mov r3, #0
- str r3, [r4, #-2704]
- ldr r3, .L3411+8
- ldrh r3, [r3, #4]
- cmp r3, #0
- bne .L3398
- mov r0, #1
- bl FtlGcFreeTempBlock
-.L3409:
- mov r0, #1
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L3412:
+ b .L3321
+.L3333:
.align 2
-.L3411:
+.L3332:
.word .LANCHOR2
.word .LANCHOR0
- .word .LANCHOR2-3428
+ .word .LANCHOR2-3424
.fnend
.size Ftl_gc_temp_data_write_back, .-Ftl_gc_temp_data_write_back
.align 2
.global Ftl_get_new_temp_ppa
+ .syntax unified
+ .arm
+ .fpu softvfp
.type Ftl_get_new_temp_ppa, %function
Ftl_get_new_temp_ppa:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- ldr r3, .L3417
- sub r2, r3, #4
- ldrh r1, [r3, #-4]
- movw r3, #65535
- cmp r1, r3
- beq .L3414
- ldrh r3, [r2, #4]
+ ldr r3, .L3341
+ movw r2, #65535
+ ldrh r1, [r3]
+ cmp r1, r2
+ beq .L3335
+ ldrh r3, [r3, #4]
cmp r3, #0
- bne .L3415
-.L3414:
- ldr r4, .L3417+4
+ ldrne r0, .L3341
+ bne .L3340
+.L3335:
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r5, #0
+ ldr r4, .L3341+4
bl FtlCacheWriteBack
mov r0, #0
- mov r5, #0
bl FtlGcFreeTempBlock
- ldr r0, .L3417+8
- strb r5, [r4, #-3420]
+ sub r0, r4, #3424
+ strb r5, [r4, #-3416]
bl allocate_data_superblock
sub r3, r4, #2672
sub r4, r4, #2656
@@ -20325,712 +20831,833 @@
mov r0, r5
bl FtlEctTblFlush
bl FtlVpcTblFlush
-.L3415:
- ldr r0, .L3417+8
- ldmfd sp!, {r3, r4, r5, lr}
+ pop {r4, r5, r6, lr}
+ ldr r0, .L3341
+.L3340:
b get_new_active_ppa
-.L3418:
+.L3342:
.align 2
-.L3417:
+.L3341:
.word .LANCHOR2-3424
.word .LANCHOR2
- .word .LANCHOR2-3428
.fnend
.size Ftl_get_new_temp_ppa, .-Ftl_get_new_temp_ppa
.align 2
.global ftl_do_gc
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_do_gc, %function
ftl_do_gc:
.fnstart
@ args = 0, pretend = 0, frame = 32
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L3583
- ldr ip, [r3, #-3616]
- cmp ip, #0
- bne .L3513
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L3507
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ mov lr, r0
.pad #44
sub sp, sp, #44
- ldr r4, .L3583+4
- ldr r8, [r4, #504]
- cmp r8, #1
- bne .L3515
+ ldr r0, [r3, #-3612]
+ cmp r0, #0
+ bne .L3439
+ ldr ip, .L3507+4
+ ldr r5, [ip, #500]
+ cmp r5, #1
+ bne .L3343
ldr r2, [r3, #-560]
cmp r2, #0
- bne .L3515
- mov r9, r0
- sub r0, r3, #3536
- ldrh r0, [r0]
+ bne .L3343
+ sub r8, r3, #3520
+ ldrh r0, [r8, #-12]
cmp r0, #47
- movls r0, r2
- bls .L3572
- movw r2, #3448
- str r1, [sp, #12]
- ldrh r1, [r4, r2]
+ bls .L3439
+ movw r2, #3444
+ mov r7, r1
+ ldrh r1, [ip, r2]
movw r2, #65535
- mov r5, r3
- str r9, [sp, #16]
+ mov r4, r3
+ str lr, [sp, #16]
cmp r1, r2
- bne .L3421
-.L3424:
- ldr r4, .L3583+8
+ bne .L3345
+.L3348:
+ ldr r6, .L3507+8
movw r2, #65535
- ldrh r0, [r4, #-8]
+ ldrh r0, [r6, #-8]
cmp r0, r2
- bne .L3422
- b .L3423
-.L3421:
- sub r3, r3, #3424
- ldrh r3, [r3, #-4]
- cmp r3, r2
- beq .L3424
- mov r0, r8
- bl FtlGcFreeTempBlock
- cmp r0, #0
- beq .L3424
- mov r0, r8
- b .L3572
-.L3422:
- ldrh r3, [r4, #-10]
- cmp r3, r2
- bne .L3423
- ldrh r1, [r4, #-6]
- cmp r1, r3
- beq .L3423
- ldrh r2, [r4, #-4]
- cmp r2, r3
- strneh r0, [r4, #-10] @ movhi
- strneh r1, [r4, #-8] @ movhi
- mvnne r3, #0
- strneh r2, [r4, #-6] @ movhi
- strneh r3, [r4, #-4] @ movhi
-.L3423:
- ldr r3, [sp, #16]
- ldr r8, [r5, #-2716]
- ldr r6, .L3583+12
- cmp r3, #1
- add r8, r8, #1
- add r8, r8, r3, asl #7
- sub r7, r6, #240
- str r8, [r5, #-2716]
- bne .L3435
- ldr r9, .L3583+16
- ldr r3, [r9, #2244]
- cmp r3, #0
- bne .L3426
- ldrb r3, [r9, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L3435
-.L3426:
- ldr r3, [r5, #-3308]
- ldr fp, .L3583
- cmp r3, #39
- bhi .L3435
- ldr r10, .L3583+20
- ldrh r3, [r10]
- add r8, r8, r3
- str r8, [fp, #-2716]
- bl FtlGcReFreshBadBlk
- ldrh r8, [r6, #-4]
- movw r3, #65535
- cmp r8, r3
- bne .L3435
- ldrh r3, [r4, #-10]
- cmp r3, r8
- bne .L3435
- ldr r3, [fp, #-2716]
- cmp r3, #1024
- bhi .L3427
- ldrh r3, [r7, #-8]
- cmp r3, #63
- bhi .L3435
-.L3427:
- ldr r1, .L3583
- mov r3, #0
- strh r3, [r10] @ movhi
- sub r8, r1, #2704
- ldrh r0, [r7, #-8]
- ldr r2, .L3583+20
- ldrh r10, [r8, #-14]
- add ip, r10, #64
- cmp r0, ip
- bgt .L3435
- str r3, [r1, #-2716]
- ldr r3, [r1, #-3308]
- cmp r3, #0
- moveq r3, #6
- beq .L3574
- cmp r3, #5
- bhi .L3429
- mov r3, #18
-.L3574:
- strh r3, [r2] @ movhi
-.L3429:
- mov r0, #32
- bl List_get_gc_head_node
- movw ip, #65535
- uxth r3, r0
- cmp r3, ip
- beq .L3434
- ldrh r0, [r8, #-8]
- ldr r2, .L3583
- cmp r0, #0
- sub r10, r2, #2704
- beq .L3431
- mov r8, r3, asl #1
- movw r3, #2390
- ldrh lr, [r9, r3]
- ldr r3, .L3583+24
- ldr r2, [r2, #-3544]
- ldrh r3, [r3]
- ldrh r1, [r2, r8]
- mul r3, r3, lr
+ bne .L3346
+.L3347:
+ ldr r3, [r4, #-2716]
+ ldr r2, [sp, #16]
add r3, r3, #1
+ cmp r2, #1
+ add r3, r3, r2, lsl #7
+ str r3, [r4, #-2716]
+ bne .L3349
+ ldr r9, .L3507+12
+ ldr r2, [r9, #2248]
+ cmp r2, #0
+ bne .L3350
+ ldrb r2, [r9, #152] @ zero_extendqisi2
+ cmp r2, #0
+ beq .L3349
+.L3350:
+ ldr r2, [r4, #-3308]
+ cmp r2, #39
+ bhi .L3349
+ ldr r10, .L3507+16
+ movw r5, #65535
+ ldrh r2, [r10]
+ add r3, r2, r3
+ str r3, [r4, #-2716]
+ bl FtlGcReFreshBadBlk
+ ldr r3, .L3507+20
+ mov r2, r10
+ ldrh r3, [r3, #-4]
+ cmp r3, r5
+ bne .L3351
+ ldrh r1, [r6, #-10]
cmp r1, r3
- bgt .L3434
- add r1, r0, #1
- str ip, [sp, #28]
- str r2, [sp, #24]
- mov r9, #0
- uxth r1, r1
- str r9, [r10, #-4]
- strh r1, [r10, #-8] @ movhi
- str r1, [sp, #20]
+ bne .L3438
+ ldr r3, [r4, #-2716]
+ cmp r3, #1024
+ bhi .L3353
+ ldrh r3, [r8, #-4]
+ cmp r3, #63
+ bhi .L3438
+.L3353:
+ ldr r6, .L3507+24
+ mov r1, #0
+ ldrh r0, [r8, #-4]
+ strh r1, [r2] @ movhi
+ ldrh r3, [r6, #-14]
+ add r3, r3, #64
+ cmp r0, r3
+ bgt .L3438
+ ldr r3, [r4, #-3308]
+ str r1, [r4, #-2716]
+ cmp r3, r1
+ moveq r3, #6
+ beq .L3499
+ cmp r3, #5
+ bhi .L3355
+ mov r3, #18
+.L3499:
+ strh r3, [r2] @ movhi
+.L3355:
+ mov r0, #32
+ movw r10, #65535
bl List_get_gc_head_node
- ldr ip, [sp, #28]
- uxth fp, r0
- ldr r1, [sp, #20]
- cmp fp, ip
- ldr r2, [sp, #24]
- beq .L3434
- mov ip, fp, asl #1
- ldr r0, .L3583+28
- str ip, [sp, #20]
- ldrh r3, [r2, ip]
- ldrh r2, [r2, r8]
- str r2, [sp]
- mov r2, fp
+ uxth r3, r0
+ cmp r3, r10
+ beq .L3359
+ ldrh ip, [r6, #-8]
+ cmp ip, #0
+ beq .L3357
+ movw r2, #2392
+ uxth r0, r0
+ ldrh lr, [r9, r2]
+ movw r2, #2324
+ ldrh r2, [r9, r2]
+ lsl r1, r0, #1
+ ldr r3, [r4, #-3540]
+ str r1, [sp, #12]
+ mul r2, r2, lr
+ ldrh r0, [r3, r1]
+ str r3, [sp, #8]
+ add r2, r2, #1
+ cmp r0, r2
+ bgt .L3359
+ add fp, ip, #1
+ mov r9, #0
+ uxth fp, fp
+ mov r0, ip
+ str r9, [r4, #-2708]
+ strh fp, [r6, #-8] @ movhi
+ bl List_get_gc_head_node
+ uxth r5, r0
+ ldr r3, [sp, #8]
+ ldr r1, [sp, #12]
+ cmp r5, r10
+ beq .L3359
+ lsl r10, r5, #1
+ mov r2, r5
+ ldrh r0, [r3, r10]
+ ldrh r3, [r3, r1]
+ mov r1, fp
+ str r3, [sp]
+ mov r3, r0
+ ldr r0, .L3507+28
bl printk
- ldrh r3, [r10, #-8]
+ ldrh r3, [r6, #-8]
cmp r3, #40
- ldr ip, [sp, #20]
- bls .L3432
- ldr r3, [r10, #-840]
- ldrh r3, [r3, ip]
+ bls .L3358
+ ldr r3, [r4, #-3540]
+ ldrh r3, [r3, r10]
cmp r3, #32
- strhih r9, [r10, #-8] @ movhi
-.L3432:
- ldr r3, .L3583+20
+ strhhi r9, [r6, #-8] @ movhi
+.L3358:
+ ldr r3, .L3507+16
mov r2, #6
strh r2, [r3] @ movhi
- b .L3436
-.L3431:
+.L3351:
+ movw r0, #65535
+ ldr r3, [sp, #16]
+ sub r2, r5, r0
+ clz r2, r2
+ lsr r2, r2, #5
+ cmp r3, #0
+ movne r1, #0
+ andeq r1, r2, #1
+ cmp r1, #0
+ beq .L3373
+ ldrh r3, [r8, #-4]
+ cmp r3, #24
+ movhi r6, #1
+ bhi .L3374
+ ldr r1, .L3507+12
+ movw r2, #2390
+ cmp r3, #16
+ ldrh r6, [r1, r2]
+ lsrhi r6, r6, #5
+ bhi .L3374
+ cmp r3, #12
+ lsrhi r6, r6, #4
+ bhi .L3374
+ cmp r3, #8
+ lsrhi r6, r6, #2
+.L3374:
+ ldr r1, .L3507+32
+ ldrh r2, [r1]
+ cmp r2, r3
+ mov r2, r1
+ bcs .L3378
+ sub r3, r1, #704
+ movw r0, #65535
+ ldrh r3, [r3]
+ cmp r3, r0
+ bne .L3379
+ ldrh r0, [r1, #54]
+ cmp r0, r3
+ bne .L3379
+ ldr r3, .L3507+16
+ ldrh r0, [r3]
+ cmp r0, #0
+ bne .L3380
+ ldr r3, .L3507+12
+ ldr ip, [r4, #-3368]
+ ldr r3, [r3, #2452]
+ add r3, r3, r3, lsl #1
+ cmp ip, r3, lsr #2
+ movcs r3, #18
+ strhcs r3, [r1] @ movhi
+ bcs .L3382
+.L3380:
+ ldr r3, .L3507+36
+ ldrh r3, [r3, #-8]
+ add r3, r3, r3, lsl #1
+ asr r3, r3, #2
+ strh r3, [r2] @ movhi
+.L3382:
+ mov r3, #0
+ str r3, [r4, #-2708]
+.L3343:
+ add sp, sp, #44
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3345:
+ sub r3, r3, #3424
+ ldrh r3, [r3]
+ cmp r3, r2
+ beq .L3348
+ mov r0, r5
+ bl FtlGcFreeTempBlock
+ cmp r0, #0
+ beq .L3348
+ mov r0, r5
+ b .L3343
+.L3346:
+ ldrh r3, [r6, #-10]
+ cmp r3, r2
+ bne .L3347
+ ldrh r1, [r6, #-6]
+ cmp r1, r3
+ beq .L3347
+ ldrh r2, [r6, #-4]
+ cmp r2, r3
+ mvnne r3, #0
+ strhne r0, [r6, #-10] @ movhi
+ strhne r1, [r6, #-8] @ movhi
+ strhne r2, [r6, #-6] @ movhi
+ strhne r3, [r6, #-4] @ movhi
+ b .L3347
+.L3357:
mov r3, #1
- strh r3, [r10, #-8] @ movhi
-.L3434:
+ strh r3, [r6, #-8] @ movhi
+.L3359:
bl GetSwlReplaceBlock
movw r3, #65535
+ mov r5, r0
cmp r0, r3
- mov fp, r0
- bne .L3436
- ldr r3, .L3583+20
+ bne .L3351
+ ldr r3, .L3507+16
mov r2, #0
strh r2, [r3] @ movhi
-.L3435:
- ldrh ip, [r6, #-4]
+.L3349:
+ ldr r3, .L3507+20
+ movw r5, #65535
+ ldrh r3, [r3, #-4]
+ cmp r3, r5
+ bne .L3351
+.L3438:
+ ldr r6, .L3507+40
movw r3, #65535
- ldr r8, .L3583
- cmp ip, r3
- bne .L3577
- sub r3, r8, #3424
- ldrh r3, [r3, #-4]
- cmp r3, ip
- movne fp, ip
- beq .L3580
-.L3436:
- movw r1, #65535
- rsb r3, r1, fp
- clz r3, r3
- ldr r2, [sp, #16]
- ldr r8, .L3583+32
- mov r3, r3, lsr #5
- cmp r2, #0
- movne ip, #0
- andeq ip, r3, #1
- cmp ip, #0
- beq .L3449
- ldrh r0, [r8, #-8]
- cmp r0, #24
- movhi r9, #1
- bhi .L3450
- ldr r2, .L3583+16
- movw r3, #2388
- cmp r0, #16
- ldrh r9, [r2, r3]
- movhi r9, r9, lsr #5
- bhi .L3450
- cmp r0, #12
- movhi r9, r9, lsr #4
- bhi .L3450
- cmp r0, #8
- movhi r9, r9, lsr #2
-.L3450:
- ldr r1, .L3583
- sub r2, r1, #2720
- ldrh r3, [r2]
- cmp r3, r0
- bcs .L3454
- sub r3, r1, #3424
- movw r0, #65535
- ldrh r3, [r3, #-4]
- cmp r3, r0
- bne .L3455
- ldrh r0, [r4, #-10]
- cmp r0, r3
- bne .L3455
- ldr r3, .L3583+20
- ldrh r0, [r3]
- cmp r0, #0
- bne .L3456
- ldr r3, .L3583+16
- ldr r1, [r1, #-3372]
- ldr r3, [r3, #2448]
- add r3, r3, r3, asl #1
- cmp r1, r3, lsr #2
- movcs r3, #18
- bcs .L3457
-.L3456:
- ldr r3, .L3583+36
- ldrh r3, [r3, #-8]
- add r3, r3, r3, asl #1
- ubfx r3, r3, #2, #16
-.L3457:
- strh r3, [r2] @ movhi
+ ldrh r5, [r6]
+ cmp r5, r3
+ movne r5, r3
+ bne .L3351
+ add r3, r6, #768
+ ldrh r9, [r3, #-10]
+ cmp r9, r5
+ bne .L3351
+ ldrh r3, [r8, #-4]
+ ldr r2, [r4, #-2716]
+ cmp r3, #24
+ movcc r3, #5120
+ movcs r3, #1024
+ cmp r2, r3
+ bls .L3351
+ ldr r2, .L3507+16
mov r3, #0
- str r3, [r5, #-2708]
- b .L3572
-.L3455:
- ldr r3, .L3583+36
- ldrh r3, [r3, #-8]
- add r3, r3, r3, asl #1
- mov r3, r3, asr #2
+ str r3, [r4, #-2716]
strh r3, [r2] @ movhi
-.L3454:
- ldr r3, .L3583+16
- movw fp, #65535
- ldr r2, [r3, #2244]
- ldr r3, [sp, #12]
- cmp r3, #2
- movhi r3, #0
- movls r3, #1
+ bl GetSwlReplaceBlock
+ cmp r0, r9
+ mov r5, r0
+ movne r10, r0
+ bne .L3361
+ add r6, r6, #720
+ ldrh r2, [r8, #-4]
+ ldrh r3, [r6, #-14]
+ mov r9, r6
+ cmp r2, r3
+ movcs r3, #80
+ strhcs r3, [r6, #-14] @ movhi
+ bcs .L3364
+ mov r0, #64
+ bl List_get_gc_head_node
+ uxth r3, r0
+ cmp r3, r5
+ beq .L3364
+ ldr r3, [r4, #-564]
+ ldr r6, .L3507+12
+ cmp r3, #0
+ uxth r3, r0
+ bne .L3365
+ movw r2, #2344
+ ldrh r2, [r6, r2]
+ cmp r2, #3
+ beq .L3365
+ ldr r2, [r4, #-2724]
cmp r2, #0
- moveq r3, #0
- cmp r3, #0
- addne r9, r9, #1
- uxthne r9, r9
- b .L3459
-.L3449:
- ldrh r0, [r8, #92]
- add r2, r8, #3520
- cmp r0, r1
- bne .L3460
- ldrh r1, [r4, #-10]
- cmp r1, r0
+ bne .L3365
+ ldr r2, [r6, #2248]
+ cmp r2, #0
+ bne .L3365
+ ldrb r0, [r6, #152] @ zero_extendqisi2
+ cmp r0, #0
+ beq .L3366
+.L3365:
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
+ movw r0, #2344
+ ldrh r0, [r6, r0]
+ ldrh r1, [r2, r3]
+ movw r3, #2392
+ movw r2, #2324
+ ldrh r3, [r6, r3]
+ ldrh r2, [r6, r2]
+ cmp r0, #3
+ mul r2, r3, r2
+ lsreq r3, r3, #1
movne r3, #0
- andeq r3, r3, #1
- cmp r3, #0
- beq .L3460
- ldrh r3, [r6, #-4]
- cmp r3, r0
- beq .L3461
-.L3465:
- movw fp, #65535
- b .L3460
-.L3461:
- sub r10, r2, #2720
- ldrh r1, [r7, #-8]
- str ip, [r2, #-2708]
- ldrh r3, [r10]
- ldr r9, .L3583+20
+ add r3, r3, r2
cmp r1, r3
- bls .L3462
- ldrh r3, [r9]
+ bgt .L3368
+ mov r0, #0
+ bl List_get_gc_head_node
+ ldr r3, [r6, #2452]
+ uxth r10, r0
+ ldr r2, [r4, #-3368]
+ add r3, r3, r3, lsl #1
+ cmp r2, r3, lsr #2
+ movls r3, #160
+ bls .L3500
+.L3501:
+ mov r3, #128
+.L3500:
+ strh r3, [r9, #-14] @ movhi
+ movw r3, #65535
+ cmp r10, r3
+ beq .L3364
+.L3361:
+ ldr r0, .L3507+32
+ lsl r1, r10, #1
+ ldr r3, [r4, #-3540]
+ mov r5, r10
+ ldrh r2, [r8, #-4]
+ ldrh r0, [r0]
+ ldrh r3, [r3, r1]
+ str r0, [sp, #4]
+ ldr r0, [r4, #-3604]
+ ldrh r1, [r0, r1]
+ ldr r0, .L3507+44
+ str r1, [sp]
+ mov r1, r10
+ bl printk
+ b .L3364
+.L3368:
+ mov r3, #128
+.L3502:
+ strh r3, [r9, #-14] @ movhi
+.L3364:
+ bl FtlGcReFreshBadBlk
+ b .L3351
+.L3366:
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
+ ldrh r3, [r2, r3]
+ cmp r3, #7
+ bhi .L3371
+ bl List_get_gc_head_node
+ uxth r10, r0
+ b .L3501
+.L3371:
+ mov r3, #64
+ b .L3502
+.L3379:
+ ldr r3, .L3507+36
+ ldrh r3, [r3, #-8]
+ add r3, r3, r3, lsl #1
+ asr r3, r3, #2
+ strh r3, [r2] @ movhi
+.L3378:
+ ldr r3, .L3507+12
+ movw r5, #65535
+ ldr r3, [r3, #2248]
+ adds r3, r3, #0
+ movne r3, #1
+ cmp r7, #2
+ movhi r3, #0
cmp r3, #0
- bne .L3463
- ldr r3, .L3583+16
- ldr r2, [r2, #-3372]
- ldr r3, [r3, #2448]
- add r3, r3, r3, asl #1
+ addne r6, r6, #1
+ uxthne r6, r6
+.L3384:
+ ldr r7, .L3507+20
+ movw r2, #65535
+ ldrh r3, [r7, #-4]
+ cmp r3, r2
+ bne .L3394
+ cmp r5, r3
+ strhne r5, [r7, #-4] @ movhi
+ bne .L3396
+ add r3, r7, #624
+ ldrh r2, [r3, #-10]
+ cmp r2, r5
+ beq .L3396
+ ldr r1, [r4, #-3540]
+ lsl r2, r2, #1
+ ldrh r2, [r1, r2]
+ cmp r2, #0
+ mvneq r2, #0
+ strheq r2, [r3, #-10] @ movhi
+ ldrh r2, [r3, #-10]
+ strh r2, [r7, #-4] @ movhi
+ mvn r2, #0
+ strh r2, [r3, #-10] @ movhi
+.L3396:
+ ldrh r0, [r7, #-4]
+ mov r3, #0
+ strb r3, [r4, #-3276]
+ movw r3, #65535
+ cmp r0, r3
+ beq .L3394
+ bl IsBlkInGcList
+ cmp r0, #0
+ mvnne r3, #0
+ strhne r3, [r7, #-4] @ movhi
+ ldr r3, .L3507+12
+ ldrb r3, [r3, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L3400
+ ldrh r0, [r7, #-4]
+ bl ftl_get_blk_mode
+ strb r0, [r4, #-3276]
+.L3400:
+ ldrh r2, [r7, #-4]
+ movw r3, #65535
+ sub r9, r7, #4
+ cmp r2, r3
+ beq .L3394
+ mov r0, r9
+ bl make_superblock
+ mov r3, #0
+ movw r2, #1986
+ strh r3, [r4, r2] @ movhi
+ strh r3, [r7, #-2] @ movhi
+ strb r3, [r4, #-3278]
+ ldrh r3, [r7, #-4]
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
+ ldrh r2, [r2, r3]
+ movw r3, #1988
+ strh r2, [r4, r3] @ movhi
+.L3394:
+ ldrh r3, [r7, #-4]
+ ldrh r2, [r8]
+ cmp r2, r3
+ beq .L3401
+ ldr r2, .L3507+48
+ ldrh r1, [r2]
+ cmp r1, r3
+ beq .L3401
+ ldrh r2, [r2, #48]
+ cmp r2, r3
+ bne .L3402
+.L3401:
+ mvn r3, #0
+ strh r3, [r7, #-4] @ movhi
+.L3402:
+ ldr r4, .L3507
+ sub r7, r4, #3280
+.L3435:
+ ldrh r2, [r7, #-4]
+ movw r3, #65535
+ cmp r2, r3
+ bne .L3403
+ ldr r9, .L3507+24
+ mov r3, #0
+ ldr r10, .L3507+52
+ str r3, [r4, #-2708]
+.L3404:
+ ldr fp, .L3507+56
+ ldrh r8, [fp]
+ mov r0, r8
+ bl List_get_gc_head_node
+ uxth r2, r0
+ sub r1, fp, #568
+ strh r2, [r1, #-4] @ movhi
+ movw r1, #65535
+ cmp r2, r1
+ bne .L3405
+ mov r3, #0
+ mov r0, #8
+ strh r3, [fp] @ movhi
+ b .L3343
+.L3373:
+ ldr r3, .L3507+40
+ ldrh r7, [r3]
+ cmp r7, r0
+ bne .L3385
+ add r0, r3, #768
+ ldrh r0, [r0, #-10]
+ cmp r0, r7
+ movne r2, #0
+ andeq r2, r2, #1
+ cmp r2, #0
+ beq .L3385
+ ldrh r2, [r3, #140]
+ cmp r2, r7
+ beq .L3386
+.L3391:
+ mov r5, r7
+.L3385:
+ ldr r3, .L3507+12
+ ldr r3, [r3, #2248]
+ cmp r3, #0
+ moveq r6, #1
+ movne r6, #2
+ b .L3384
+.L3386:
+ add r5, r3, #704
+ ldrh r2, [r8, #-4]
+ ldrh r3, [r5]
+ str r1, [r4, #-2708]
+ ldr r6, .L3507+16
+ cmp r2, r3
+ bls .L3387
+ ldrh r3, [r6]
+ cmp r3, #0
+ bne .L3388
+ ldr r3, .L3507+12
+ ldr r2, [r4, #-3368]
+ ldr r3, [r3, #2452]
+ add r3, r3, r3, lsl #1
cmp r2, r3, lsr #2
movcs r3, #18
- bcs .L3464
-.L3463:
- ldr r3, .L3583+36
+ bcs .L3503
+.L3388:
+ ldr r3, .L3507+36
ldrh r3, [r3, #-8]
- add r3, r3, r3, asl #1
- ubfx r3, r3, #2, #16
-.L3464:
- strh r3, [r10] @ movhi
+ add r3, r3, r3, lsl #1
+ asr r3, r3, #2
+.L3503:
+ strh r3, [r5] @ movhi
bl FtlReadRefresh
mov r0, #0
bl List_get_gc_head_node
- ldr r3, [r5, #-3544]
uxth r0, r0
- mov r0, r0, asl #1
+ ldr r3, [r4, #-3540]
+ lsl r0, r0, #1
ldrh r3, [r3, r0]
cmp r3, #4
- ldrhih r0, [r9]
- bhi .L3572
-.L3462:
- ldrh r0, [r9]
+ bls .L3387
+.L3504:
+ ldrh r0, [r6]
+ b .L3343
+.L3387:
+ ldrh r0, [r6]
cmp r0, #0
- bne .L3465
- ldr r3, .L3583+36
+ bne .L3391
+ ldr r3, .L3507+36
ldrh r9, [r3, #-8]
- add r3, r9, r9, asl #1
- mov r3, r3, asr #2
- strh r3, [r10] @ movhi
+ add r3, r9, r9, lsl #1
+ asr r3, r3, #2
+ strh r3, [r5] @ movhi
bl List_get_gc_head_node
- ldr r3, [r5, #-3544]
- movw r2, #2390
uxth r0, r0
- mov r0, r0, asl #1
+ ldr r3, [r4, #-3540]
+ ldr r2, .L3507+12
+ lsl r0, r0, #1
ldrh r1, [r3, r0]
- ldr r3, .L3583+16
- ldrh r2, [r3, r2]
- add r3, r3, #2320
- ldrh r3, [r3]
- mul r3, r3, r2
+ movw r3, #2392
+ ldrh r0, [r2, r3]
+ movw r3, #2324
+ ldrh r3, [r2, r3]
+ mul r3, r3, r0
add r3, r3, r3, lsr #31
cmp r1, r3, asr #1
- ble .L3466
- ldrh r3, [r7, #-8]
- sub r2, r9, #1
- cmp r3, r2
- blt .L3466
- bl FtlReadRefresh
- b .L3578
-.L3466:
- cmp r1, #0
- bne .L3465
- movw r0, #65535
- bl decrement_vpc_count
- ldrh r0, [r8, #-8]
- add r0, r0, #1
- b .L3572
-.L3460:
- ldr r3, .L3583+16
- ldr r3, [r3, #2244]
- cmp r3, #0
- moveq r9, #1
- movne r9, #2
-.L3459:
- ldrh r3, [r6, #-4]
- movw r0, #65535
- ldr r2, .L3583
- cmp r3, r0
- sub r1, r2, #3280
- bne .L3468
- cmp fp, r3
- strneh fp, [r1, #-4] @ movhi
- bne .L3470
- ldrh r3, [r4, #-10]
- sub r1, r2, #2656
- cmp r3, fp
- beq .L3470
- ldr r2, [r2, #-3544]
- mov r3, r3, asl #1
- ldrh r3, [r2, r3]
- cmp r3, #0
- mvneq r3, #0
- streqh r3, [r1, #-10] @ movhi
- ldrh r3, [r4, #-10]
- strh r3, [r6, #-4] @ movhi
- mvn r3, #0
- strh r3, [r4, #-10] @ movhi
-.L3470:
- ldrh r0, [r6, #-4]
- mov r3, #0
- strb r3, [r5, #-3276]
- movw r3, #65535
- cmp r0, r3
- beq .L3468
- bl IsBlkInGcList
- cmp r0, #0
- ldrne r3, .L3583+12
- mvnne r2, #0
- strneh r2, [r3, #-4] @ movhi
- ldr r3, .L3583+16
- ldrb r3, [r3, #144] @ zero_extendqisi2
- cmp r3, #0
- beq .L3474
- ldrh r0, [r6, #-4]
- bl ftl_get_blk_mode
- strb r0, [r5, #-3276]
-.L3474:
- ldrh r2, [r6, #-4]
- movw r3, #65535
- ldr r5, .L3583
- cmp r2, r3
- sub r7, r5, #3280
- sub r4, r7, #4
- beq .L3468
- mov r0, r4
- bl make_superblock
- ldr r2, .L3583+40
- movw r1, #1986
- mov r3, #0
- strh r3, [r7, #-2] @ movhi
- strh r3, [r2, r1] @ movhi
- strb r3, [r5, #-3278]
- ldrh r3, [r7, #-4]
- ldr r1, [r5, #-3544]
- mov r3, r3, asl #1
- ldrh r1, [r1, r3]
- movw r3, #1988
- strh r1, [r2, r3] @ movhi
-.L3468:
- ldrh r3, [r6, #-4]
+ ble .L3392
ldrh r2, [r8, #-4]
+ sub r3, r9, #1
cmp r2, r3
- beq .L3475
- ldr r2, .L3583+44
- ldrh r1, [r2, #-4]
- cmp r1, r3
- beq .L3475
- ldrh r2, [r2, #44]
- cmp r2, r3
- bne .L3509
-.L3475:
- mvn r3, #0
- strh r3, [r6, #-4] @ movhi
-.L3509:
- ldr r6, .L3583+48
- movw r3, #65535
- ldr r5, .L3583
- ldrh r2, [r6]
- mov r10, r6
- cmp r2, r3
- bne .L3477
- mov r3, #0
- str r5, [sp, #12]
- str r3, [r5, #-2708]
-.L3478:
- ldr r8, .L3583+52
- ldrh r4, [r8]
- mov r0, r4
- bl List_get_gc_head_node
- movw r3, #65535
- uxth r7, r0
- strh r7, [r10] @ movhi
- cmp r7, r3
- moveq r3, #0
- moveq r0, #8
- streqh r3, [r8] @ movhi
- beq .L3572
-.L3479:
- mov r0, r7
- add r4, r4, #1
- bl IsBlkInGcList
- cmp r0, #0
- ldrne r3, .L3583+52
- strneh r4, [r3] @ movhi
- bne .L3478
- ldr r3, .L3583+52
- uxth r4, r4
- mov r2, r7, asl #1
- strh r4, [r3] @ movhi
- ldr r3, [sp, #12]
- ldr r1, [r3, #-3544]
- ldr r3, .L3583+56
- ldrh r0, [r1, r2]
- ldrh ip, [r3]
- ldrh r3, [r3, #-68]
- mul r3, r3, ip
- add ip, r3, r3, lsr #31
- cmp r0, ip, asr #1
- bgt .L3482
- cmp r0, #8
- cmphi r4, #48
- bls .L3483
- ldrh r0, [r8, #36]
- cmp r0, #35
- bhi .L3483
-.L3482:
- ldr ip, .L3583+52
- mov r0, #0
- strh r0, [ip] @ movhi
-.L3483:
- ldrh r2, [r1, r2]
- movw r1, #65535
- cmp r2, r3
- cmpge fp, r1
- bne .L3484
- ldr r3, .L3583+52
- ldrh r1, [r3]
- cmp r1, #3
- bhi .L3484
- sub r2, r3, #568
- mvn r1, #0
- strh r1, [r2, #-4] @ movhi
- mov r2, #0
- strh r2, [r3] @ movhi
-.L3578:
- ldr r3, .L3583+20
- ldrh r0, [r3]
- b .L3572
-.L3484:
- cmp r2, #0
- bne .L3485
+ blt .L3392
+ bl FtlReadRefresh
+ b .L3504
+.L3392:
+ cmp r1, #0
+ bne .L3391
movw r0, #65535
bl decrement_vpc_count
- ldr r3, .L3583+52
- ldr r2, .L3583+52
+ ldrh r0, [r8, #-4]
+ add r0, r0, #1
+ b .L3343
+.L3405:
+ str r0, [sp, #12]
+ mov r0, r2
+ str r2, [sp, #8]
+ add r8, r8, #1
+ bl IsBlkInGcList
+ cmp r0, #0
+ ldr r2, [sp, #8]
+ ldr r3, [sp, #12]
+ strhne r8, [fp] @ movhi
+ bne .L3404
+ uxth r3, r3
+ ldrh lr, [r10]
+ ldr r0, [r4, #-3540]
+ uxth r8, r8
+ lsl r1, r3, #1
+ ldr r3, .L3507+60
+ strh r8, [fp] @ movhi
+ ldrh ip, [r0, r1]
ldrh r3, [r3]
+ mul r3, r3, lr
+ add lr, r3, r3, lsr #31
+ cmp ip, lr, asr #1
+ bgt .L3408
+ cmp r8, #48
+ cmphi ip, #8
+ bls .L3409
+ ldrh ip, [fp, #36]
+ cmp ip, #35
+ bhi .L3409
+.L3408:
+ mov ip, #0
+ strh ip, [r9, #-8] @ movhi
+.L3409:
+ ldrh r1, [r0, r1]
+ movw r0, #65535
+ cmp r3, r1
+ cmple r5, r0
+ bne .L3410
+ ldrh r0, [r9, #-8]
+ cmp r0, #3
+ bhi .L3410
+ ldr r1, .L3507+20
+ mvn r2, #0
+ strh r2, [r1, #-4] @ movhi
+ mov r2, #0
+ strh r2, [r9, #-8] @ movhi
+.L3506:
+ ldr r3, .L3507+16
+ b .L3505
+.L3410:
+ cmp r1, #0
+ bne .L3411
+ movw r0, #65535
+ bl decrement_vpc_count
+ ldrh r3, [r9, #-8]
add r3, r3, #1
- strh r3, [r2] @ movhi
- b .L3478
-.L3485:
+ strh r3, [r9, #-8] @ movhi
+ b .L3404
+.L3411:
mov r3, #0
- strb r3, [r5, #-3276]
- ldr r3, .L3583+16
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ strb r3, [r4, #-3276]
+ ldr r3, .L3507+12
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3486
- mov r0, r7
+ beq .L3412
+ mov r0, r2
bl ftl_get_blk_mode
- ldr r3, .L3583
- strb r0, [r3, #-3276]
-.L3486:
- ldr r0, .L3583+48
+ strb r0, [r4, #-3276]
+.L3412:
+ ldr r3, .L3507+20
+ sub r8, r3, #4
+ mov r0, r8
bl make_superblock
- ldrh r2, [r6]
- ldr r1, .L3583+60
+ add r2, r8, #4
+ ldr r1, .L3507+64
+ ldrh r2, [r2, #-4]
mov r3, #0
- ldr r0, [r5, #-3544]
- mov r2, r2, asl #1
+ ldr r0, [r4, #-3540]
strh r3, [r1] @ movhi
+ lsl r2, r2, #1
ldrh r2, [r0, r2]
- strh r3, [r6, #2] @ movhi
- strb r3, [r5, #-3278]
+ strh r3, [r8, #2] @ movhi
+ strb r3, [r4, #-3278]
strh r2, [r1, #2] @ movhi
-.L3477:
+.L3403:
ldr r3, [sp, #16]
cmp r3, #1
- bne .L3487
+ bne .L3413
bl FtlReadRefresh
-.L3487:
+.L3413:
mov r3, #1
- str r3, [r5, #-560]
- ldr r3, .L3583+56
+ str r3, [r4, #-560]
+ ldr r3, .L3507+52
ldrh r3, [r3]
- str r3, [sp, #12]
- ldr r3, .L3583+16
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ str r3, [sp, #8]
+ ldr r3, .L3507+12
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3488
- ldr r3, .L3583
- ldrb r3, [r3, #-3276] @ zero_extendqisi2
+ beq .L3414
+ ldrb r3, [r4, #-3276] @ zero_extendqisi2
cmp r3, #1
- ldreq r3, .L3583+64
- ldreqh r3, [r3]
- streq r3, [sp, #12]
-.L3488:
- ldrh r3, [r6, #2]
- mov r6, #0
- ldr r1, [sp, #12]
- add r2, r3, r9
- ldr r4, .L3583
+ ldreq r3, .L3507+68
+ ldrheq r3, [r3]
+ streq r3, [sp, #8]
+.L3414:
+ ldr r3, .L3507+20
+ ldr r1, [sp, #8]
+ ldrh r3, [r3, #-2]
+ add r2, r3, r6
cmp r2, r1
movgt r2, r1
- rsbgt r3, r3, r2
- uxthgt r9, r3
-.L3490:
- uxth r3, r6
- ldr r7, .L3583
- cmp r3, r9
- ldr r5, .L3583+48
- bcs .L3497
- ldr r3, .L3583+24
- add r0, r5, #14
- ldrh r1, [r5, #2]
- movw lr, #65535
- ldr r7, [r4, #-2688]
- mov ip, #36
- ldrh r8, [r3]
- add r1, r1, r6
+ subgt r6, r2, r3
mov r3, #0
- mov r5, r3
-.L3498:
- uxth r2, r3
- cmp r2, r8
- bcs .L3581
- ldrh r2, [r0, #2]!
- add r3, r3, #1
- cmp r2, lr
- orrne r2, r1, r2, asl #10
- mlane r10, ip, r5, r7
- addne r5, r5, #1
- uxthne r5, r5
- strne r2, [r10, #4]
- b .L3498
-.L3581:
+ uxthgt r6, r6
+ str r3, [sp, #12]
+ sub r3, r7, #4
+ str r3, [sp, #20]
+.L3416:
+ ldrh r3, [sp, #12]
+ cmp r6, r3
+ bls .L3423
+ ldr r3, .L3507+60
+ add ip, r7, #10
ldr r0, [r4, #-2688]
- mov r1, r5
+ movw r9, #65535
+ mov lr, #36
+ ldrh r10, [r3]
+ ldr r3, [sp, #20]
+ ldrh r1, [r3, #2]
+ ldr r3, [sp, #12]
+ add r1, r1, r3
+ mov r3, #0
+ mov r8, r3
+ b .L3424
+.L3418:
+ ldrh r2, [ip, #2]!
+ add r3, r3, #1
+ cmp r2, r9
+ mlane fp, lr, r8, r0
+ addne r8, r8, #1
+ orrne r2, r1, r2, lsl #10
+ uxthne r8, r8
+ strne r2, [fp, #4]
+.L3424:
+ uxth r2, r3
+ cmp r10, r2
+ bhi .L3418
+ mov fp, #0
ldrb r2, [r4, #-3276] @ zero_extendqisi2
- mov r8, #0
+ mov r1, r8
bl FlashReadPages
-.L3493:
- uxth r3, r8
- cmp r3, r5
- bcs .L3582
+.L3419:
+ uxth r3, fp
+ cmp r8, r3
+ ldrls r3, [sp, #12]
+ addls r3, r3, #1
+ strls r3, [sp, #12]
+ bls .L3416
+.L3422:
mov r3, #36
ldr r2, [r4, #-2688]
- mul r7, r3, r8
- add r1, r2, r7
- ldr r2, [r2, r7]
- ldr r10, [r1, #12]
+ mul r9, r3, fp
+ add r1, r2, r9
+ ldr r2, [r2, r9]
cmn r2, #1
- beq .L3529
- ldrh r1, [r10]
+ beq .L3420
+ ldr r10, [r1, #12]
movw r2, #61589
+ ldrh r1, [r10]
cmp r1, r2
- bne .L3529
- add r1, sp, #32
+ bne .L3420
mov r2, #0
+ add r1, sp, #32
ldr r0, [r10, #8]
- str r3, [sp, #20]
- bl log2phys
- ldr r2, [r4, #-2688]
- add r2, r2, r7
- ldr r0, [r2, #4]
- ldr r1, [sp, #32]
- ldr r3, [sp, #20]
- bic r1, r1, #-2147483648
- cmp r1, r0
- bne .L3529
- ldr r1, .L3583+60
- ldr r0, .L3583+60
- ldr r2, [r2, #16]
- ldrh r1, [r1]
str r3, [sp, #24]
- add r1, r1, #1
- strh r1, [r0] @ movhi
- ldr r0, [r4, #-2704]
- ldr r1, [r4, #-532]
- mla r1, r3, r0, r1
- str r2, [r1, #16]
- str r1, [sp, #20]
- bl Ftl_get_new_temp_ppa
- ldr r2, [r4, #-532]
- ldr r1, [sp, #20]
+ bl log2phys
+ ldr r1, [r4, #-2688]
+ ldr r2, [sp, #32]
ldr r3, [sp, #24]
- str r0, [r1, #4]
- ldr r1, [r4, #-2704]
- mla r3, r3, r1, r2
+ add r1, r1, r9
+ ldr r0, [r1, #4]
+ bic r2, r2, #-2147483648
+ cmp r2, r0
+ bne .L3420
+ ldr r2, .L3507+64
+ ldr r0, .L3507+64
+ ldr r1, [r1, #16]
+ ldrh r2, [r2]
+ str r3, [sp, #28]
+ add r2, r2, #1
+ strh r2, [r0] @ movhi
+ ldr r0, [r4, #-2704]
+ ldr r2, [r4, #-532]
+ mla r2, r3, r0, r2
+ str r1, [r2, #16]
+ str r2, [sp, #24]
+ bl Ftl_get_new_temp_ppa
+ ldr r2, [sp, #24]
+ ldr r1, [r4, #-532]
+ ldr r3, [sp, #28]
+ str r0, [r2, #4]
+ ldr r2, [r4, #-2704]
+ mla r3, r3, r2, r1
ldr r2, [r4, #-2688]
- add r2, r2, r7
+ add r2, r2, r9
ldr r1, [r2, #8]
str r1, [r3, #8]
mov r1, #1
@@ -21038,592 +21665,479 @@
str r2, [r3, #12]
ldr r3, [sp, #32]
str r3, [r10, #12]
- ldr r3, .L3583+68
+ ldr r3, .L3507+40
ldrh r3, [r3]
strh r3, [r10, #2] @ movhi
ldr r3, [r4, #-3328]
ldr r0, [r4, #-2688]
str r3, [r10, #4]
- add r0, r0, r7
ldr r3, [r4, #-2704]
+ add r0, r0, r9
add r3, r3, #1
str r3, [r4, #-2704]
bl FtlGcBufAlloc
- ldr r3, .L3583+16
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ ldr r3, .L3507+12
+ ldrb r3, [r3, #152] @ zero_extendqisi2
cmp r3, #0
- bne .L3495
- ldrb r3, [r4, #-3421] @ zero_extendqisi2
- ldr r2, [r4, #-2704]
+ bne .L3421
+ ldrb r2, [r4, #-3417] @ zero_extendqisi2
+ ldr r3, [r4, #-2704]
cmp r2, r3
- beq .L3495
- ldr r3, .L3583+68
+ beq .L3421
+ ldr r3, .L3507+40
ldrh r3, [r3, #4]
cmp r3, #0
- bne .L3529
-.L3495:
+ bne .L3420
+.L3421:
bl Ftl_gc_temp_data_write_back
cmp r0, #0
- beq .L3529
- ldr r3, .L3583
+ beq .L3420
+ ldr r3, .L3507
mov r2, #0
- mvn r1, #0
- sub r3, r3, #3280
- str r2, [r3, #2720]
- strh r1, [r3, #-4] @ movhi
- strh r2, [r3, #-2] @ movhi
- b .L3578
-.L3529:
- add r8, r8, #1
- b .L3493
-.L3582:
- add r6, r6, #1
- b .L3490
-.L3497:
- ldrh r3, [r5, #2]
- add r9, r9, r3
- ldr r3, [sp, #12]
- uxth r9, r9
- strh r9, [r5, #2] @ movhi
- cmp r9, r3
- bcc .L3499
- ldr r3, [r7, #-2704]
+ mvn ip, #0
+ sub r1, r3, #3280
+ str r2, [r3, #-560]
+ add r3, r3, #1984
+ strh ip, [r1, #-4] @ movhi
+ strh r2, [r1, #-2] @ movhi
+.L3505:
+ ldrh r0, [r3]
+ b .L3343
+.L3420:
+ add fp, fp, #1
+ b .L3419
+.L3423:
+ ldrh r3, [r7, #-2]
+ add r6, r6, r3
+ ldr r3, [sp, #8]
+ uxth r6, r6
+ cmp r3, r6
+ strh r6, [r7, #-2] @ movhi
+ bhi .L3425
+ ldr r3, [r4, #-2704]
cmp r3, #0
- beq .L3500
+ beq .L3426
bl Ftl_gc_temp_data_write_back
cmp r0, #0
movne r3, #0
- strne r3, [r7, #-560]
- bne .L3578
-.L3500:
- ldr r3, .L3583+60
- ldrh r4, [r3]
- cmp r4, #0
- bne .L3501
- ldrh r3, [r5]
- ldr r2, [r7, #-3544]
- mov r3, r3, asl #1
+ strne r3, [r4, #-560]
+ bne .L3506
+.L3426:
+ ldr r3, .L3507+64
+ ldrh r0, [r3]
+ cmp r0, #0
+ bne .L3427
+ ldrh r3, [r7, #-4]
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
ldrh r3, [r2, r3]
cmp r3, #0
- beq .L3501
- ldr r6, .L3583+16
-.L3502:
- ldr r3, [r6, #2448]
- cmp r4, r3
- bcs .L3507
- mov r0, r4
- add r1, sp, #36
+ movne r6, r0
+ ldrne r8, .L3507+12
+ bne .L3428
+.L3427:
+ mvn r3, #0
+ strh r3, [r7, #-4] @ movhi
+.L3425:
+ ldr r3, .L3507+72
+ ldrh r3, [r3]
+ cmp r3, #2
+ bhi .L3434
+ ldr r3, .L3507+52
+ ldrh r6, [r3]
+ b .L3435
+.L3429:
+ add r6, r6, #1
+.L3428:
+ ldr r3, [r8, #2452]
+ cmp r6, r3
+ bcs .L3433
mov r2, #0
+ add r1, sp, #36
+ mov r0, r6
bl log2phys
ldr r0, [sp, #36]
cmn r0, #1
- beq .L3503
+ beq .L3429
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
- ldrh r3, [r5]
+ ldrh r3, [r7, #-4]
cmp r3, r0
- bne .L3503
-.L3507:
- ldr r3, .L3583+16
- ldr r3, [r3, #2448]
- cmp r4, r3
- bcc .L3501
- ldrh r3, [r5]
+ bne .L3429
+.L3433:
+ ldr r3, [r8, #2452]
+ cmp r6, r3
+ bcc .L3427
+ ldrh r3, [r7, #-4]
mov r1, #0
- ldr r2, [r7, #-3544]
- mov r3, r3, asl #1
+ ldr r2, [r4, #-3540]
+ lsl r3, r3, #1
strh r1, [r2, r3] @ movhi
- ldrh r0, [r5]
+ ldrh r0, [r7, #-4]
bl update_vpc_list
bl FtlCacheWriteBack
bl l2p_flush
bl FtlVpcTblFlush
- b .L3501
-.L3503:
- add r4, r4, #1
- b .L3502
-.L3501:
- mvn r3, #0
- strh r3, [r5] @ movhi
-.L3499:
- ldr r3, .L3583+72
- ldrh r3, [r3]
- cmp r3, #2
- ldrls r3, .L3583+56
- ldrlsh r9, [r3]
- bls .L3509
-.L3508:
- ldr r2, .L3583
- mov r1, #0
- str r1, [r2, #-560]
- ldr r2, .L3583+20
+ b .L3427
+.L3434:
+ mov r2, #0
+ str r2, [r4, #-560]
+ ldr r2, .L3507+16
ldrh r0, [r2]
- cmp r0, r1
- addeq r0, r3, #1
- b .L3572
-.L3513:
- mov r0, #0
- bx lr
-.L3515:
- mov r0, ip
- b .L3572
-.L3580:
- ldrh r9, [r4, #-10]
- cmp r9, r3
- bne .L3577
- sub r3, r8, #3520
- ldr r2, [r8, #-2716]
- ldrh r3, [r3, #-8]
- cmp r3, #24
- movcc r3, #5120
- movcs r3, #1024
- cmp r2, r3
- movls fp, r9
- bls .L3436
- ldr r2, .L3583+20
- mov r3, #0
- str r3, [r5, #-2716]
- strh r3, [r2] @ movhi
- bl GetSwlReplaceBlock
- cmp r0, r9
- mov fp, r0
- bne .L3438
- sub r3, r8, #2704
- ldrh r1, [r7, #-8]
- ldrh r2, [r3, #-14]
- mov r9, r3
- cmp r1, r2
- movcs r2, #80
- strcsh r2, [r3, #-14] @ movhi
- bcs .L3448
- mov r0, #64
- bl List_get_gc_head_node
- uxth r3, r0
- cmp r3, fp
- beq .L3448
- ldr r2, [r8, #-564]
- ldr r10, .L3583+16
- cmp r2, #0
- bne .L3441
- movw r1, #2340
- ldrh r1, [r10, r1]
- cmp r1, #3
- beq .L3441
- ldr r1, [r8, #-3236]
- cmp r1, #0
- bne .L3441
- ldr r1, [r10, #2244]
- cmp r1, #0
- bne .L3441
- ldrb r0, [r10, #144] @ zero_extendqisi2
cmp r0, #0
- beq .L3442
-.L3441:
- ldr r2, [r5, #-3544]
- mov r3, r3, asl #1
- movw r0, #2340
- ldrh r0, [r10, r0]
- ldrh r1, [r2, r3]
- movw r3, #2390
- ldr r2, .L3583+24
- cmp r0, #3
- ldrh r3, [r10, r3]
- ldrh r2, [r2]
- mul r2, r2, r3
- moveq r3, r3, lsr #1
- movne r3, #0
- add r3, r2, r3
- cmp r1, r3
- bgt .L3444
+ addeq r0, r3, #1
+ b .L3343
+.L3439:
mov r0, #0
- bl List_get_gc_head_node
- ldr r3, [r10, #2448]
- ldr r2, [r5, #-3372]
- add r3, r3, r3, asl #1
- cmp r2, r3, lsr #2
- movls r3, #160
- uxth fp, r0
- bls .L3575
- b .L3579
-.L3442:
- ldr r2, [r8, #-3544]
- mov r3, r3, asl #1
- ldrh r3, [r2, r3]
- cmp r3, #7
- bhi .L3447
- bl List_get_gc_head_node
- uxth fp, r0
-.L3579:
- mov r3, #128
-.L3575:
- strh r3, [r9, #-14] @ movhi
- movw r3, #65535
- cmp fp, r3
- beq .L3448
- b .L3438
-.L3444:
- mov r3, #128
- b .L3576
-.L3447:
- mov r3, #64
-.L3576:
- strh r3, [r9, #-14] @ movhi
- b .L3448
-.L3438:
- ldr r0, [r5, #-3608]
- mov r1, fp, asl #1
- ldr r3, [r5, #-3544]
- ldrh r2, [r7, #-8]
- ldrh r3, [r3, r1]
- ldrh r1, [r0, r1]
- ldr r0, .L3583+76
- str r1, [sp]
- ldr r1, .L3583+80
- ldrh r1, [r1]
- str r1, [sp, #4]
- mov r1, fp
- bl printk
-.L3448:
- bl FtlGcReFreshBadBlk
- b .L3436
-.L3577:
- mov fp, r3
- b .L3436
-.L3572:
- add sp, sp, #44
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3584:
+ b .L3343
+.L3508:
.align 2
-.L3583:
+.L3507:
.word .LANCHOR2
.word .LANCHOR1
.word .LANCHOR2-2656
- .word .LANCHOR2-3280
.word .LANCHOR0
- .word .LANCHOR4+1984
- .word .LANCHOR0+2320
+ .word .LANCHOR2+1984
+ .word .LANCHOR2-3280
+ .word .LANCHOR2-2704
.word .LC157
- .word .LANCHOR2-3520
- .word .LANCHOR2-3296
- .word .LANCHOR4
- .word .LANCHOR2-3472
- .word .LANCHOR2-3284
- .word .LANCHOR2-2712
- .word .LANCHOR0+2388
- .word .LANCHOR4+1986
- .word .LANCHOR0+2390
- .word .LANCHOR2-3428
- .word .LANCHOR2-3528
- .word .LC158
.word .LANCHOR2-2720
+ .word .LANCHOR2-3296
+ .word .LANCHOR2-3424
+ .word .LC158
+ .word .LANCHOR2-3472
+ .word .LANCHOR0+2390
+ .word .LANCHOR2-2712
+ .word .LANCHOR0+2324
+ .word .LANCHOR2+1986
+ .word .LANCHOR0+2392
+ .word .LANCHOR2-3524
.fnend
.size ftl_do_gc, .-ftl_do_gc
.align 2
.global FtlCacheWriteBack
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlCacheWriteBack, %function
FtlCacheWriteBack:
.fnstart
- @ args = 0, pretend = 0, frame = 8
+ @ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #12
- ldr r3, .L3629
- ldr r7, .L3629+4
- ldr r5, [r3, #1992]
- ldr r3, [r7, #-3616]
- cmp r3, #0
- bne .L3587
- ldr r4, .L3629+8
- ldr r1, [r4, #2440]
+ .pad #20
+ sub sp, sp, #20
+ ldr r6, .L3552
+ ldr r9, [r6, #-3612]
+ cmp r9, #0
+ bne .L3511
+ ldr r4, .L3552+4
+ ldr r1, [r4, #2444]
cmp r1, #0
- beq .L3587
- ldrb r6, [r4, #144] @ zero_extendqisi2
- mov r8, #0
- ldr r0, [r4, #2444]
+ beq .L3511
+ ldrb r3, [r4, #152] @ zero_extendqisi2
+ mov r7, #0
+ ldr r5, [r6, #1992]
mov r10, #36
- cmp r6, #0
+ ldr fp, .L3552+8
+ cmp r3, #0
+ ldr r0, [r4, #2448]
+ ldrbne r8, [r5, #8] @ zero_extendqisi2
+ moveq r8, r9
ldrb r3, [r5, #9] @ zero_extendqisi2
- ldr r9, .L3629+8
- ldrneb r6, [r5, #8] @ zero_extendqisi2
- subne r6, r6, #1
- clzne r6, r6
- movne r6, r6, lsr #5
- mov r2, r6
+ subne r8, r8, #1
+ clzne r8, r8
+ lsrne r8, r8, #5
+ mov r2, r8
bl FlashProgPages
-.L3590:
- ldr r3, [r4, #2440]
- cmp r8, r3
- bcs .L3608
- mul fp, r10, r8
- ldr r3, [r9, #2444]
- add r2, r3, fp
- ldr r3, [r3, fp]
- cmn r3, #1
- beq .L3611
- ldr r3, [r2, #4]
- cmp r6, #0
- ldr r0, [r2, #16]
- add r1, sp, #4
- mov r2, #1
- orrne r3, r3, #-2147483648
- str r3, [sp, #4]
- bl log2phys
+.L3514:
ldr r3, [r4, #2444]
- add r3, r3, fp
+ cmp r7, r3
+ bcc .L3521
+.L3533:
+ mov r3, #0
+ str r3, [r4, #2444]
+.L3511:
+ mov r0, #0
+ add sp, sp, #20
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3521:
+ mul r3, r10, r7
+ ldr r2, [r4, #2448]
+ add r0, r2, r3
+ ldr r2, [r2, r3]
+ cmn r2, #1
+ beq .L3516
+ ldr r2, [r0, #4]
+ cmp r8, #0
+ add r1, sp, #12
+ ldr r0, [r0, #16]
+ str r3, [sp, #4]
+ orrne r2, r2, #-2147483648
+ str r2, [sp, #12]
+ mov r2, #1
+ bl log2phys
+ ldr r2, [r4, #2448]
+ ldr r3, [sp, #4]
+ add r3, r2, r3
ldr r3, [r3, #12]
ldr r0, [r3, #12]
cmn r0, #1
- beq .L3594
+ beq .L3519
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
- ldr r2, [r7, #-3544]
- mov r3, r0, asl #1
- mov fp, r0
+ ldr r1, [r6, #-3540]
+ lsl r2, r0, #1
+ mov r3, r0
+ ldrh r2, [r1, r2]
+ cmp r2, #0
+ bne .L3520
+ mov r1, r0
+ str r0, [sp, #4]
+ mov r0, fp
+ bl printk
+ ldr r3, [sp, #4]
+.L3520:
+ mov r0, r3
+ bl decrement_vpc_count
+.L3519:
+ add r7, r7, #1
+ b .L3514
+.L3531:
+ mov r7, #36
+ ldr r3, [r4, #2448]
+ mul r7, r7, r9
+ mov r10, #0
+ mov fp, #1
+ mvn r2, #0
+ str r2, [r3, r7]
+.L3522:
+ ldr r2, [r4, #2448]
+ add r3, r2, r7
+ ldr r2, [r2, r7]
+ ldr r0, [r3, #4]
+ cmn r2, #1
+ beq .L3526
+ cmp r8, #0
+ mov r2, #1
+ orrne r0, r0, #-2147483648
+ add r1, sp, #12
+ str r0, [sp, #12]
+ ldr r0, [r3, #16]
+ bl log2phys
+ ldr r3, [r4, #2448]
+ add r7, r3, r7
+ ldr r3, [r7, #12]
+ ldr r0, [r3, #12]
+ cmn r0, #1
+ beq .L3529
+ ubfx r0, r0, #10, #16
+ bl P2V_block_in_plane
+ ldr r2, [r6, #-3540]
+ lsl r3, r0, #1
+ mov r7, r0
ldrh r2, [r2, r3]
cmp r2, #0
- bne .L3595
- ldr r0, .L3629+12
- mov r1, fp
- bl printk
-.L3595:
- mov r0, fp
- bl decrement_vpc_count
-.L3594:
- add r8, r8, #1
- b .L3590
-.L3627:
- ldr r6, .L3629+16
- movw r5, #16386
-.L3607:
- ldrh r3, [r6]
- cmp r3, #0
- beq .L3608
- mov r0, #1
+ bne .L3530
mov r1, r0
+ ldr r0, .L3552+8
+ bl printk
+.L3530:
+ mov r0, r7
+ bl decrement_vpc_count
+.L3529:
+ add r9, r9, #1
+.L3516:
+ ldr r3, [r4, #2444]
+ cmp r9, r3
+ bcc .L3531
+ movw r5, #16386
+.L3534:
+ ldr r3, .L3552+12
+ ldrh r3, [r3]
+ cmp r3, #0
+ beq .L3533
+ mov r1, #1
+ mov r0, r1
bl ftl_do_gc
subs r5, r5, #1
- bne .L3607
-.L3608:
- mov r3, #0
- str r3, [r4, #2440]
- b .L3587
-.L3611:
- ldr fp, .L3629+8
- mov r9, #0
-.L3591:
- ldr r3, [r4, #2440]
- cmp r9, r3
- bcs .L3627
- mov r8, #36
- ldr r3, [fp, #2444]
- mul r8, r8, r9
- mov r10, #0
- mvn r2, #0
- str r2, [r3, r8]
-.L3597:
- ldr r3, [r4, #2444]
- add r2, r3, r8
- ldr r3, [r3, r8]
- cmn r3, #1
- bne .L3628
- ldr r0, [r2, #4]
+ bne .L3534
+ b .L3533
+.L3526:
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
ldrh r3, [r5]
cmp r3, r0
- bne .L3598
- ldr r1, [r7, #-3544]
- mov r3, r3, asl #1
+ bne .L3523
+ ldr r1, [r6, #-3540]
+ lsl r3, r3, #1
ldrh r0, [r5, #4]
ldrh r2, [r1, r3]
- rsb r2, r0, r2
+ sub r2, r2, r0
strh r2, [r1, r3] @ movhi
- ldr r3, .L3629+20
+ ldr r3, .L3552+16
strb r10, [r5, #6]
strh r10, [r5, #4] @ movhi
ldrh r3, [r3]
strh r3, [r5, #2] @ movhi
-.L3598:
+.L3523:
ldrh r3, [r5, #4]
cmp r3, #0
- bne .L3599
+ bne .L3524
mov r0, r5
bl allocate_new_data_superblock
-.L3599:
- ldr r3, [r7, #-3136]
+.L3524:
+ ldr r3, [r6, #-3140]
add r3, r3, #1
- str r3, [r7, #-3136]
- ldr r3, [r4, #2444]
- add r3, r3, r8
+ str r3, [r6, #-3140]
+ ldr r3, [r4, #2448]
+ add r3, r3, r7
ldr r0, [r3, #4]
ubfx r0, r0, #10, #16
bl FtlGcMarkBadPhyBlk
mov r0, r5
bl get_new_active_ppa
- ldr r3, [r4, #2444]
- mov r2, r6
+ ldr r3, [r4, #2448]
+ mov r2, r0
+ str r0, [sp, #12]
mov r1, #1
- add r3, r3, r8
- str r0, [sp, #4]
- str r0, [r3, #4]
- mov r0, r3
+ add r0, r3, r7
+ str r2, [r0, #4]
+ mov r2, r8
ldrb r3, [r5, #9] @ zero_extendqisi2
bl FlashProgPages
- ldr r3, [r4, #2444]
- ldr r3, [r3, r8]
+ ldr r3, [r4, #2448]
+ ldr r3, [r3, r7]
cmn r3, #1
- ldreq r2, .L3629+4
- moveq r3, #1
- streq r3, [r2, #-3616]
- ldr r3, [r7, #-3616]
+ streq fp, [r6, #-3612]
+ ldr r3, [r6, #-3612]
cmp r3, #0
- beq .L3597
- b .L3587
-.L3628:
- ldr r3, [r2, #4]
- cmp r6, #0
- ldr r0, [r2, #16]
- add r1, sp, #4
- mov r2, #1
- orrne r3, r3, #-2147483648
- str r3, [sp, #4]
- bl log2phys
- ldr r3, [r4, #2444]
- add r8, r3, r8
- ldr r3, [r8, #12]
- ldr r0, [r3, #12]
- cmn r0, #1
- beq .L3604
- ubfx r0, r0, #10, #16
- bl P2V_block_in_plane
- ldr r2, [r7, #-3544]
- mov r3, r0, asl #1
- mov r8, r0
- ldrh r2, [r2, r3]
- cmp r2, #0
- bne .L3605
- ldr r0, .L3629+12
- mov r1, r8
- bl printk
-.L3605:
- mov r0, r8
- bl decrement_vpc_count
-.L3604:
- add r9, r9, #1
- b .L3591
-.L3587:
- mov r0, #0
- add sp, sp, #12
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3630:
+ beq .L3522
+ b .L3511
+.L3553:
.align 2
-.L3629:
- .word .LANCHOR4
+.L3552:
.word .LANCHOR2
.word .LANCHOR0
.word .LC159
.word .LANCHOR2-2658
- .word .LANCHOR0+2388
+ .word .LANCHOR0+2390
.fnend
.size FtlCacheWriteBack, .-FtlCacheWriteBack
.align 2
.global FtlSysFlush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlSysFlush, %function
FtlSysFlush:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L3635
- ldr r3, [r3, #-3616]
+ ldr r3, .L3560
+ ldr r3, [r3, #-3612]
cmp r3, #0
- bne .L3634
- ldr r3, .L3635+4
- stmfd sp!, {r4, lr}
+ bne .L3557
+ ldr r3, .L3560+4
+ push {r4, lr}
.save {r4, lr}
- ldr r4, [r3, #504]
+ ldr r4, [r3, #500]
cmp r4, #1
- bne .L3632
+ bne .L3555
bl FtlCacheWriteBack
bl l2p_flush
mov r0, r4
bl FtlEctTblFlush
bl FtlVpcTblFlush
-.L3632:
+.L3555:
mov r0, #0
- ldmfd sp!, {r4, pc}
-.L3634:
+ pop {r4, pc}
+.L3557:
mov r0, #0
bx lr
-.L3636:
+.L3561:
.align 2
-.L3635:
+.L3560:
.word .LANCHOR2
.word .LANCHOR1
.fnend
.size FtlSysFlush, .-FtlSysFlush
.align 2
.global FtlDeInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlDeInit, %function
FtlDeInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
- ldr r3, .L3640
- ldr r3, [r3, #504]
+ ldr r3, .L3568
+ ldr r3, [r3, #500]
cmp r3, #1
- bne .L3638
+ bne .L3565
+ push {r4, lr}
+ .save {r4, lr}
bl FtlSysFlush
-.L3638:
mov r0, #0
- ldmfd sp!, {r3, pc}
-.L3641:
+ pop {r4, pc}
+.L3565:
+ mov r0, #0
+ bx lr
+.L3569:
.align 2
-.L3640:
+.L3568:
.word .LANCHOR1
.fnend
.size FtlDeInit, .-FtlDeInit
.align 2
.global ftl_deinit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_deinit, %function
ftl_deinit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
bl ftl_flash_de_init
bl FtlDeInit
- ldmfd sp!, {r3, lr}
+ pop {r4, lr}
b ftl_flash_de_init
.fnend
.size ftl_deinit, .-ftl_deinit
.align 2
.global rk_ftl_de_init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_de_init, %function
rk_ftl_de_init:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, lr}
- .save {r3, lr}
+ push {r4, lr}
+ .save {r4, lr}
mov r1, #0
- ldr r0, .L3646
+ ldr r0, .L3574
bl printk
- ldmfd sp!, {r3, lr}
+ pop {r4, lr}
b ftl_deinit
-.L3647:
+.L3575:
.align 2
-.L3646:
+.L3574:
.word .LC160
.fnend
.size rk_ftl_de_init, .-rk_ftl_de_init
.align 2
.global ftl_cache_flush
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_cache_flush, %function
ftl_cache_flush:
.fnstart
@@ -21635,6 +22149,9 @@
.size ftl_cache_flush, .-ftl_cache_flush
.align 2
.global rk_ftl_cache_write_back
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_cache_write_back, %function
rk_ftl_cache_write_back:
.fnstart
@@ -21646,74 +22163,89 @@
.size rk_ftl_cache_write_back, .-rk_ftl_cache_write_back
.align 2
.global ftl_discard
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_discard, %function
ftl_discard:
.fnstart
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
- .save {r4, r5, r6, r7, r8, r9, lr}
- .pad #12
+ push {r0, r1, r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
+ .pad #8
mov r6, r0
- ldr r8, .L3669
+ ldr r5, .L3596
+ ldr r3, [r5, #2432]
+ cmp r3, r1
+ cmpcs r3, r0
+ movls r0, #1
+ movhi r0, #0
+ bls .L3586
+ add r2, r6, r1
mov r4, r1
- ldr r3, [r8, #2428]
- cmp r1, r3
- cmpls r0, r3
- movcs r5, #1
- movcc r5, #0
- bcs .L3658
- add r2, r0, r1
- cmp r2, r3
- bhi .L3658
+ cmp r3, r2
+ bcc .L3586
cmp r1, #31
- bls .L3656
- ldr r7, .L3669+4
- ldr r3, [r7, #-3616]
+ bls .L3578
+ ldr r7, .L3596+4
+ ldr r3, [r7, #-3612]
cmp r3, #0
- movne r0, r5
- bne .L3651
+ bne .L3578
bl FtlCacheWriteBack
- movw r3, #2394
- ldrh r5, [r8, r3]
+ movw r3, #2396
mov r0, r6
+ ldrh r5, [r5, r3]
mov r1, r5
bl __aeabi_uidiv
smulbb r3, r0, r5
mov r8, r0
- rsb r6, r3, r6
+ sub r6, r6, r3
uxth r6, r6
cmp r6, #0
- beq .L3652
- rsb r5, r6, r5
+ beq .L3580
+ sub r5, r5, r6
add r8, r0, #1
cmp r5, r4
movcs r5, r4
uxth r5, r5
- rsb r4, r5, r4
-.L3652:
- ldr r5, .L3669+8
+ sub r4, r4, r5
+.L3580:
+ ldr r5, .L3596+8
mvn r3, #0
- ldr r9, .L3669+12
str r3, [sp, #4]
mov r6, r5
-.L3653:
+.L3581:
ldrh r3, [r5]
cmp r4, r3
- bcc .L3668
- mov r0, r8
- mov r1, sp
+ bcs .L3583
+ ldr r3, [r7, #1996]
+ cmp r3, #32
+ bls .L3584
+ mov r3, #0
+ str r3, [r7, #1996]
+ bl l2p_flush
+ bl FtlVpcTblFlush
+.L3584:
+ mov r0, #0
+.L3578:
+ add sp, sp, #8
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, pc}
+.L3583:
mov r2, #0
+ mov r1, sp
+ mov r0, r8
bl log2phys
ldr r3, [sp]
cmn r3, #1
- beq .L3654
- ldr r3, [r9, #1996]
- add r1, sp, #4
+ beq .L3582
+ ldr r3, [r7, #1996]
mov r2, #1
+ add r1, sp, #4
mov r0, r8
add r3, r3, #1
- str r3, [r9, #1996]
+ str r3, [r7, #1996]
ldr r3, [r7, #-3360]
add r3, r3, #1
str r3, [r7, #-3360]
@@ -21722,40 +22254,27 @@
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
bl decrement_vpc_count
-.L3654:
+.L3582:
ldrh r3, [r6]
add r8, r8, #1
- rsb r4, r3, r4
- b .L3653
-.L3668:
- ldr r3, .L3669+12
- ldr r2, [r3, #1996]
- cmp r2, #32
- bls .L3656
- mov r2, #0
- str r2, [r3, #1996]
- bl l2p_flush
- bl FtlVpcTblFlush
-.L3656:
- mov r0, #0
- b .L3651
-.L3658:
+ sub r4, r4, r3
+ b .L3581
+.L3586:
mvn r0, #0
-.L3651:
- add sp, sp, #12
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L3670:
+ b .L3578
+.L3597:
.align 2
-.L3669:
+.L3596:
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2394
- .word .LANCHOR4
+ .word .LANCHOR0+2396
.fnend
.size ftl_discard, .-ftl_discard
.align 2
.global FtlDiscard
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlDiscard, %function
FtlDiscard:
.fnstart
@@ -21767,393 +22286,403 @@
.size FtlDiscard, .-FtlDiscard
.align 2
.global ftl_read
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_read, %function
ftl_read:
.fnstart
@ args = 0, pretend = 0, frame = 56
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr ip, .L3643
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r5, r1
- ldr r1, .L3720
.pad #84
sub sp, sp, #84
- ldr r1, [r1, #504]
- cmp r1, #1
- bne .L3697
+ ldr ip, [ip, #500]
+ cmp ip, #1
+ bne .L3623
cmp r0, #16
mov r8, r3
- mov r9, r2
- bne .L3674
- mov r1, r2
- add r0, r5, #256
+ str r2, [sp, #28]
+ mov r5, r1
+ bne .L3601
mov r2, r3
+ ldr r1, [sp, #28]
+ add r0, r5, #256
bl FtlVendorPartRead
- b .L3673
-.L3674:
- ldr r2, .L3720+4
- ldr r3, [r2, #2428]
- cmp r9, r3
- cmpls r5, r3
- bcs .L3697
- add r1, r5, r9
- str r1, [sp, #40]
+ mov r10, r0
+.L3599:
+ mov r0, r10
+ add sp, sp, #84
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3601:
+ ldr r2, .L3643+4
+ ldr r1, [sp, #28]
+ ldr r3, [r2, #2432]
cmp r1, r3
- bhi .L3697
- movw r3, #2394
+ cmpls r5, r3
+ bcs .L3623
+ add r1, r5, r1
+ cmp r3, r1
+ str r1, [sp, #44]
+ bcc .L3623
+ movw r3, #2396
mov r0, r5
ldrh r4, [r2, r3]
mov r1, r4
bl __aeabi_uidiv
+ ldr r3, [sp, #44]
mov r1, r4
- ldr r3, [sp, #40]
- str r0, [sp, #32]
+ str r0, [sp, #36]
sub r0, r3, #1
bl __aeabi_uidiv
- ldr r3, [sp, #32]
- str r0, [sp, #36]
+ ldr r3, [sp, #36]
+ ldr r1, [sp, #28]
+ str r0, [sp, #40]
rsb r3, r3, #1
add r3, r3, r0
- str r3, [sp, #28]
- ldr r3, .L3720+8
- ldr r1, [sp, #28]
- ldr r0, [sp, #32]
+ str r3, [sp, #32]
+ ldr r3, .L3643+8
ldr r2, [r3, #-3336]
- add r2, r9, r2
+ add r2, r2, r1
+ ldr r1, [sp, #32]
str r2, [r3, #-3336]
ldr r2, [r3, #-3364]
- add r2, r1, r2
- ldr r1, [sp, #36]
+ add r2, r2, r1
+ mov r1, r0
+ ldr r0, [sp, #36]
str r2, [r3, #-3364]
bl FtlCacheMetchLpa
cmp r0, #0
- beq .L3675
+ beq .L3602
bl FtlCacheWriteBack
-.L3675:
- ldr r6, [sp, #32]
- mov r10, #0
- ldr r4, .L3720+8
- mov r7, r10
- str r10, [sp, #48]
- str r10, [sp, #52]
-.L3676:
- ldr r3, [sp, #28]
+.L3602:
+ ldr r6, [sp, #36]
+ mov r3, #0
+ ldr r4, .L3643+8
+ mov r7, r3
+ mov r10, r3
+ str r3, [sp, #52]
+ str r3, [sp, #48]
+.L3603:
+ ldr r3, [sp, #32]
cmp r3, #0
- beq .L3719
- mov r0, r6
- add r1, sp, #76
+ bne .L3620
+ ldr r3, .L3643+12
+ ldrh r3, [r3, #-2]
+ cmp r3, #0
+ beq .L3599
+ mov r1, #1
+ ldr r0, [sp, #32]
+ bl ftl_do_gc
+ b .L3599
+.L3620:
mov r2, #0
+ add r1, sp, #76
+ mov r0, r6
bl log2phys
ldr r3, [sp, #76]
cmn r3, #1
- bne .L3715
- mov fp, #0
-.L3677:
- ldr r3, .L3720+12
- ldrh r0, [r3]
- cmp fp, r0
- bcs .L3681
- mla r0, r0, r6, fp
- ldr r2, [sp, #40]
- cmp r0, r5
- movcs r3, #1
- movcc r3, #0
- cmp r0, r2
- movcs r3, #0
- cmp r3, #0
- beq .L3679
- rsb r0, r5, r0
- mov r1, #0
- mov r2, #512
- add r0, r8, r0, asl #9
- bl ftl_memset
-.L3679:
- add fp, fp, #1
- b .L3677
-.L3715:
+ moveq r9, #0
+ beq .L3605
ldr r2, [r4, #-536]
- mov fp, #36
- mla fp, fp, r7, r2
- str r3, [fp, #4]
- ldr r3, [sp, #32]
- cmp r6, r3
- bne .L3682
- ldr r3, [r4, #-508]
- mov r0, r5
- str r3, [fp, #8]
- ldr r3, .L3720+12
- ldrh ip, [r3]
- mov r1, ip
- str ip, [sp, #44]
- bl __aeabi_uidivmod
- ldr ip, [sp, #44]
- str r1, [sp, #56]
- rsb r3, r1, ip
- cmp r3, r9
- movcs r3, r9
- cmp r3, ip
- str r3, [sp, #48]
- streq r8, [fp, #8]
- b .L3683
-.L3682:
+ mov r9, #36
+ mla r9, r9, r7, r2
+ str r3, [r9, #4]
ldr r3, [sp, #36]
cmp r6, r3
- bne .L3684
- ldr r3, [r4, #-504]
- ldr r1, [sp, #40]
- str r3, [fp, #8]
- ldr r3, .L3720+12
- ldrh r2, [r3]
- mul r3, r2, r6
- rsb r10, r3, r1
- cmp r10, r2
- bne .L3683
- b .L3717
-.L3684:
- ldr r3, .L3720+12
- ldrh r3, [r3]
- mul r3, r3, r6
-.L3717:
- rsb r3, r5, r3
- add r3, r8, r3, asl #9
- str r3, [fp, #8]
-.L3683:
- ldr r3, .L3720+16
+ bne .L3609
+ ldr r3, [r4, #-508]
+ mov r0, r5
+ str r3, [r9, #8]
+ ldr r3, .L3643+16
+ ldrh fp, [r3]
+ mov r1, fp
+ bl __aeabi_uidivmod
+ ldr r2, [sp, #28]
+ sub r3, fp, r1
+ str r1, [sp, #56]
+ cmp r2, r3
+ movcc r3, r2
+ cmp r3, fp
+ str r3, [sp, #48]
+ streq r8, [r9, #8]
+.L3610:
+ ldr r3, .L3643+20
ldr r2, [r4, #-496]
- str r6, [fp, #16]
+ str r6, [r9, #16]
ldrh r3, [r3]
- mul r3, r3, r7
+ mul r3, r7, r3
add r7, r7, #1
bic r3, r3, #3
add r3, r2, r3
- str r3, [fp, #12]
-.L3681:
- ldr r3, [sp, #28]
+ str r3, [r9, #12]
+ b .L3608
+.L3607:
+ mla r0, r0, r6, r9
+ ldr r2, [sp, #44]
+ cmp r5, r0
+ movls r3, #1
+ movhi r3, #0
+ cmp r2, r0
+ movls r3, #0
+ cmp r3, #0
+ beq .L3606
+ sub r0, r0, r5
+ mov r2, #512
+ mov r1, #0
+ add r0, r8, r0, lsl #9
+ bl ftl_memset
+.L3606:
+ add r9, r9, #1
+.L3605:
+ ldr r3, .L3643+16
+ ldrh r0, [r3]
+ cmp r9, r0
+ bcc .L3607
+.L3608:
+ ldr r3, [sp, #32]
add r6, r6, #1
subs r3, r3, #1
- str r3, [sp, #28]
- beq .L3685
- ldr r3, .L3720+20
+ str r3, [sp, #32]
+ beq .L3612
+ ldr r3, .L3643+24
ldrh r3, [r3]
- cmp r7, r3, asl #3
- bne .L3676
-.L3685:
+ cmp r7, r3, lsl #3
+ bne .L3603
+.L3612:
cmp r7, #0
- beq .L3676
- ldr r0, [r4, #-536]
- mov r1, r7
+ beq .L3603
mov r2, #0
+ mov r1, r7
+ ldr r0, [r4, #-536]
+ mov fp, #0
bl FlashReadPages
+ ldr r3, [sp, #52]
+ lsl r3, r3, #9
+ str r3, [sp, #68]
ldr r3, [sp, #56]
- mov r3, r3, asl #9
+ lsl r3, r3, #9
str r3, [sp, #60]
ldr r3, [sp, #48]
- mov r3, r3, asl #9
+ lsl r3, r3, #9
str r3, [sp, #64]
- mov r3, r10, asl #9
- str r3, [sp, #68]
- mov r3, #0
- str r3, [sp, #44]
-.L3692:
- ldr r3, [sp, #44]
- mov ip, #36
- ldr r1, [sp, #32]
- mul fp, ip, r3
+.L3619:
+ mov r9, #36
ldr r3, [r4, #-536]
- add r3, r3, fp
+ mul r9, r9, fp
+ ldr r1, [sp, #36]
+ add r3, r3, r9
ldr r2, [r3, #16]
- cmp r2, r1
- bne .L3687
+ cmp r1, r2
+ bne .L3614
ldr r1, [r3, #8]
ldr r3, [r4, #-508]
cmp r1, r3
- bne .L3688
+ bne .L3615
ldr r3, [sp, #60]
mov r0, r8
ldr r2, [sp, #64]
add r1, r1, r3
- b .L3718
-.L3687:
- ldr r1, [sp, #36]
- cmp r2, r1
- bne .L3688
- ldr r1, [r3, #8]
- ldr r3, [r4, #-504]
- cmp r1, r3
- bne .L3688
- ldr r3, .L3720+12
- ldr r2, [sp, #68]
- ldrh r0, [r3]
- ldr r3, [sp, #36]
- mul r0, r0, r3
- rsb r0, r5, r0
- add r0, r8, r0, asl #9
-.L3718:
+.L3642:
bl ftl_memcpy
-.L3688:
- ldr r2, [r4, #-536]
- add r3, r2, fp
- ldr r1, [r2, fp]
- cmn r1, #1
- streq r1, [sp, #52]
- ldreq r2, [r4, #-3160]
- addeq r2, r2, #1
- streq r2, [r4, #-3160]
- ldr r2, [r3, #12]
- ldr r1, [r3, #16]
- ldr r2, [r2, #8]
- cmp r1, r2
- beq .L3690
- ldr r2, [r4, #-3160]
- ldr r0, .L3720+24
- add r2, r2, #1
- str r2, [r4, #-3160]
- ldr lr, [r3, #12]
- ldr r2, [r3, #8]
- ldr r1, [lr, #4]
- str r1, [sp]
- ldr r1, [lr, #8]
- str r1, [sp, #4]
- ldr r1, [lr, #12]
- str r1, [sp, #8]
- ldr r1, [r2]
- str r1, [sp, #12]
- ldr r2, [r2, #4]
- str r2, [sp, #16]
- ldr r1, [r3, #16]
- ldr r2, [r3, #4]
- ldr r3, [lr]
- bl printk
-.L3690:
+.L3615:
ldr r3, [r4, #-536]
- add r2, r3, fp
- ldr r3, [r3, fp]
+ ldr r2, [r3, r9]
+ add r1, r3, r9
+ cmn r2, #1
+ ldreq r3, [r4, #-3164]
+ moveq r10, r2
+ addeq r3, r3, #1
+ streq r3, [r4, #-3164]
+ ldr r3, [r1, #12]
+ ldr r2, [r1, #16]
+ ldr r3, [r3, #8]
+ cmp r2, r3
+ beq .L3617
+ ldr r3, [r4, #-3164]
+ add r3, r3, #1
+ str r3, [r4, #-3164]
+ ldr r2, [r1, #8]
+ ldr r3, [r1, #12]
+ ldr r0, [r2, #4]
+ str r0, [sp, #16]
+ ldr r2, [r2]
+ ldr r0, .L3643+28
+ str r2, [sp, #12]
+ ldr r2, [r3, #12]
+ str r2, [sp, #8]
+ ldr r2, [r3, #8]
+ str r2, [sp, #4]
+ ldr r2, [r3, #4]
+ str r2, [sp]
+ ldr r2, [r1, #4]
+ ldr r3, [r3]
+ ldr r1, [r1, #16]
+ bl printk
+.L3617:
+ ldr r3, [r4, #-536]
+ add r2, r3, r9
+ ldr r3, [r3, r9]
cmp r3, #256
- bne .L3691
+ bne .L3618
ldr r0, [r2, #4]
ubfx r0, r0, #10, #16
bl P2V_block_in_plane
bl FtlGcRefreshBlock
-.L3691:
- ldr r3, [sp, #44]
- add r3, r3, #1
- str r3, [sp, #44]
- cmp r3, r7
- bne .L3692
+.L3618:
+ add fp, fp, #1
+ cmp r7, fp
+ bne .L3619
mov r7, #0
- b .L3676
-.L3719:
- ldr r3, .L3720+28
- ldrh r3, [r3, #-2]
- cmp r3, #0
- beq .L3694
- ldr r0, [sp, #28]
- mov r1, #1
- bl ftl_do_gc
-.L3694:
- ldr r0, [sp, #52]
- b .L3673
-.L3697:
- mvn r0, #0
-.L3673:
- add sp, sp, #84
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3721:
+ b .L3603
+.L3609:
+ ldr r3, [sp, #40]
+ cmp r6, r3
+ bne .L3611
+ ldr r3, [r4, #-504]
+ ldr r1, [sp, #44]
+ str r3, [r9, #8]
+ ldr r3, .L3643+16
+ ldrh r2, [r3]
+ mul r3, r2, r6
+ sub r1, r1, r3
+ cmp r2, r1
+ str r1, [sp, #52]
+ bne .L3610
+.L3641:
+ sub r3, r3, r5
+ add r3, r8, r3, lsl #9
+ str r3, [r9, #8]
+ b .L3610
+.L3611:
+ ldr r3, .L3643+16
+ ldrh r3, [r3]
+ mul r3, r6, r3
+ b .L3641
+.L3614:
+ ldr r1, [sp, #40]
+ cmp r1, r2
+ bne .L3615
+ ldr r1, [r3, #8]
+ ldr r3, [r4, #-504]
+ cmp r1, r3
+ bne .L3615
+ ldr r3, .L3643+16
+ ldr r2, [sp, #68]
+ ldrh r0, [r3]
+ ldr r3, [sp, #40]
+ mul r0, r3, r0
+ sub r0, r0, r5
+ add r0, r8, r0, lsl #9
+ b .L3642
+.L3623:
+ mvn r10, #0
+ b .L3599
+.L3644:
.align 2
-.L3720:
+.L3643:
.word .LANCHOR1
.word .LANCHOR0
.word .LANCHOR2
- .word .LANCHOR0+2394
- .word .LANCHOR0+2400
- .word .LANCHOR0+2320
- .word .LC148
.word .LANCHOR2-2656
+ .word .LANCHOR0+2396
+ .word .LANCHOR0+2402
+ .word .LANCHOR0+2324
+ .word .LC148
.fnend
.size ftl_read, .-ftl_read
.align 2
.global ftl_vendor_read
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_vendor_read, %function
ftl_vendor_read:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- str lr, [sp, #-4]!
- .save {lr}
- mov ip, r1
- mov lr, r0
+ @ link register save eliminated.
mov r3, r2
- mov r1, lr
+ mov r2, r1
+ mov r1, r0
mov r0, #16
- mov r2, ip
- ldr lr, [sp], #4
b ftl_read
.fnend
.size ftl_vendor_read, .-ftl_vendor_read
.align 2
.global FlashBootVendorRead
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashBootVendorRead, %function
FlashBootVendorRead:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- mov r4, r2
- mov r6, r0
+ mov r4, r0
mov r5, r1
+ mov r6, r2
bl rknand_device_lock
- ldr r3, .L3728
- ldr r3, [r3, #504]
+ ldr r3, .L3650
+ ldr r3, [r3, #500]
cmp r3, #1
mvnne r4, #0
- bne .L3725
- mov r2, r4
- mov r0, r6
+ bne .L3647
+ mov r0, r4
+ mov r2, r6
mov r1, r5
bl ftl_vendor_read
mov r4, r0
-.L3725:
+.L3647:
bl rknand_device_unlock
mov r0, r4
- ldmfd sp!, {r4, r5, r6, pc}
-.L3729:
+ pop {r4, r5, r6, pc}
+.L3651:
.align 2
-.L3728:
+.L3650:
.word .LANCHOR1
.fnend
.size FlashBootVendorRead, .-FlashBootVendorRead
.align 2
.global ftl_sys_read
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_sys_read, %function
ftl_sys_read:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- mov ip, r1
mov r3, r2
+ mov r2, r1
add r1, r0, #256
- mov r2, ip
mov r0, #16
b ftl_read
.fnend
.size ftl_sys_read, .-ftl_sys_read
.align 2
.global StorageSysDataLoad
+ .syntax unified
+ .arm
+ .fpu softvfp
.type StorageSysDataLoad, %function
StorageSysDataLoad:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r2, #512
- mov r5, r0
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
mov r4, r1
- mov r0, r1
+ mov r5, r0
+ mov r2, #512
mov r1, #0
+ mov r0, r4
bl ftl_memset
bl rknand_device_lock
mov r2, r4
@@ -22163,11 +22692,14 @@
mov r4, r0
bl rknand_device_unlock
mov r0, r4
- ldmfd sp!, {r3, r4, r5, pc}
+ pop {r4, r5, r6, pc}
.fnend
.size StorageSysDataLoad, .-StorageSysDataLoad
.align 2
.global FtlRead
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlRead, %function
FtlRead:
.fnstart
@@ -22179,284 +22711,288 @@
.size FtlRead, .-FtlRead
.align 2
.global FtlInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlInit, %function
FtlInit:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
mvn r3, #0
- ldr r2, .L3751
- ldr r7, .L3751+4
- ldr r5, .L3751+8
- ldr r6, .L3751+12
- ldr r1, .L3751+16
- ldr r0, .L3751+20
- str r3, [r7, #504]
+ ldr r7, .L3673
+ ldr r5, .L3673+4
+ ldr r6, .L3673+8
+ ldr r1, .L3673+12
+ str r3, [r7, #500]
mov r3, #0
- str r3, [r2, #2000]
- str r3, [r5, #-3616]
+ ldr r0, .L3673+16
+ str r3, [r5, #2000]
+ str r3, [r5, #-3612]
bl printk
- add r0, r6, #116
+ add r0, r6, #124
bl FtlConstantsInit
bl FtlMemInit
bl FtlVariablesInit
- ldr r3, [r6, #2324]
- uxth r0, r3
+ add r3, r6, #2320
+ add r3, r3, #8
+ ldrh r0, [r3]
bl FtlFreeSysBlkQueueInit
bl FtlLoadBbt
cmp r0, #0
- ldrne r0, .L3751+24
- bne .L3750
+ beq .L3657
+ ldr r1, .L3673+20
+ ldr r0, .L3673+24
+.L3672:
+ bl printk
+.L3658:
+ mov r0, #0
+ pop {r4, r5, r6, r7, r8, pc}
+.L3657:
bl FtlSysBlkInit
subs r4, r0, #0
- beq .L3737
- ldr r0, .L3751+28
-.L3750:
- ldr r1, .L3751+32
- bl printk
- b .L3736
-.L3737:
- sub r5, r5, #3520
+ ldrne r1, .L3673+20
+ ldrne r0, .L3673+28
+ bne .L3672
+.L3659:
mov r1, #1
- str r1, [r7, #504]
+ sub r5, r5, #3520
+ str r1, [r7, #500]
bl ftl_do_gc
- ldrh r5, [r5, #-8]
- cmp r5, #15
- bhi .L3738
- ldr r6, .L3751+36
- ldr r7, .L3751+40
- sub r8, r6, #244
-.L3741:
- ldrh r3, [r6]
+ ldrh r7, [r5, #-4]
+ cmp r7, #15
+ bhi .L3660
+.L3663:
+ ldr r3, .L3673+32
movw r2, #65535
+ ldrh r3, [r3]
cmp r3, r2
- bne .L3739
- ldrh r2, [r7]
+ bne .L3661
+ ldr r2, .L3673+36
+ ldrh r2, [r2]
cmp r2, r3
- bne .L3739
+ bne .L3661
and r0, r4, #63
bl List_get_gc_head_node
uxth r0, r0
bl FtlGcRefreshBlock
-.L3739:
- mov r0, #1
- mov r1, r0
- bl ftl_do_gc
- mov r0, #0
+.L3661:
mov r1, #1
+ mov r0, r1
bl ftl_do_gc
- ldrh r2, [r8]
- add r3, r5, #2
+ mov r1, #1
+ mov r0, #0
+ bl ftl_do_gc
+ ldrh r2, [r5, #-4]
+ add r3, r7, #2
cmp r2, r3
- bhi .L3736
+ bhi .L3658
add r4, r4, #1
cmp r4, #4096
- bne .L3741
- b .L3736
-.L3738:
- ldrb r3, [r6, #144] @ zero_extendqisi2
+ bne .L3663
+ b .L3658
+.L3660:
+ ldrb r3, [r6, #152] @ zero_extendqisi2
cmp r3, #0
- beq .L3736
+ beq .L3658
mov r4, #128
-.L3743:
- mov r0, #1
- mov r1, r0
+.L3665:
+ mov r1, #1
+ mov r0, r1
bl ftl_do_gc
subs r4, r4, #1
- bne .L3743
-.L3736:
- mov r0, #0
- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
-.L3752:
+ bne .L3665
+ b .L3658
+.L3674:
.align 2
-.L3751:
- .word .LANCHOR4
+.L3673:
.word .LANCHOR1
.word .LANCHOR2
.word .LANCHOR0
- .word .LC77
.word .LC76
+ .word .LC77
+ .word .LANCHOR3+224
.word .LC161
.word .LC162
- .word .LANCHOR3+240
.word .LANCHOR2-3284
.word .LANCHOR2-2666
.fnend
.size FtlInit, .-FtlInit
.align 2
.global rk_ftl_init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_init, %function
rk_ftl_init:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r0, #2048
- bl ftl_malloc
- ldr r6, .L3758
- ldr r4, .L3758+4
+ bl ftl_dma32_malloc
mov r5, #0
- ldr r1, .L3758+8
- str r5, [r6, #2008]
+ ldr r4, .L3680
+ ldr r1, .L3680+4
+ str r0, [r4, #2004]
+ sub r0, r1, #324
+ str r5, [r4, #1688]
str r5, [r4, #1684]
- str r0, [r6, #2004]
- ldr r0, .L3758+12
+ str r5, [r4, #2008]
bl rknand_get_reg_addr
ldr r3, [r4, #1684]
cmp r3, r5
- beq .L3756
+ mvneq r4, #0
+ beq .L3675
bl rk_nandc_irq_init
- mov r1, r5
- mov r2, r5
mov r3, #2048
- ldr r0, [r6, #2004]
+ mov r2, r5
+ mov r1, r5
+ ldr r0, [r4, #2004]
bl FlashSramLoadStore
bl rknand_flash_cs_init
ldr r0, [r4, #1684]
bl FlashInit
subs r4, r0, #0
- bne .L3755
+ bne .L3677
bl FtlInit
-.L3755:
+.L3677:
mov r1, r4
- ldr r0, .L3758+16
+ ldr r0, .L3680+8
bl printk
+.L3675:
mov r0, r4
- ldmfd sp!, {r4, r5, r6, pc}
-.L3756:
- mvn r0, #0
- ldmfd sp!, {r4, r5, r6, pc}
-.L3759:
+ pop {r4, r5, r6, pc}
+.L3681:
.align 2
-.L3758:
- .word .LANCHOR4
+.L3680:
.word .LANCHOR2
- .word .LANCHOR4+2008
- .word .LANCHOR2+1684
+ .word .LANCHOR2+2008
.word .LC163
.fnend
.size rk_ftl_init, .-rk_ftl_init
.align 2
.global ftl_fix_nand_power_lost_error
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_fix_nand_power_lost_error, %function
ftl_fix_nand_power_lost_error:
.fnstart
@ args = 0, pretend = 0, frame = 48
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L3777
- ldrb r3, [r3, #144] @ zero_extendqisi2
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ .pad #48
+ sub sp, sp, #48
+ ldr r8, .L3697
+ ldrb r3, [r8, #152] @ zero_extendqisi2
cmp r3, #0
- bxeq lr
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #1848
- ldr r8, .L3777+4
- .pad #52
- sub sp, sp, #52
- ldr r4, .L3777+8
+ beq .L3682
+ ldr r4, .L3697+4
+ movw r3, #1846
+ ldr r0, .L3697+8
+ ldrh r6, [r4, r3]
+ sub r9, r4, #3520
+ ldr r3, [r4, #-3540]
+ sub r5, r4, #3472
+ mov r1, r6
+ lsl r7, r6, #1
+ ldrh r2, [r3, r7]
+ bl printk
+ ldrh r0, [r9]
+ bl FtlGcRefreshOpenBlock
+ ldrh r0, [r5]
+ bl FtlGcRefreshOpenBlock
+ mov r0, r9
+ bl allocate_new_data_superblock
+ mov r0, r5
movw r5, #4097
- ldr r0, .L3777+12
- ldrh r7, [r8, r3]
- ldr r3, [r4, #-3544]
- mov r6, r7, asl #1
- mov r1, r7
- ldrh r2, [r3, r6]
- bl printk
- sub r3, r4, #3520
- ldrh r0, [r3, #-4]
- bl FtlGcRefreshOpenBlock
- sub r3, r4, #3472
- ldrh r0, [r3, #-4]
- bl FtlGcRefreshOpenBlock
- ldr r0, .L3777+16
bl allocate_new_data_superblock
- ldr r0, .L3777+20
- bl allocate_new_data_superblock
-.L3762:
+.L3684:
subs r5, r5, #1
- beq .L3766
- mov r0, #1
- mov r1, r0
+ beq .L3688
+ mov r1, #1
+ mov r0, r1
bl ftl_do_gc
- ldr r3, [r4, #-3544]
- ldrh r3, [r3, r6]
+ ldr r3, [r4, #-3540]
+ ldrh r3, [r3, r7]
cmp r3, #0
- bne .L3762
-.L3766:
- ldr r3, [r4, #-3544]
- mov r1, r7
- ldr r0, .L3777+12
- ldrh r2, [r3, r6]
+ bne .L3684
+.L3688:
+ ldr r3, [r4, #-3540]
+ mov r1, r6
+ ldr r0, .L3697+8
+ ldrh r2, [r3, r7]
bl printk
- ldr r3, [r4, #-3544]
- ldrh r5, [r3, r6]
+ ldr r3, [r4, #-3540]
+ ldrh r5, [r3, r7]
cmp r5, #0
- bne .L3764
+ bne .L3686
add r0, sp, #48
- movw r10, #65535
- mov fp, #36
- strh r7, [r0, #-48]! @ movhi
+ movw r9, #65535
+ strh r6, [r0, #-48]! @ movhi
+ mov r10, #36
bl make_superblock
- ldr r3, .L3777+24
- ldrh lr, [r3]
- ldr r3, .L3777+8
- ldr r9, [r3, #-3612]
- mov r3, r5
- mov ip, r3
+ movw r3, #2324
add r0, sp, #14
-.L3767:
- uxth r2, r3
- cmp r2, lr
- bcs .L3776
- ldrh r2, [r0, #2]!
- add r3, r3, #1
- cmp r2, r10
- movne r2, r2, asl #10
- mlane r1, fp, r5, r9
+ ldrh lr, [r8, r3]
+ mov r2, r5
+ ldr r8, [r4, #-3608]
+ mov ip, r5
+.L3689:
+ uxth r3, r2
+ cmp lr, r3
+ bhi .L3691
+ ldr r3, [r4, #-3540]
+ mov r1, r6
+ ldr r0, .L3697+12
+ ldrh r2, [r3, r7]
+ bl printk
+ mov r2, r5
+ mov r1, #0
+ ldr r0, [r4, #-3608]
+ bl FlashEraseBlocks
+ mov r2, r5
+ mov r1, #1
+ ldr r0, [r4, #-3608]
+ bl FlashEraseBlocks
+.L3686:
+ mvn r2, #0
+ movw r3, #1846
+ strh r2, [r4, r3] @ movhi
+.L3682:
+ add sp, sp, #48
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3691:
+ ldrh r3, [r0, #2]!
+ add r2, r2, #1
+ cmp r3, r9
+ mlane r1, r10, r5, r8
+ lslne r3, r3, #10
addne r5, r5, #1
uxthne r5, r5
- stmneib r1, {r2, ip}
+ stmibne r1, {r3, ip}
strne ip, [r1, #12]
- b .L3767
-.L3776:
- ldr r3, [r4, #-3544]
- mov r1, r7
- ldr r0, .L3777+28
- ldrh r2, [r3, r6]
- bl printk
- mov r1, #0
- mov r2, r5
- ldr r0, [r4, #-3612]
- bl FlashEraseBlocks
- ldr r0, [r4, #-3612]
- mov r1, #1
- mov r2, r5
- bl FlashEraseBlocks
-.L3764:
- movw r3, #1848
- mvn r2, #0
- strh r2, [r8, r3] @ movhi
- add sp, sp, #52
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3778:
+ b .L3689
+.L3698:
.align 2
-.L3777:
+.L3697:
.word .LANCHOR0
- .word .LANCHOR4
.word .LANCHOR2
.word .LC164
- .word .LANCHOR2-3524
- .word .LANCHOR2-3476
- .word .LANCHOR0+2320
.word .LC165
.fnend
.size ftl_fix_nand_power_lost_error, .-ftl_fix_nand_power_lost_error
.align 2
.global rk_ftl_garbage_collect
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_garbage_collect, %function
rk_ftl_garbage_collect:
.fnstart
@@ -22468,907 +23004,910 @@
.size rk_ftl_garbage_collect, .-rk_ftl_garbage_collect
.align 2
.global ftl_write
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_write, %function
ftl_write:
.fnstart
- @ args = 0, pretend = 0, frame = 96
+ @ args = 0, pretend = 0, frame = 80
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- .pad #100
- sub sp, sp, #100
- ldr r10, .L3854
- str r3, [sp, #4]
- ldr r3, [r10, #-3616]
+ mov fp, r3
+ ldr r4, .L3768
+ .pad #84
+ sub sp, sp, #84
+ ldr r3, [r4, #-3612]
cmp r3, #0
- bne .L3821
- mov r8, r2
- ldr r2, .L3854+4
- ldr r2, [r2, #504]
+ bne .L3741
+ mov r9, r2
+ ldr r2, .L3768+4
+ ldr r2, [r2, #500]
cmp r2, #1
movne r0, r3
- bne .L3781
+ bne .L3700
cmp r0, #16
mov r7, r1
- bne .L3782
- add r0, r1, #256
- ldr r2, [sp, #4]
- mov r1, r8
+ bne .L3702
+ mov r2, fp
+ mov r1, r9
+ add r0, r7, #256
bl FtlVendorPartWrite
- b .L3781
-.L3782:
- ldr fp, .L3854+8
- ldr r3, [fp, #2428]
- cmp r8, r3
+.L3700:
+ add sp, sp, #84
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3702:
+ ldr r10, .L3768+8
+ ldr r3, [r10, #2432]
+ cmp r9, r3
cmpls r1, r3
- bcs .L3824
- add r5, r1, r8
- cmp r5, r3
- bhi .L3824
- ldr r6, .L3854+12
+ bcs .L3744
+ add r6, r1, r9
+ cmp r3, r6
+ bcc .L3744
mov r3, #2048
- mov r0, r1
- str r3, [r6, #2012]
- movw r3, #2394
- ldrh r4, [fp, r3]
- mov r1, r4
+ mov r0, r7
+ str r3, [r4, #2012]
+ movw r3, #2396
+ ldrh r5, [r10, r3]
+ mov r1, r5
bl __aeabi_uidiv
- mov r1, r4
- str r0, [sp, #8]
- sub r0, r5, #1
+ mov r1, r5
+ str r0, [sp, #4]
+ sub r0, r6, #1
bl __aeabi_uidiv
- cmp r8, r4, asl #1
- ldr r2, [sp, #8]
- str r0, [sp, #28]
- rsb r5, r2, r0
- add r3, r5, #1
- str r3, [sp]
- ldr r2, [sp]
- ldr r3, [r10, #-3356]
- add r3, r2, r3
- ldr r2, [fp, #2440]
- str r3, [r10, #-3356]
- ldr r3, [r10, #-3340]
- add r3, r8, r3
- str r3, [r10, #-3340]
+ ldr r2, [sp, #4]
+ cmp r9, r5, lsl #1
+ ldr r3, [r4, #-3356]
+ ldr r1, [r10, #2444]
+ sub r6, r0, r2
+ str r0, [sp, #24]
+ add r8, r6, #1
+ add r3, r3, r8
+ str r3, [r4, #-3356]
+ ldr r3, [r4, #-3340]
+ add r3, r3, r9
+ str r3, [r4, #-3340]
movcs r3, #1
movcc r3, #0
- cmp r2, #0
- str r3, [sp, #20]
- beq .L3784
+ cmp r1, #0
+ str r3, [sp, #16]
+ beq .L3745
mov r3, #36
- ldr r9, [fp, #2444]
- mul r3, r3, r2
- ldr r2, [sp, #8]
+ ldr r2, [r10, #2448]
+ mul r3, r3, r1
sub r3, r3, #36
- add r9, r9, r3
- ldr r3, [r9, #16]
- cmp r2, r3
- bne .L3785
- ldr r3, [r10, #-3352]
- mov r1, r4
- mov r0, r7
- add r3, r3, #1
- str r3, [r10, #-3352]
- ldr r3, [r6, #2016]
- add r3, r3, #1
- str r3, [r6, #2016]
- bl __aeabi_uidivmod
- ldr r0, [r9, #8]
- rsb r4, r1, r4
- add r0, r0, r1, asl #9
- cmp r4, r8
- ldr r1, [sp, #4]
- movcs r4, r8
- mov r10, r4, asl #9
- mov r2, r10
- bl ftl_memcpy
- cmp r5, #0
- bne .L3786
- ldr r3, [r6, #2016]
- cmp r3, #2
- ble .L3821
-.L3786:
+ add r10, r2, r3
ldr r3, [sp, #4]
- rsb r8, r4, r8
- add r7, r7, r4
- str r5, [sp]
- add r3, r3, r10
- str r3, [sp, #4]
- ldr r3, [sp, #8]
+ ldr r2, [r10, #16]
+ cmp r3, r2
+ strne fp, [sp, #12]
+ bne .L3705
+ ldr r2, [r4, #-3352]
+ mov r1, r5
+ mov r0, r7
+ add r2, r2, #1
+ str r2, [r4, #-3352]
+ ldr r2, [r4, #2016]
+ add r2, r2, #1
+ str r2, [r4, #2016]
+ bl __aeabi_uidivmod
+ sub r5, r5, r1
+ ldr r3, [r10, #8]
+ cmp r9, r5
+ mov r0, r1
+ movcc r5, r9
+ mov r1, fp
+ lsl r8, r5, #9
+ add r0, r3, r0, lsl #9
+ mov r2, r8
+ bl ftl_memcpy
+ cmp r6, #0
+ bne .L3706
+ ldr r3, [r4, #2016]
+ cmp r3, #2
+ bgt .L3706
+.L3741:
+ mov r0, #0
+ b .L3700
+.L3706:
+ add r3, fp, r8
+ sub r9, r9, r5
+ str r3, [sp, #12]
+ add r7, r7, r5
+ ldr r3, [sp, #4]
+ mov r8, r6
add r3, r3, #1
- str r3, [sp, #8]
-.L3785:
+ str r3, [sp, #4]
+.L3705:
mov r3, #0
- str r3, [r6, #2016]
-.L3784:
- ldr r0, [sp, #8]
- ldr r1, [sp, #28]
+ str r3, [r4, #2016]
+.L3704:
+ ldr r1, [sp, #24]
+ ldr r0, [sp, #4]
bl FtlCacheMetchLpa
cmp r0, #0
- beq .L3787
+ beq .L3707
bl FtlCacheWriteBack
-.L3787:
- ldr r5, .L3854+16
- mov r3, #0
- ldr r4, .L3854+8
- str r3, [sp, #12]
- str r5, [r6, #1992]
- ldr r6, [sp, #8]
- mov r10, r4
- str r3, [sp, #32]
-.L3788:
- ldr r3, [sp]
- cmp r3, #0
- beq .L3853
- ldrh r2, [r5, #4]
- cmp r2, #0
- bne .L3789
- ldr r3, .L3854+16
- ldr r9, .L3854+4
- cmp r5, r3
- bne .L3790
- add r0, r3, #48
- ldrh r5, [r0, #4]
- cmp r5, #0
- bne .L3791
- bl allocate_new_data_superblock
- str r5, [r9, #3452]
-.L3791:
- ldr r0, .L3854+16
- bl allocate_new_data_superblock
- ldr r3, [r9, #3452]
- cmp r3, #0
- ldrne r5, .L3854+20
- bne .L3792
-.L3793:
- ldr r5, .L3854+16
- b .L3792
-.L3790:
- ldrh r3, [r3, #4]
- str r2, [r9, #3452]
- cmp r3, #0
- bne .L3793
- mov r0, r5
- bl allocate_new_data_superblock
-.L3792:
- ldrh r3, [r5, #4]
- cmp r3, #0
- bne .L3794
- mov r0, r5
- bl allocate_new_data_superblock
-.L3794:
- ldr r3, .L3854+12
- str r5, [r3, #1992]
-.L3789:
- ldr r2, .L3854
- ldr r1, [r4, #2440]
- ldrh r3, [r5, #4]
- ldr r2, [r2, #-540]
- rsb r2, r1, r2
- cmp r3, r2
- movcs r3, r2
- ldr r2, [sp]
- cmp r3, r2
- movcs r3, r2
- str r3, [sp, #44]
- mov r3, #0
-.L3851:
- str r3, [sp, #16]
- ldr r3, [sp, #16]
- ldr r2, [sp, #44]
- cmp r3, r2
- beq .L3796
- ldrh r3, [r5, #4]
- cmp r3, #0
- beq .L3796
- ldr r3, [sp, #28]
- ldr r2, [sp, #16]
- rsb ip, r3, r6
- ldr r3, [sp, #20]
- clz ip, ip
- mov ip, ip, lsr #5
- and r3, ip, r3
- cmp r2, #0
- moveq r3, #0
- andne r3, r3, #1
- cmp r3, #0
- beq .L3797
- ldr r3, .L3854+24
- ldrh r2, [r3]
- add r3, r8, r7
- mls r3, r2, r6, r3
- cmp r3, r2
- bne .L3796
-.L3797:
- add r1, sp, #56
- mov r2, #0
- mov r0, r6
- str ip, [sp, #52]
- bl log2phys
- mov r0, r5
- bl get_new_active_ppa
- ldr r2, [r4, #2440]
- ldr r1, [r4, #2444]
- mov r3, #36
- ldr fp, .L3854+28
- mla r1, r3, r2, r1
- ldrh r2, [fp]
- str r6, [r1, #16]
- str r3, [sp, #48]
- ldr r3, [r4, #2440]
- str r0, [r1, #4]
- ldr r0, .L3854
- mul lr, r3, r2
- bic r3, lr, #3
- str r3, [sp, #36]
- ldr r3, [r0, #-492]
- ldr ip, [sp, #36]
- ldrh lr, [fp, #-2]
- add r9, r3, ip
- str r3, [sp, #40]
- ldr r3, [r4, #2440]
- ldr r0, [r0, #-512]
- str r9, [r1, #12]
- mul lr, r3, lr
- bic lr, lr, #3
- add lr, r0, lr
- mov r0, r9
- str lr, [r1, #8]
- mov r1, #0
- bl ftl_memset
- ldr r3, [sp, #8]
- ldr ip, [sp, #52]
- rsb r3, r3, r6
- clz r3, r3
- mov r3, r3, lsr #5
- str r3, [sp, #24]
- orrs r3, r3, ip
- ldr r3, [sp, #48]
- beq .L3798
+.L3707:
+ ldr r6, [sp, #4]
+ ldr r10, .L3768+8
+ ldr r5, .L3768+12
+ str r5, [r4, #1992]
+.L3708:
+ cmp r8, #0
+ bne .L3736
ldr r3, [sp, #24]
- cmp r3, #0
- beq .L3799
- ldrh fp, [fp, #-6]
- mov r0, r7
- mov r1, fp
- bl __aeabi_uidivmod
- rsb fp, r1, fp
- mov r3, r1
- cmp fp, r8
- str r1, [sp, #32]
- movcc r3, fp
- movcs r3, r8
- str r3, [sp, #12]
- b .L3800
-.L3799:
- cmp ip, #0
- beq .L3800
- ldr r2, .L3854+24
- add r3, r8, r7
- ldrh r2, [r2]
- smulbb r2, r2, r6
- rsb r3, r2, r3
- uxth r3, r3
- str r3, [sp, #12]
- ldr r3, [sp, #24]
- str r3, [sp, #32]
-.L3800:
- ldr r3, .L3854+24
- ldr r2, [sp, #12]
- ldrh r3, [r3]
- cmp r2, r3
- bne .L3801
- ldr r3, [sp, #24]
- ldr r0, [r10, #2444]
- cmp r3, #0
- moveq r3, r2
- ldr r2, [r10, #2440]
- muleq r1, r6, r3
- ldreq r3, [sp, #4]
- ldrne r1, [sp, #4]
- rsbeq r1, r7, r1
- addeq r1, r3, r1, asl #9
- ldr r3, [sp, #20]
- cmp r3, #0
- mov r3, #36
- mla r3, r3, r2, r0
- strne r1, [r3, #8]
- bne .L3804
- ldr r0, [r3, #8]
- ldr r3, .L3854+32
- ldrh r2, [r3]
- b .L3849
-.L3801:
- ldr r2, [sp, #56]
- mov r3, #36
- cmn r2, #1
- beq .L3805
- ldr r1, [r4, #2444]
- add r0, sp, #60
- str r2, [sp, #64]
- ldr r2, [r4, #2440]
- str r6, [sp, #76]
- mla r3, r3, r2, r1
- mov r1, #1
- ldr r2, [r3, #8]
- ldr r3, [r3, #12]
- str r2, [sp, #68]
- mov r2, #0
- str r3, [sp, #72]
- bl FlashReadPages
- ldr r3, [sp, #60]
- cmn r3, #1
- ldr r3, .L3854
- ldreq r2, [r3, #-3160]
- addeq r2, r2, #1
- streq r2, [r3, #-3160]
- beq .L3808
- ldr r2, [r9, #8]
- cmp r2, r6
- beq .L3808
- ldr r2, [r3, #-3160]
- ldr r0, .L3854+36
- add r2, r2, #1
- str r2, [r3, #-3160]
- mov r2, r6
- ldr r1, [r9, #8]
- bl printk
- b .L3808
-.L3805:
- ldr r2, [r4, #2440]
- ldr r1, [r4, #2444]
- mla r3, r3, r2, r1
- mov r1, #0
- ldr r0, [r3, #8]
- ldr r3, .L3854+32
- ldrh r2, [r3]
- bl ftl_memset
-.L3808:
- ldr r3, [sp, #24]
- cmp r3, #0
- mov r3, #36
- beq .L3809
- ldr r1, [r4, #2444]
- ldr r2, [r4, #2440]
- mla r3, r3, r2, r1
- ldr r1, [sp, #4]
- ldr r0, [r3, #8]
- ldr r3, [sp, #32]
- add r0, r0, r3, asl #9
- b .L3852
-.L3809:
- ldr r1, [r4, #2440]
- ldr r2, [r4, #2444]
- mla r3, r3, r1, r2
- ldr r2, .L3854+24
- ldrh r1, [r2]
- ldr r0, [r3, #8]
- mul r1, r1, r6
- ldr r3, [sp, #4]
- rsb r1, r7, r1
- add r1, r3, r1, asl #9
-.L3852:
- ldr r3, [sp, #12]
- mov r2, r3, asl #9
- b .L3849
-.L3798:
- ldr r2, [sp, #20]
- cmp r2, #0
- ldr r2, [r4, #2440]
- beq .L3810
- ldr r1, [r4, #2444]
- mla r3, r3, r2, r1
- ldr r2, .L3854+24
- ldrh fp, [r2]
+ mov r0, r8
ldr r2, [sp, #4]
- mul fp, fp, r6
- rsb fp, r7, fp
- add fp, r2, fp, asl #9
- str fp, [r3, #8]
- b .L3804
-.L3810:
- ldr r0, [r4, #2444]
- mla r3, r3, r2, r0
- ldr r2, .L3854+24
- ldrh r1, [r2]
- ldrh r2, [fp, #-2]
- ldr r0, [r3, #8]
- mul r1, r1, r6
- ldr r3, [sp, #4]
- rsb r1, r7, r1
- add r1, r3, r1, asl #9
-.L3849:
- bl ftl_memcpy
-.L3804:
- ldr r3, .L3854+40
- ldr r2, [sp, #40]
- ldr r1, [sp, #36]
- strh r3, [r2, r1] @ movhi
- ldr r2, .L3854
- str r6, [r9, #8]
- add r6, r6, #1
- ldr r3, [r2, #-3328]
- str r3, [r9, #4]
- add r3, r3, #1
- cmn r3, #1
- moveq r3, #0
- str r3, [r2, #-3328]
- ldr r3, [sp, #56]
- str r3, [r9, #12]
- ldrh r3, [r5]
- strh r3, [r9, #2] @ movhi
- ldr r3, [r4, #2440]
- add r3, r3, #1
- str r3, [r4, #2440]
- ldr r3, [sp, #16]
- add r3, r3, #1
- b .L3851
-.L3796:
- ldr r3, [sp]
- ldr r2, [sp, #16]
- ldr r1, [sp, #20]
- rsb r3, r2, r3
- ldr r2, .L3854
- str r3, [sp]
- ldr r3, [r4, #2440]
- ldr r2, [r2, #-540]
- cmp r3, r2
- orrcs r1, r1, #1
- cmp r1, #0
- bne .L3814
- ldrh r3, [r5, #4]
- cmp r3, #0
- beq .L3814
-.L3816:
- mov r3, #0
- str r3, [sp, #20]
- b .L3788
-.L3814:
- bl FtlCacheWriteBack
- mov r3, #0
- str r3, [r10, #2440]
- ldr r3, [sp]
- cmp r3, #1
- bhi .L3788
- b .L3816
-.L3853:
- mov r0, r3
- ldr r2, [sp, #8]
- ldr r3, [sp, #28]
- rsb r1, r2, r3
+ sub r1, r3, r2
bl ftl_do_gc
- ldr r3, .L3854+44
- ldrh r3, [r3, #-8]
+ ldr r2, .L3768+12
+ ldrh r3, [r2, #-4]
+ mov r4, r2
cmp r3, #5
- bls .L3827
+ bls .L3737
cmp r3, #31
- bhi .L3821
- ldr r3, .L3854+8
- ldrb r3, [r3] @ zero_extendqisi2
+ bhi .L3741
+ ldr r3, .L3768+8
+ ldrb r3, [r3, #36] @ zero_extendqisi2
cmp r3, #0
- bne .L3821
-.L3827:
- ldr r4, [sp]
- ldr r5, .L3854+48
- ldr r6, .L3854
- ldr r7, .L3854+52
-.L3840:
- ldrh r2, [r5]
+ bne .L3741
+.L3737:
+ ldr r5, .L3768+16
+.L3740:
+ ldr r3, .L3768+20
+ ldrh r2, [r3]
movw r3, #65535
cmp r2, r3
- bne .L3820
- ldrh r3, [r7]
+ bne .L3739
+ ldr r3, .L3768+24
+ ldrh r3, [r3]
cmp r3, r2
- bne .L3820
- ldr r2, .L3854+56
- ldrh r2, [r2]
+ bne .L3739
+ ldrh r2, [r5, #-8]
cmp r2, r3
- bne .L3820
- and r0, r4, #7
+ bne .L3739
+ and r0, r8, #7
bl List_get_gc_head_node
uxth r0, r0
bl FtlGcRefreshBlock
-.L3820:
- ldr r3, .L3854+60
- mov r0, #1
- mov r1, r0
+.L3739:
+ ldr r3, .L3768+28
+ mov r1, #1
mov r2, #128
+ mov r0, r1
strh r2, [r3] @ movhi
strh r2, [r3, #-2] @ movhi
bl ftl_do_gc
- mov r0, #0
mov r1, #1
- bl ftl_do_gc
- ldr r3, [r6, #-3616]
- cmp r3, #0
- bne .L3821
- ldr r3, .L3854+64
- ldrh r3, [r3]
- cmp r3, #2
- bhi .L3821
- add r4, r4, #1
- cmp r4, #256
- bne .L3840
- b .L3821
-.L3824:
- mvn r0, #0
- b .L3781
-.L3821:
mov r0, #0
-.L3781:
- add sp, sp, #100
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3855:
+ bl ftl_do_gc
+ ldr r3, .L3768
+ ldr r3, [r3, #-3612]
+ cmp r3, #0
+ bne .L3741
+ ldrh r3, [r4, #-4]
+ cmp r3, #2
+ bhi .L3741
+ add r8, r8, #1
+ cmp r8, #256
+ bne .L3740
+ b .L3741
+.L3745:
+ str fp, [sp, #12]
+ b .L3704
+.L3736:
+ ldrh r1, [r5, #4]
+ ldr r4, .L3768
+ cmp r1, #0
+ bne .L3709
+ sub r2, r4, #3520
+ ldr fp, .L3768+4
+ cmp r5, r2
+ bne .L3710
+ sub r0, r4, #3472
+ ldrh r5, [r0, #4]
+ cmp r5, #0
+ bne .L3711
+ bl allocate_new_data_superblock
+ str r5, [fp, #3448]
+.L3711:
+ ldr r0, .L3768+12
+ bl allocate_new_data_superblock
+ ldr r5, .L3768+12
+ ldr r1, [fp, #3448]
+ add r2, r5, #48
+ cmp r1, #0
+ movne r5, r2
+.L3712:
+ ldrh r2, [r5, #4]
+ cmp r2, #0
+ bne .L3713
+ mov r0, r5
+ bl allocate_new_data_superblock
+.L3713:
+ str r5, [r4, #1992]
+.L3709:
+ ldr r1, [r10, #2444]
+ ldr r2, [r4, #-540]
+ sub r2, r2, r1
+ ldrh r1, [r5, #4]
+ cmp r2, r8
+ movcs r2, r8
+ cmp r1, r2
+ movcc r3, r1
+ movcs r3, r2
+ str r3, [sp, #36]
+ mov r3, #0
+.L3766:
+ str r3, [sp, #20]
+ ldr r3, [sp, #20]
+ ldr r2, [sp, #36]
+ cmp r3, r2
+ bne .L3732
+.L3715:
+ ldr r3, [sp, #20]
+ ldr r1, .L3768
+ ldr r2, [r10, #2444]
+ sub r8, r8, r3
+ ldr r3, [sp, #16]
+ ldr r1, [r1, #-540]
+ cmp r2, r1
+ orrcs r3, r3, #1
+ cmp r3, #0
+ bne .L3733
+ ldrh r2, [r5, #4]
+ cmp r2, #0
+ beq .L3733
+.L3735:
+ mov r3, #0
+ str r3, [sp, #16]
+ b .L3708
+.L3710:
+ str r1, [fp, #3448]
+ ldrh r1, [r2, #4]
+ cmp r1, #0
+ movne r5, r2
+ bne .L3713
+ mov r0, r5
+ bl allocate_new_data_superblock
+ b .L3712
+.L3732:
+ ldrh r2, [r5, #4]
+ cmp r2, #0
+ beq .L3715
+ ldr r3, [sp, #24]
+ sub r4, r3, r6
+ ldr r3, [sp, #16]
+ clz r4, r4
+ lsr r4, r4, #5
+ and r2, r4, r3
+ ldr r3, [sp, #20]
+ cmp r3, #0
+ moveq r2, #0
+ andne r2, r2, #1
+ cmp r2, #0
+ beq .L3716
+ ldr r3, .L3768+32
+ add r2, r7, r9
+ ldrh r1, [r3]
+ mls r2, r1, r6, r2
+ cmp r1, r2
+ bne .L3715
+.L3716:
+ mov r2, #0
+ add r1, sp, #40
+ mov r0, r6
+ mov fp, #36
+ bl log2phys
+ mov r0, r5
+ bl get_new_active_ppa
+ ldr r2, .L3768+36
+ ldr r1, [r10, #2444]
+ ldr ip, [r10, #2448]
+ ldrh r2, [r2]
+ mla ip, fp, r1, ip
+ mul lr, r2, r1
+ str r0, [ip, #4]
+ ldr r0, .L3768
+ bic r3, lr, #3
+ str r6, [ip, #16]
+ str r3, [sp, #28]
+ ldr lr, [sp, #28]
+ ldr r3, [r0, #-492]
+ ldr r0, [r0, #-512]
+ str r3, [sp, #32]
+ add r3, r3, lr
+ str r3, [sp, #8]
+ str r3, [ip, #12]
+ ldr r3, .L3768+40
+ ldrh lr, [r3]
+ mul r1, r1, lr
+ bic r1, r1, #3
+ add r1, r0, r1
+ ldr r0, [sp, #8]
+ str r1, [ip, #8]
+ mov r1, #0
+ bl ftl_memset
+ ldr r3, [sp, #4]
+ cmp r3, r6
+ orreq r4, r4, #1
+ cmp r4, #0
+ beq .L3717
+ cmp r3, r6
+ bne .L3718
+ ldr r3, .L3768+32
+ mov r0, r7
+ ldrh r4, [r3]
+ mov r1, r4
+ bl __aeabi_uidivmod
+ sub r4, r4, r1
+ mov fp, r1
+ cmp r4, r9
+ movcs r4, r9
+.L3719:
+ ldr r3, .L3768+32
+ ldrh r2, [r3]
+ cmp r2, r4
+ bne .L3720
+ ldr r3, [sp, #4]
+ cmp r3, r6
+ mulne r1, r4, r6
+ ldrne r3, [sp, #12]
+ ldreq r1, [sp, #12]
+ subne r1, r1, r7
+ addne r1, r3, r1, lsl #9
+ ldr r3, [sp, #16]
+ cmp r3, #0
+ beq .L3722
+ ldr r2, [r10, #2444]
+ mov ip, #36
+ ldr r0, [r10, #2448]
+ mla r2, ip, r2, r0
+ str r1, [r2, #8]
+.L3723:
+ ldr r2, .L3768+44
+ ldr r3, [sp, #32]
+ ldr r1, [sp, #28]
+ strh r2, [r3, r1] @ movhi
+ ldr r1, .L3768
+ ldr r3, [sp, #8]
+ ldr r2, [r1, #-3328]
+ str r2, [r3, #4]
+ add r2, r2, #1
+ cmn r2, #1
+ ldr r3, [sp, #8]
+ moveq r2, #0
+ str r2, [r1, #-3328]
+ ldr r2, [sp, #40]
+ str r6, [r3, #8]
+ add r6, r6, #1
+ str r2, [r3, #12]
+ ldrh r2, [r5]
+ strh r2, [r3, #2] @ movhi
+ ldr r2, [r10, #2444]
+ ldr r3, [sp, #20]
+ add r2, r2, #1
+ str r2, [r10, #2444]
+ add r3, r3, #1
+ b .L3766
+.L3718:
+ ldr r3, .L3768+32
+ add r4, r7, r9
+ mov fp, #0
+ ldrh r2, [r3]
+ smulbb r2, r2, r6
+ sub r4, r4, r2
+ uxth r4, r4
+ b .L3719
+.L3722:
+ ldr r2, [r10, #2448]
+ mov ip, #36
+ ldr r0, [r10, #2444]
+ mla r0, ip, r0, r2
+ ldr r2, .L3768+40
+ ldrh r2, [r2]
+.L3767:
+ ldr r0, [r0, #8]
+ b .L3764
+.L3720:
+ ldr r2, [sp, #40]
+ cmn r2, #1
+ beq .L3724
+ ldr r1, [r10, #2448]
+ mov r0, #36
+ str r2, [sp, #48]
+ ldr r2, [r10, #2444]
+ str r6, [sp, #60]
+ mla r2, r0, r2, r1
+ add r0, sp, #44
+ ldr r1, [r2, #8]
+ ldr r2, [r2, #12]
+ str r1, [sp, #52]
+ mov r1, #1
+ str r2, [sp, #56]
+ mov r2, #0
+ bl FlashReadPages
+ ldr r2, [sp, #44]
+ cmn r2, #1
+ ldr r2, .L3768
+ ldreq r1, [r2, #-3164]
+ addeq r1, r1, #1
+ streq r1, [r2, #-3164]
+ beq .L3727
+ ldr r3, [sp, #8]
+ ldr r1, [r3, #8]
+ cmp r6, r1
+ beq .L3727
+ ldr r1, [r2, #-3164]
+ ldr r0, .L3768+48
+ add r1, r1, #1
+ str r1, [r2, #-3164]
+ mov r2, r6
+ ldr r1, [r3, #8]
+ bl printk
+.L3727:
+ ldr r3, [sp, #4]
+ lsl r2, r4, #9
+ cmp r3, r6
+ bne .L3728
+ ldr r0, [r10, #2448]
+ mov ip, #36
+ ldr r1, [r10, #2444]
+ mla r1, ip, r1, r0
+ ldr r0, [r1, #8]
+ ldr r1, [sp, #12]
+ add r0, r0, fp, lsl #9
+.L3764:
+ bl ftl_memcpy
+ b .L3723
+.L3724:
+ ldr r2, [r10, #2448]
+ mov r1, #36
+ ldr r0, [r10, #2444]
+ mla r0, r1, r0, r2
+ ldr r2, .L3768+40
+ mov r1, #0
+ ldrh r2, [r2]
+ ldr r0, [r0, #8]
+ bl ftl_memset
+ b .L3727
+.L3728:
+ ldr r3, .L3768+32
+ mov lr, #36
+ ldr r0, [r10, #2444]
+ ldr ip, [r10, #2448]
+ ldrh r1, [r3]
+ ldr r3, [sp, #12]
+ mla r0, lr, r0, ip
+ mul r1, r6, r1
+ sub r1, r1, r7
+ add r1, r3, r1, lsl #9
+ b .L3767
+.L3717:
+ ldr r3, [sp, #16]
+ cmp r3, #0
+ beq .L3729
+ ldr r2, [r10, #2444]
+ ldr r1, [r10, #2448]
+ ldr r3, .L3768+32
+ mla fp, fp, r2, r1
+ ldrh r2, [r3]
+ ldr r3, [sp, #12]
+ mul r2, r6, r2
+ sub r2, r2, r7
+ add r2, r3, r2, lsl #9
+ str r2, [fp, #8]
+ b .L3723
+.L3729:
+ ldr r3, .L3768+32
+ ldr r2, [r10, #2444]
+ ldr r0, [r10, #2448]
+ ldrh r1, [r3]
+ mla fp, fp, r2, r0
+ ldrh r2, [r3, #4]
+ ldr r3, [sp, #12]
+ mul r1, r6, r1
+ ldr r0, [fp, #8]
+ sub r1, r1, r7
+ add r1, r3, r1, lsl #9
+ b .L3764
+.L3733:
+ bl FtlCacheWriteBack
+ cmp r8, #1
+ mov r2, #0
+ str r2, [r10, #2444]
+ bhi .L3708
+ b .L3735
+.L3744:
+ mvn r0, #0
+ b .L3700
+.L3769:
.align 2
-.L3854:
+.L3768:
.word .LANCHOR2
.word .LANCHOR1
.word .LANCHOR0
- .word .LANCHOR4
- .word .LANCHOR2-3524
- .word .LANCHOR2-3476
- .word .LANCHOR0+2394
- .word .LANCHOR0+2400
- .word .LANCHOR0+2398
- .word .LC166
- .word -3947
.word .LANCHOR2-3520
+ .word .LANCHOR2-2656
.word .LANCHOR2-3284
.word .LANCHOR2-2666
- .word .LANCHOR2-2664
.word .LANCHOR2-2718
- .word .LANCHOR2-3528
+ .word .LANCHOR0+2396
+ .word .LANCHOR0+2402
+ .word .LANCHOR0+2400
+ .word -3947
+ .word .LC166
.fnend
.size ftl_write, .-ftl_write
.align 2
.global ftl_vendor_write
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_vendor_write, %function
ftl_vendor_write:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- str lr, [sp, #-4]!
- .save {lr}
- mov ip, r1
- mov lr, r0
+ @ link register save eliminated.
mov r3, r2
- mov r1, lr
+ mov r2, r1
+ mov r1, r0
mov r0, #16
- mov r2, ip
- ldr lr, [sp], #4
b ftl_write
.fnend
.size ftl_vendor_write, .-ftl_vendor_write
.align 2
.global FlashBootVendorWrite
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FlashBootVendorWrite, %function
FlashBootVendorWrite:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
- mov r4, r2
- mov r6, r0
+ mov r4, r0
mov r5, r1
+ mov r6, r2
bl rknand_device_lock
- ldr r3, .L3862
- ldr r3, [r3, #504]
+ ldr r3, .L3775
+ ldr r3, [r3, #500]
cmp r3, #1
mvnne r4, #0
- bne .L3859
- mov r2, r4
- mov r0, r6
+ bne .L3772
+ mov r0, r4
+ mov r2, r6
mov r1, r5
bl ftl_vendor_write
mov r4, r0
-.L3859:
+.L3772:
bl rknand_device_unlock
mov r0, r4
- ldmfd sp!, {r4, r5, r6, pc}
-.L3863:
+ pop {r4, r5, r6, pc}
+.L3776:
.align 2
-.L3862:
+.L3775:
.word .LANCHOR1
.fnend
.size FlashBootVendorWrite, .-FlashBootVendorWrite
.align 2
.global ftl_sys_write
+ .syntax unified
+ .arm
+ .fpu softvfp
.type ftl_sys_write, %function
ftl_sys_write:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- mov ip, r1
mov r3, r2
+ mov r2, r1
add r1, r0, #256
- mov r2, ip
mov r0, #16
b ftl_write
.fnend
.size ftl_sys_write, .-ftl_sys_write
.align 2
.global StorageSysDataStore
+ .syntax unified
+ .arm
+ .fpu softvfp
.type StorageSysDataStore, %function
StorageSysDataStore:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- mov r4, r1
- mov r5, r0
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r5, r1
+ mov r4, r0
bl rknand_device_lock
- mov r2, r4
+ mov r2, r5
mov r1, #1
- mov r0, r5
+ mov r0, r4
bl ftl_sys_write
mov r4, r0
bl rknand_device_unlock
mov r0, r4
- ldmfd sp!, {r3, r4, r5, pc}
+ pop {r4, r5, r6, pc}
.fnend
.size StorageSysDataStore, .-StorageSysDataStore
.align 2
.global FtlDumpSysBlock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlDumpSysBlock, %function
FtlDumpSysBlock:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
- .save {r4, r5, r6, r7, r8, r9, lr}
- mov r8, r0, asl #10
- ldr r4, .L3876
- .pad #28
- sub sp, sp, #28
- ldr r7, .L3876+4
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
+ lsl r8, r0, #10
+ ldr r4, .L3788
+ .pad #24
+ sub sp, sp, #24
mov r6, r0
mov r5, #0
+ ldr r7, .L3788+4
ldr r3, [r4, #-524]
- mov r9, r4
- str r3, [r4, #1760]
+ add r9, r4, #1760
+ ldr r10, .L3788+8
+ str r3, [r4, #1768]
ldr r3, [r4, #-500]
- str r3, [r4, #1764]
-.L3868:
+ str r3, [r4, #1772]
+.L3781:
ldrh r2, [r7]
sxth r3, r5
cmp r3, r2
- bge .L3875
- mov r1, #1
- ldr r0, .L3876+8
- mov r2, r1
+ blt .L3783
+ add sp, sp, #24
+ @ sp needed
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3783:
+ mov r2, #1
orr r3, r3, r8
- str r3, [r4, #1756]
+ mov r1, r2
+ mov r0, r9
+ str r3, [r4, #1764]
bl FlashReadPages
- ldr r3, [r4, #1764]
+ ldr r2, [r4, #1768]
mov r1, r6
- ldr r0, .L3876+12
- ldr r2, [r3]
- str r2, [sp]
- ldr r2, [r3, #4]
- str r2, [sp, #4]
+ ldr r3, [r4, #1772]
+ mov r0, r10
+ ldr r2, [r2]
+ str r2, [sp, #16]
+ ldr r2, [r3, #12]
+ str r2, [sp, #12]
ldr r2, [r3, #8]
str r2, [sp, #8]
- ldr r3, [r3, #12]
- ldr r2, [r4, #1752]
- str r3, [sp, #12]
- ldr r3, [r4, #1760]
+ ldr r2, [r3, #4]
+ str r2, [sp, #4]
ldr r3, [r3]
- str r3, [sp, #16]
- ldr r3, [r4, #1756]
- bl printk
+ ldr r2, [r4, #1760]
+ str r3, [sp]
ldr r3, [r4, #1764]
+ bl printk
+ ldr r3, [r4, #1772]
ldr r3, [r3]
cmn r3, #1
- beq .L3869
- ldr r0, .L3876+16
- mov r2, #4
- ldr r1, [r9, #-524]
+ beq .L3782
mov r3, #768
+ mov r2, #4
+ ldr r1, [r4, #-524]
+ ldr r0, .L3788+12
bl rknand_print_hex
-.L3869:
+.L3782:
add r5, r5, #1
- b .L3868
-.L3875:
- add sp, sp, #28
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L3877:
+ b .L3781
+.L3789:
.align 2
-.L3876:
+.L3788:
.word .LANCHOR2
- .word .LANCHOR0+2390
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2392
.word .LC167
.word .LC168
.fnend
.size FtlDumpSysBlock, .-FtlDumpSysBlock
.align 2
.global dump_map_info
+ .syntax unified
+ .arm
+ .fpu softvfp
.type dump_map_info, %function
dump_map_info:
.fnstart
- @ args = 0, pretend = 0, frame = 24
+ @ args = 0, pretend = 0, frame = 16
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L3805
+ movw r2, #2332
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- movw r3, #2328
- ldr r6, .L3896
- .pad #52
- sub sp, sp, #52
- ldr r10, .L3896+4
- ldrh r7, [r6, r3]
- add fp, r10, #18
-.L3879:
- ldrh r3, [r10]
- ldr r4, .L3896+8
- cmp r3, r7
- bls .L3892
- ldr r1, .L3896+12
- mov r8, #0
- ldr r2, [r4, #-536]
- mov r5, r8
- ldr r3, [r4, #-2696]
- ldrh ip, [r1]
- ldr r9, [r4, #-2692]
- ldrh r1, [r1, #80]
- str r1, [sp, #28]
-.L3888:
- uxth r1, r8
- cmp r1, ip
- bcs .L3894
- mov r1, r7
- ldrb r0, [fp, r8] @ zero_extendqisi2
- str r3, [sp, #44]
- str r2, [sp, #40]
- str ip, [sp, #36]
+ .pad #44
+ sub sp, sp, #44
+ ldrh r6, [r3, r2]
+ str r3, [sp, #24]
+.L3791:
+ ldr r3, .L3805+4
+ ldr r4, .L3805+8
+ ldrh r3, [r3]
+ cmp r3, r6
+ bhi .L3798
+ ldr r10, .L3805+12
+ mov r7, #0
+ sub r9, r4, #388
+ add fp, r4, #1760
+.L3799:
+ ldrh r3, [r9]
+ sxth r5, r7
+ cmp r5, r3
+ bge .L3802
+ lsl r5, r5, #1
+ mov r6, #0
+ ldr r8, .L3805+16
+ b .L3803
+.L3793:
+ str r3, [sp, #32]
+ mov r1, r6
+ ldr r3, .L3805+20
+ str r2, [sp, #36]
+ ldrb r0, [r3, r7] @ zero_extendqisi2
bl V2P_block
- str r0, [sp, #32]
+ str r0, [sp, #28]
bl FtlBbmIsBadBlock
cmp r0, #0
- ldr r1, [sp, #32]
- ldr ip, [sp, #36]
- ldr r2, [sp, #40]
- ldr r3, [sp, #44]
- bne .L3880
- mov r0, #36
- mov r1, r1, asl #10
- mla r0, r0, r5, r2
- stmib r0, {r1, r3}
+ ldr r3, [sp, #32]
+ ldr r2, [sp, #36]
+ bne .L3792
ldr r1, [sp, #28]
- mul r1, r1, r5
+ mla r0, r2, r5, r8
+ lsl r1, r1, #10
+ stmib r0, {r1, fp}
+ mul r1, r9, r5
add r5, r5, #1
uxth r5, r5
- add lr, r1, #3
+ add ip, r1, #3
cmp r1, #0
- movlt r1, lr
+ movlt r1, ip
bic r1, r1, #3
- add r1, r9, r1
+ add r1, r10, r1
str r1, [r0, #12]
-.L3880:
- add r8, r8, #1
- b .L3888
-.L3894:
+.L3792:
+ add r7, r7, #1
+.L3800:
+ uxth r1, r7
+ cmp r3, r1
+ bhi .L3793
cmp r5, #0
- beq .L3883
- ldr r0, [r4, #-536]
- mov r1, r5
- mov r2, #1
- mov r8, #0
- bl FlashReadPages
- mov r9, #36
-.L3884:
- uxth r3, r8
- cmp r3, r5
- bcs .L3883
- ldr r3, [r4, #-536]
- ldr r0, .L3896+16
- mla r3, r9, r8, r3
- add r8, r8, #1
- ldmib r3, {r2, r3, ip}
- ldr r1, [ip, #4]
- str r1, [sp]
- ldr r1, [ip, #8]
- str r1, [sp, #4]
- ldr r1, [ip, #12]
- str r1, [sp, #8]
- ldr r1, [r3]
- str r1, [sp, #12]
- ubfx r1, r2, #10, #16
- ldr r3, [r3, #4]
- str r3, [sp, #16]
- ldr r3, [ip]
- bl printk
- b .L3884
-.L3883:
- add r7, r7, #1
- uxth r7, r7
- b .L3879
-.L3892:
- ldr r9, .L3896+20
- mov r8, #0
-.L3887:
- ldr r7, .L3896+8
- sxth r5, r8
- sub r3, r7, #388
- ldrh r3, [r3]
- cmp r5, r3
- bge .L3890
- mov r5, r5, asl #1
+ bne .L3794
+.L3797:
+ add r6, r6, #1
+ uxth r6, r6
+ b .L3791
+.L3794:
+ ldr r9, .L3805+24
+ mov r0, r8
mov r7, #0
-.L3891:
- ldrh r2, [r9]
- sxth r3, r7
- add r7, r7, #1
- cmp r3, r2
- bge .L3895
- ldr r2, [r4, #-472]
- mov r1, #1
- ldr r0, .L3896+24
- ldrh r2, [r2, r5]
- orr r3, r3, r2, asl #10
- mov r2, r1
- str r3, [r4, #1756]
+ mov r8, #36
+ mov r2, #1
+ mov r1, r5
bl FlashReadPages
- ldr r3, [r4, #1764]
- ldr r1, [r4, #-472]
- ldr r2, [r4, #1760]
- ldr r0, [r3]
- ldrh r1, [r1, r5]
- str r0, [sp]
+.L3795:
+ uxth r3, r7
+ cmp r5, r3
+ bls .L3797
+ ldr r3, [r4, #-536]
+ mla r3, r8, r7, r3
+ add r7, r7, #1
+ ldr r1, [r3, #12]
+ ldr r2, [r3, #4]
+ ldr r3, [r3, #8]
ldr r0, [r3, #4]
- str r0, [sp, #4]
- ldr r0, [r3, #8]
- str r0, [sp, #8]
- ldr r3, [r3, #12]
- ldr r0, .L3896+28
+ str r0, [sp, #16]
+ mov r0, r9
+ ldr r3, [r3]
str r3, [sp, #12]
- ldr r3, [r2]
- str r3, [sp, #16]
- ldr r3, [r2, #4]
- str r3, [sp, #20]
- ldr r2, [r4, #1752]
- ldr r3, [r4, #1756]
+ ldr r3, [r1, #12]
+ str r3, [sp, #8]
+ ldr r3, [r1, #8]
+ str r3, [sp, #4]
+ ldr r3, [r1, #4]
+ str r3, [sp]
+ ldr r3, [r1]
+ ubfx r1, r2, #10, #16
bl printk
- b .L3891
-.L3895:
- add r8, r8, #1
- b .L3887
-.L3890:
- ldr r1, [r7, #-472]
- movw r4, #2424
- ldr r3, [r6, #2416]
+ b .L3795
+.L3798:
+ ldr r2, .L3805+28
+ mov r7, #0
+ ldr r8, [r4, #-536]
+ mov r5, r7
+ ldr fp, [r4, #-2696]
+ ldrh r3, [r2]
+ ldrh r9, [r2, #78]
+ mov r2, #36
+ ldr r10, [r4, #-2692]
+ b .L3800
+.L3801:
+ ldr r2, [r4, #-472]
+ mov r0, fp
+ ldrh r2, [r2, r5]
+ orr r3, r3, r2, lsl #10
+ mov r2, #1
+ mov r1, r2
+ str r3, [r4, #1764]
+ bl FlashReadPages
+ ldr r2, [r4, #1768]
+ ldr r1, [r4, #-472]
+ ldr r3, [r4, #1772]
+ ldr r0, [r2, #4]
+ ldrh r1, [r1, r5]
+ str r0, [sp, #20]
+ mov r0, r8
+ ldr r2, [r2]
+ str r2, [sp, #16]
+ ldr r2, [r3, #12]
+ str r2, [sp, #12]
+ ldr r2, [r3, #8]
+ str r2, [sp, #8]
+ ldr r2, [r3, #4]
+ str r2, [sp, #4]
+ ldr r3, [r3]
+ ldr r2, [r4, #1760]
+ str r3, [sp]
+ ldr r3, [r4, #1764]
+ bl printk
+.L3803:
+ ldrh r2, [r10]
+ sxth r3, r6
+ add r6, r6, #1
+ cmp r3, r2
+ blt .L3801
+ add r7, r7, #1
+ b .L3799
+.L3802:
+ ldr r3, [sp, #24]
mov r2, #2
- ldr r0, .L3896+32
+ ldr r1, [r4, #-472]
+ movw r5, #2428
+ ldr r0, .L3805+32
+ ldr r3, [r3, #2420]
bl rknand_print_hex
- ldr r1, [r7, #-452]
- ldrh r3, [r6, r4]
+ ldr r3, [sp, #24]
mov r2, #4
- ldr r0, .L3896+36
+ ldr r1, [r4, #-452]
+ ldr r0, .L3805+36
+ ldrh r3, [r3, r5]
bl rknand_print_hex
- ldr r0, .L3896+40
- ldr r1, [r7, #-448]
+ ldr r3, [sp, #24]
mov r2, #4
- ldrh r3, [r6, r4]
- add sp, sp, #52
+ ldr r1, [r4, #-448]
+ ldr r0, .L3805+40
+ ldrh r3, [r3, r5]
+ add sp, sp, #44
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, lr}
b rknand_print_hex
-.L3897:
+.L3806:
.align 2
-.L3896:
+.L3805:
.word .LANCHOR0
- .word .LANCHOR0+2330
+ .word .LANCHOR0+2334
.word .LANCHOR2
- .word .LANCHOR0+2320
- .word .LC169
- .word .LANCHOR0+2390
- .word .LANCHOR2+1752
+ .word .LANCHOR0+2392
.word .LC113
+ .word .LANCHOR0+2350
+ .word .LC169
+ .word .LANCHOR0+2324
.word .LC170
.word .LC171
.word .LC172
@@ -23376,493 +23915,483 @@
.size dump_map_info, .-dump_map_info
.align 2
.global flash_boot_enter_slc_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type flash_boot_enter_slc_mode, %function
flash_boot_enter_slc_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L3900
- ldr r2, [r3, #2264]
- ldr r3, .L3900+4
+ ldr r3, .L3809
+ ldr r2, [r3, #2268]
+ ldr r3, .L3809+4
cmp r2, r3
bxne lr
b flash_enter_slc_mode
-.L3901:
+.L3810:
.align 2
-.L3900:
+.L3809:
.word .LANCHOR0
.word 1446522928
.fnend
.size flash_boot_enter_slc_mode, .-flash_boot_enter_slc_mode
.align 2
.global flash_boot_exit_slc_mode
+ .syntax unified
+ .arm
+ .fpu softvfp
.type flash_boot_exit_slc_mode, %function
flash_boot_exit_slc_mode:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
- ldr r3, .L3904
- ldr r2, [r3, #2264]
- ldr r3, .L3904+4
+ ldr r3, .L3813
+ ldr r2, [r3, #2268]
+ ldr r3, .L3813+4
cmp r2, r3
bxne lr
b flash_exit_slc_mode
-.L3905:
+.L3814:
.align 2
-.L3904:
+.L3813:
.word .LANCHOR0
.word 1446522928
.fnend
.size flash_boot_exit_slc_mode, .-flash_boot_exit_slc_mode
.align 2
.global write_idblock
+ .syntax unified
+ .arm
+ .fpu softvfp
.type write_idblock, %function
write_idblock:
.fnstart
- @ args = 0, pretend = 0, frame = 120
+ @ args = 0, pretend = 0, frame = 112
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r8, r0
- ldr r7, .L3959
- .pad #132
- sub sp, sp, #132
+ mov r6, r0
+ ldr r4, .L3864
+ .pad #124
+ sub sp, sp, #124
mov r0, #256000
- mov fp, r1
- mov r6, r2
- ldr r3, [r7, #44]
- ldr r4, [r7, #4]
- ldrb r5, [r3, #9] @ zero_extendqisi2
+ mov r10, r1
+ mov r5, r2
+ ldr r3, [r4, #48]
+ ldr r8, [r4, #40]
+ ldrb r7, [r3, #9] @ zero_extendqisi2
bl ftl_malloc
subs r3, r0, #0
str r3, [sp, #8]
- beq .L3933
- add ip, r8, #508
- add ip, ip, #3
- mov r10, ip, lsr #9
- cmp r10, #8
- bls .L3931
- cmp r10, #500
- bhi .L3933
- b .L3908
-.L3931:
- mov r10, #8
-.L3908:
- ldr r2, [fp]
- ldr r3, .L3959+4
+ beq .L3842
+ add r0, r6, #508
+ add r0, r0, #3
+ lsr r9, r0, #9
+ cmp r9, #8
+ bls .L3840
+ cmp r9, #500
+ bhi .L3842
+.L3817:
+ ldr r2, [r10]
+ ldr r3, .L3864+4
cmp r2, r3
- bne .L3933
- smulbb r3, r5, r4
- uxth r3, r3
- str r3, [sp, #12]
- sub r0, r3, #1
- mov r1, r3
- add r0, r0, r10
+ bne .L3842
+ smulbb r7, r7, r8
+ uxth fp, r7
+ sub r0, fp, #1
+ mov r1, fp
+ add r0, r0, r9
bl __aeabi_uidiv
+ str r0, [sp, #32]
+ add r0, r10, #254976
+ add r0, r0, #512
mov r3, #0
movw r2, #63871
- str r0, [sp, #36]
- add r0, fp, #254976
- add r0, r0, #512
-.L3912:
+.L3821:
ldr r1, [r0, #-4]!
cmp r1, #0
- bne .L3909
- ldr r1, [fp, r3, asl #2]
+ bne .L3818
+ ldr r1, [r10, r3, lsl #2]
add r3, r3, #1
cmp r3, #4096
sub r2, r2, #1
movhi r3, #0
cmp r2, #4096
str r1, [r0, #512]
- bne .L3912
- b .L3911
-.L3909:
- ldr r0, .L3959+8
- bl printk
-.L3911:
+ bne .L3821
+.L3820:
mov r3, #5
- ldr r0, .L3959+12
- mov r1, r6
+ mov r1, r5
mov r2, #4
+ ldr r0, .L3864+8
bl rknand_print_hex
- ldr r1, [fp, #512]
- ldrb r2, [r7, #1] @ zero_extendqisi2
- sub r4, r6, #4
- ldr r0, .L3959+16
+ ldrb r2, [r4, #37] @ zero_extendqisi2
+ sub r5, r5, #4
+ ldr r1, [r10, #512]
+ ldr r0, .L3864+12
bl printk
- ldr r2, .L3959+20
- ldrh r3, [r7, #142]
- mov r1, r10
- ldr r0, .L3959+24
- ldr r2, [r2, #1708]
- ldr r5, .L3959
+ ldr r2, .L3864+16
+ mov r1, r9
+ ldrh r3, [r4, #150]
+ ldr r0, .L3864+20
+ ldr r2, [r2, #1716]
str r2, [sp]
- mov r2, r10
+ mov r2, r9
bl printk
- ldrb r3, [r7, #1] @ zero_extendqisi2
- ldr r2, [fp, #512]
+ ldrb r3, [r4, #37] @ zero_extendqisi2
+ ldr r2, [r10, #512]
+ ldr r4, .L3864
cmp r2, r3
- strhi r3, [fp, #512]
- mov r3, r10, asl #7
+ strhi r3, [r10, #512]
+ lsl r3, r9, #7
str r3, [sp, #40]
mov r3, #0
str r3, [sp, #20]
- str r3, [sp, #16]
-.L3929:
- ldr r2, [r4, #4]
- ldrb r3, [r5, #1] @ zero_extendqisi2
- ldr r7, .L3959
+ str r3, [sp, #12]
+.L3838:
+ ldr r2, [r5, #4]
+ ldrb r3, [r4, #37] @ zero_extendqisi2
cmp r2, r3
- bcs .L3914
- ldr r3, .L3959+20
- ldr r3, [r3, #1708]
+ bcs .L3823
+ ldr r3, .L3864+16
+ ldr r3, [r3, #1716]
cmp r2, r3
- bcc .L3914
- ldr r3, [sp, #36]
- ldr r1, [sp, #36]
- cmp r3, #1
- movls r3, #0
- movhi r3, #1
- str r3, [sp, #44]
- ldr r3, [sp, #16]
- cmp r3, #0
- cmpne r1, #1
- bls .L3915
- ldr r3, [r4]
+ bcc .L3823
+ ldr r3, [sp, #32]
+ ldr r1, [sp, #12]
+ cmp r1, #0
+ cmpne r3, #1
+ bls .L3824
+ ldr r3, [r5]
add r3, r3, #1
cmp r2, r3
- beq .L3914
-.L3915:
- mov r1, #0
+ beq .L3823
+.L3824:
mov r2, #512
+ mov r1, #0
ldr r0, [sp, #8]
bl memset
- ldr r6, [r4, #4]
- mov r2, r10
- ldr r0, .L3959+28
- ldr r3, [sp, #12]
- mul r6, r6, r3
- ldr r3, [r7, #44]
- ldr r7, [r7, #4]
- ldrb r9, [r3, #9] @ zero_extendqisi2
+ ldr r3, [r4, #48]
+ mov r2, r9
+ ldr r6, [r5, #4]
+ ldr r7, [r4, #40]
+ ldrb r3, [r3, #9] @ zero_extendqisi2
+ ldr r0, .L3864+24
+ mul r6, r6, fp
+ str r3, [sp, #16]
+ ldrh r3, [sp, #16]
mov r1, r6
+ smulbb r7, r7, r3
bl printk
mov r0, #0
- bl flash_boot_enter_slc_mode
- mov r1, r9
- mov r0, r6
- bl __aeabi_uidiv
- smulbb r7, r7, r9
uxth r7, r7
+ bl flash_boot_enter_slc_mode
+ mov r0, r6
+ ldr r1, [sp, #16]
+ bl __aeabi_uidiv
+ mov r2, #0
mov r1, r0
- mov r0, #0
- mov r2, r0
+ mov r0, r2
bl FlashEraseBlock
- cmp r10, r7
- movls r8, #1
- bls .L3916
- mov r0, #0
- add r1, r6, r7
- mov r2, r0
+ cmp r7, r9
+ movcs r8, #1
+ bcs .L3825
+ mov r2, #0
mov r8, #2
+ add r1, r6, r7
+ mov r0, r2
bl FlashEraseBlock
-.L3916:
+.L3825:
mov r0, #0
bl flash_boot_exit_slc_mode
- ldr r3, [r5, #44]
+ ldr r3, [r4, #48]
ldrh r0, [r3, #10]
ldrb r1, [r3, #12] @ zero_extendqisi2
- mov r0, r0, asl #2
+ lsl r0, r0, #2
mul r0, r8, r0
+ mov r8, #0
bl __aeabi_idiv
mov r1, r7
- mov r8, #0
- str r0, [sp, #48]
+ str r0, [sp, #44]
mov r0, r6
bl __aeabi_uidivmod
- mov ip, r1
- rsb r3, r1, r6
- str fp, [sp, #24]
- str r3, [sp, #28]
-.L3917:
- ldr r3, [sp, #48]
- ldr r7, .L3959
- cmp r8, r3
- bcs .L3957
- add r3, r8, ip
- ubfx r3, r3, #2, #16
- cmp r3, #0
- beq .L3918
- add r2, r3, #1
- add r1, r5, r2, asl #1
- ldrh r7, [r1, #148]
- ldrb r1, [r5, #144] @ zero_extendqisi2
- cmp r1, #0
- beq .L3919
- ldr r1, [r5, #2264]
- ldr r0, .L3959+32
- cmp r1, r0
- moveq r7, r2
-.L3919:
- sub r7, r7, #-1073741823
- mov r7, r7, asl #2
- str r7, [sp, #64]
-.L3918:
- movw r2, #61424
- str r2, [sp, #68]
- add r2, r5, r3, asl #1
- ldrh r7, [r2, #148]
- ldrb r2, [r5, #144] @ zero_extendqisi2
- cmp r2, #0
- beq .L3920
- ldr r2, [r5, #2264]
- ldr r1, .L3959+32
- cmp r2, r1
- moveq r7, r3
-.L3920:
- ldr r3, [sp, #28]
- add r8, r8, #4
- str ip, [sp, #56]
- uxth r8, r8
- mla r2, r9, r7, r3
- ldr r3, .L3959
- ldrb r3, [r3, #2312] @ zero_extendqisi2
- str r2, [sp, #52]
- str r3, [sp, #32]
- ldr r3, .L3959+20
- ldrb r0, [r3, #1714] @ zero_extendqisi2
- bl FlashBchSel
- mov r0, #0
- bl flash_boot_enter_slc_mode
- ldr r3, .L3959
- ldr r3, [r3, #44]
- ldrb r1, [r3, #9] @ zero_extendqisi2
- ldr r2, [sp, #52]
- mov r0, r2
- bl __aeabi_uidiv
- add r3, sp, #64
- mov r1, r0
- ldr r2, [sp, #24]
- mov r0, #0
- bl FlashProgPage
- mov r0, #0
- bl flash_boot_exit_slc_mode
- ldr r0, [sp, #32]
- bl FlashBchSel
- mov r1, r9
- ldr r0, [sp, #28]
- bl __aeabi_uidiv
- add r2, r7, #1
- uxth r2, r2
- mov r1, r0
- mov r0, #0
- bl FlashPageProgMsbFFData
- ldr r3, [sp, #24]
- ldr ip, [sp, #56]
- add r3, r3, #2048
- str r3, [sp, #24]
- b .L3917
-.L3957:
- mov r1, r6
- mov r2, r10
- mov r3, #0
- ldr r0, .L3959+36
- bl printk
- ldr r6, [r4, #4]
- ldr r8, [r7, #4]
- mov r2, r10
- ldr r0, .L3959+40
- mov r9, #0
- ldr r3, [sp, #12]
- mul r6, r6, r3
- ldr r3, [r7, #44]
- ldrb r3, [r3, #9] @ zero_extendqisi2
- mov r1, r6
- str r3, [sp, #24]
- ldrh r3, [sp, #24]
- smulbb r8, r8, r3
- bl printk
- mov r0, r6
- uxth r8, r8
- mov r1, r8
- bl __aeabi_uidivmod
- rsb r3, r1, r6
- str r3, [sp, #48]
- ldr r3, [sp, #24]
+ sub r3, r6, r1
str r1, [sp, #28]
- mul ip, r3, r1
- ldr r3, [sp, #8]
- ubfx ip, ip, #2, #2
- str r3, [sp, #32]
-.L3922:
- cmp r9, r10
- bcs .L3958
- ldr r3, [sp, #28]
- rsb r8, ip, #4
- ldrb r1, [r5, #144] @ zero_extendqisi2
- add r3, r9, r3
- uxth r8, r8
- ubfx r3, r3, #2, #16
- cmp r1, #0
- add r2, r5, r3, asl #1
- ldrh r2, [r2, #148]
- beq .L3923
- ldr r1, [r5, #2264]
- ldr r0, .L3959+32
- cmp r1, r0
- moveq r2, r3
-.L3923:
- ldr r3, [sp, #48]
- add r9, r8, r9
- ldr r1, [sp, #24]
- add r3, ip, r3
- ldrb ip, [r7, #2312] @ zero_extendqisi2
- uxth r9, r9
- mla r3, r1, r2, r3
- ldr r2, [r7, #44]
- str ip, [sp, #52]
- ldrb r1, [r2, #9] @ zero_extendqisi2
- ldr r2, .L3959+20
- str r3, [sp, #60]
- str r1, [sp, #56]
- ldrb r0, [r2, #1714] @ zero_extendqisi2
- bl FlashBchSel
- mov r0, #0
- bl flash_boot_enter_slc_mode
- ldr r3, [sp, #60]
- ldr r1, [sp, #56]
- mov r0, r3
- bl __aeabi_uidiv
- mov r1, r0
- mov r0, #0
- mov r3, r0
- ldr r2, [sp, #32]
- bl FlashReadPage
- mov r0, #0
- bl flash_boot_exit_slc_mode
- ldr ip, [sp, #52]
- mov r0, ip
- bl FlashBchSel
- mov ip, #0
- ldr r3, [sp, #32]
- add r3, r3, r8, asl #9
- str r3, [sp, #32]
- b .L3922
-.L3958:
+ str r3, [sp, #36]
+ str r10, [sp, #24]
+.L3826:
+ ldr r3, [sp, #44]
+ cmp r3, r8
+ bhi .L3830
mov r1, r6
- mov r2, r10
mov r3, #0
- ldr r0, .L3959+44
+ mov r2, r9
+ ldr r0, .L3864+28
bl printk
- mov r6, #0
- mov r3, fp
+ ldr r3, [r4, #48]
+ mov r2, r9
+ ldr r6, [r5, #4]
+ mov r8, #0
+ ldr r7, [r4, #40]
+ ldrb r3, [r3, #9] @ zero_extendqisi2
+ ldr r0, .L3864+32
+ mul r6, r6, fp
+ str r3, [sp, #16]
+ ldrh r3, [sp, #16]
+ mov r1, r6
+ smulbb r7, r7, r3
+ bl printk
+ uxth r7, r7
+ mov r0, r6
+ mov r1, r7
+ bl __aeabi_uidivmod
+ sub r3, r6, r1
ldr r2, [sp, #8]
-.L3928:
- mov r8, r2
- mov r7, r3
- ldr r0, [r8]
+ str r3, [sp, #36]
+ ldr r3, [sp, #16]
+ str r1, [sp, #24]
+ str r2, [sp, #28]
+ mul r3, r3, r1
+ ubfx r3, r3, #2, #2
+.L3831:
+ cmp r8, r9
+ bcc .L3833
+ mov r3, #0
+ mov r2, r9
+ mov r1, r6
+ ldr r0, .L3864+36
+ bl printk
+ ldr r2, [sp, #8]
+ mov r3, r10
+ mov r6, #0
+.L3836:
+ mov r7, r2
+ mov r8, r3
+ ldr r0, [r7]
add r2, r2, #4
- ldr r1, [r7]
+ ldr r1, [r8]
add r3, r3, #4
cmp r0, r1
- beq .L3925
- mov r1, #0
+ beq .L3834
mov r2, #512
+ mov r1, #0
ldr r0, [sp, #8]
bl memset
ldr r3, [r8]
- ldr r0, .L3959+48
- str r3, [sp]
- ldr r3, [r7]
- bic r7, r6, #255
- ldr r1, [sp, #16]
- mov r7, r7, asl #2
+ ldr r1, [sp, #12]
+ ldr r0, .L3864+40
str r3, [sp, #4]
+ ldr r3, [r7]
+ str r3, [sp]
mov r3, r6
- ldr r2, [r4, #4]
+ bic r6, r6, #255
+ ldr r2, [r5, #4]
+ lsl r6, r6, #2
bl printk
- ldr r0, .L3959+52
- add r1, fp, r7
- mov r2, #4
mov r3, #256
+ mov r2, #4
+ add r1, r10, r6
+ ldr r0, .L3864+44
bl rknand_print_hex
- mov r2, #4
- ldr r0, .L3959+56
- ldr r3, [sp, #8]
- add r1, r3, r7
+ ldr r1, [sp, #8]
mov r3, #256
+ mov r2, #4
+ ldr r0, .L3864+48
+ add r1, r1, r6
bl rknand_print_hex
mov r0, #0
bl flash_boot_enter_slc_mode
- ldr r1, [r4, #4]
- mov r0, #0
- mov r2, r0
- ldr r3, [sp, #12]
- mul r1, r1, r3
+ ldr r1, [r5, #4]
+ mov r2, #0
+ mov r0, r2
+ mul r1, r1, fp
bl FlashEraseBlock
- ldr r3, [sp, #44]
- cmp r3, #0
- beq .L3926
- ldr r1, [r4, #4]
- mov r0, #0
- ldr r3, [sp, #12]
- mov r2, r0
- mla r1, r1, r3, r3
+ ldr r3, [sp, #32]
+ cmp r3, #1
+ bls .L3835
+ ldr r1, [r5, #4]
+ mov r2, #0
+ mov r0, r2
+ mla r1, r1, fp, fp
bl FlashEraseBlock
-.L3926:
+.L3835:
mov r0, #0
bl flash_boot_exit_slc_mode
- ldr r0, .L3959+60
- ldr r1, [r4, #4]
+ ldr r1, [r5, #4]
+ ldr r0, .L3864+52
bl printk
- ldr r3, [sp, #40]
- cmp r6, r3
- bcc .L3914
- b .L3927
-.L3925:
- ldr r1, [sp, #40]
- add r6, r6, #1
- cmp r6, r1
- bne .L3928
-.L3927:
- ldr r3, [sp, #20]
+.L3823:
+ ldr r3, [sp, #12]
+ add r5, r5, #4
add r3, r3, #1
- str r3, [sp, #20]
-.L3914:
- ldr r3, [sp, #16]
- add r4, r4, #4
- add r3, r3, #1
- str r3, [sp, #16]
cmp r3, #5
- bne .L3929
+ str r3, [sp, #12]
+ bne .L3838
ldr r0, [sp, #8]
bl ftl_free
ldr r3, [sp, #20]
clz r0, r3
- mov r0, r0, lsr #5
+ lsr r0, r0, #5
rsb r0, r0, #0
- b .L3907
-.L3933:
- mvn r0, #0
-.L3907:
- add sp, sp, #132
+.L3815:
+ add sp, sp, #124
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L3960:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3840:
+ mov r9, #8
+ b .L3817
+.L3818:
+ ldr r0, .L3864+56
+ bl printk
+ b .L3820
+.L3830:
+ ldr r3, [sp, #28]
+ add r2, r3, r8
+ lsrs r2, r2, #2
+ beq .L3827
+ ldrb r0, [r4, #152] @ zero_extendqisi2
+ add r1, r2, #1
+ add r3, r4, r1, lsl #1
+ cmp r0, #0
+ ldrh r3, [r3, #156]
+ beq .L3828
+ ldr r0, [r4, #2268]
+ ldr ip, .L3864+60
+ cmp r0, ip
+ moveq r3, r1
+.L3828:
+ sub r3, r3, #-1073741823
+ lsl r3, r3, #2
+ str r3, [sp, #56]
+.L3827:
+ movw r3, #61424
+ str r3, [sp, #60]
+ add r3, r4, r2, lsl #1
+ ldrh r7, [r3, #156]
+ ldrb r3, [r4, #152] @ zero_extendqisi2
+ cmp r3, #0
+ beq .L3829
+ ldr r3, [r4, #2268]
+ ldr r1, .L3864+60
+ cmp r3, r1
+ moveq r7, r2
+.L3829:
+ ldr r2, [sp, #36]
+ add r8, r8, #4
+ ldr r3, [sp, #16]
+ uxth r8, r8
+ mla r3, r7, r3, r2
+ ldr r2, .L3864+16
+ add r7, r7, #1
+ ldrb r0, [r2, #1722] @ zero_extendqisi2
+ uxth r7, r7
+ str r3, [sp, #52]
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
+ str r3, [sp, #48]
+ bl FlashBchSel
+ mov r0, #0
+ bl flash_boot_enter_slc_mode
+ ldr r2, [r4, #48]
+ ldr r3, [sp, #52]
+ ldrb r1, [r2, #9] @ zero_extendqisi2
+ mov r0, r3
+ bl __aeabi_uidiv
+ add r3, sp, #56
+ ldr r2, [sp, #24]
+ mov r1, r0
+ mov r0, #0
+ bl FlashProgPage
+ mov r0, #0
+ bl flash_boot_exit_slc_mode
+ ldr r0, [sp, #48]
+ bl FlashBchSel
+ ldr r1, [sp, #16]
+ ldr r0, [sp, #36]
+ bl __aeabi_uidiv
+ mov r2, r7
+ mov r1, r0
+ mov r0, #0
+ bl FlashPageProgMsbFFData
+ ldr r3, [sp, #24]
+ add r3, r3, #2048
+ str r3, [sp, #24]
+ b .L3826
+.L3833:
+ ldr r2, [sp, #24]
+ rsb r7, r3, #4
+ ldrb r0, [r4, #152] @ zero_extendqisi2
+ uxth r7, r7
+ add r2, r2, r8
+ lsr r2, r2, #2
+ cmp r0, #0
+ add r1, r4, r2, lsl #1
+ ldrh r1, [r1, #156]
+ beq .L3832
+ ldr r0, [r4, #2268]
+ ldr ip, .L3864+60
+ cmp r0, ip
+ moveq r1, r2
+.L3832:
+ ldr r2, [sp, #36]
+ add r8, r7, r8
+ uxth r8, r8
+ add r3, r3, r2
+ ldr r2, [sp, #16]
+ mla r3, r1, r2, r3
+ ldr r2, [r4, #48]
+ ldrb r1, [r2, #9] @ zero_extendqisi2
+ ldr r2, .L3864+16
+ str r3, [sp, #52]
+ ldrb r3, [r4, #2316] @ zero_extendqisi2
+ ldrb r0, [r2, #1722] @ zero_extendqisi2
+ str r1, [sp, #48]
+ str r3, [sp, #44]
+ bl FlashBchSel
+ mov r0, #0
+ bl flash_boot_enter_slc_mode
+ ldr r3, [sp, #52]
+ ldr r1, [sp, #48]
+ mov r0, r3
+ bl __aeabi_uidiv
+ mov r3, #0
+ mov r1, r0
+ ldr r2, [sp, #28]
+ mov r0, r3
+ bl FlashReadPage
+ mov r0, #0
+ bl flash_boot_exit_slc_mode
+ ldr r0, [sp, #44]
+ bl FlashBchSel
+ ldr r3, [sp, #28]
+ add r3, r3, r7, lsl #9
+ str r3, [sp, #28]
+ mov r3, #0
+ b .L3831
+.L3834:
+ ldr r1, [sp, #40]
+ add r6, r6, #1
+ cmp r1, r6
+ bne .L3836
+ ldr r3, [sp, #20]
+ add r3, r3, #1
+ str r3, [sp, #20]
+ b .L3823
+.L3842:
+ mvn r0, #0
+ b .L3815
+.L3865:
.align 2
-.L3959:
+.L3864:
.word .LANCHOR0
.word -52655045
- .word .LC173
.word .LC174
.word .LC175
.word .LANCHOR2
.word .LC176
.word .LC177
- .word 1446522928
.word .LC178
.word .LC179
.word .LC180
@@ -23870,92 +24399,90 @@
.word .LC182
.word .LC183
.word .LC184
+ .word .LC173
+ .word 1446522928
.fnend
.size write_idblock, .-write_idblock
.align 2
.global write_loader_lba
+ .syntax unified
+ .arm
+ .fpu softvfp
.type write_loader_lba, %function
write_loader_lba:
.fnstart
@ args = 0, pretend = 0, frame = 40
@ frame_needed = 0, uses_anonymous_args = 0
cmp r0, #64
- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
- .save {r4, r5, r6, r7, r8, r9, lr}
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mov r5, r0
- .pad #52
- sub sp, sp, #52
+ .pad #48
+ sub sp, sp, #48
mov r6, r1
mov r8, r2
- ldr r4, .L3984
- bne .L3962
+ ldr r4, .L3890
+ bne .L3867
ldr r2, [r2]
- ldr r3, .L3984+4
+ ldr r3, .L3890+4
cmp r2, r3
- bne .L3962
- mov r0, #256000
+ bne .L3867
mov r3, #1
+ mov r0, #256000
strb r3, [r4, #2020]
bl ftl_malloc
- mov r1, #0
mov r2, #256000
+ mov r1, #0
str r0, [r4, #2024]
bl ftl_memset
str r5, [r4, #2028]
-.L3962:
+.L3867:
str r6, [sp]
mov r3, r5
- ldr r0, .L3984+8
- ldr r1, [r4, #2024]
ldr r2, [r8]
+ ldr r1, [r4, #2024]
+ ldr r0, .L3890+8
bl printk
ldrb r3, [r4, #2020] @ zero_extendqisi2
- ldr r9, .L3984
cmp r3, #0
- beq .L3961
+ beq .L3866
sub r0, r5, #64
- ldr r7, [r9, #2024]
+ ldr r7, [r4, #2024]
cmp r0, #500
- bcs .L3964
+ bcs .L3869
rsb r2, r5, #564
- add r0, r7, r0, asl #9
- cmp r2, r6
mov r1, r8
- movcs r2, r6
- mov r2, r2, asl #9
+ cmp r6, r2
+ add r0, r7, r0, lsl #9
+ movcc r2, r6
+ lsl r2, r2, #9
bl ftl_memcpy
- b .L3965
-.L3964:
- cmp r5, #564
- bcs .L3973
-.L3965:
+.L3870:
ldr r3, [r4, #2028]
- cmp r3, r5
- beq .L3971
- ldr r2, .L3984
+ cmp r5, r3
+ beq .L3879
mov r3, #0
cmp r7, r3
+ strb r3, [r4, #2020]
mov r8, r3
- strb r3, [r2, #2020]
- beq .L3972
+ beq .L3880
mov r0, r7
bl ftl_free
-.L3972:
+.L3880:
str r8, [r4, #2024]
-.L3971:
- add r5, r5, r6
- str r5, [r4, #2028]
- b .L3961
-.L3973:
- ldr r3, .L3984+12
- ldr r0, [r9, #2028]
- ldr r3, [r3, #44]
+ b .L3879
+.L3869:
+ cmp r5, #564
+ bcc .L3870
+ ldr r3, .L3890+12
+ ldr r0, [r4, #2028]
+ ldr r3, [r3, #48]
sub r0, r0, #64
cmp r0, #500
ldrb r3, [r3, #9] @ zero_extendqisi2
movcs r0, #500
cmp r3, #4
- beq .L3974
+ beq .L3871
mov r3, #2
str r3, [sp, #8]
mov r3, #3
@@ -23966,49 +24493,52 @@
str r3, [sp, #20]
mov r3, #6
str r3, [sp, #24]
- b .L3967
-.L3974:
- mov r3, #0
-.L3966:
- cmp r0, #256
- add r1, sp, #8
- mov r2, r3, asl #1
- movls r2, r3
- str r2, [r1, r3, asl #2]
- add r3, r3, #1
- cmp r3, #5
- bne .L3966
-.L3967:
+.L3872:
movw r3, #63872
-.L3970:
- ldr r2, [r7, r3, asl #2]
+.L3878:
+ ldr r2, [r7, r3, lsl #2]
cmp r2, #0
- addne r3, r3, #128
- movne r0, r3, asl #2
- bne .L3969
-.L3968:
- sub r3, r3, #1
- cmp r3, #4096
- bne .L3970
- mov r0, r0, asl #9
-.L3969:
+ beq .L3876
+ add r3, r3, #128
+ lsl r0, r3, #2
+.L3877:
mov r1, r7
add r2, sp, #8
+ mov r7, #0
bl write_idblock
ldr r0, [r4, #2024]
- mov r7, #0
strb r7, [r4, #2020]
bl ftl_free
str r7, [r4, #2024]
- b .L3971
-.L3961:
- add sp, sp, #52
+.L3879:
+ add r5, r5, r6
+ str r5, [r4, #2028]
+.L3866:
+ add sp, sp, #48
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
-.L3985:
+ pop {r4, r5, r6, r7, r8, pc}
+.L3871:
+ mov r2, #0
+ add r3, sp, #8
+.L3875:
+ cmp r0, #256
+ lslhi r1, r2, #1
+ strls r2, [r3, r2, lsl #2]
+ strhi r1, [r3, r2, lsl #2]
+ add r2, r2, #1
+ cmp r2, #5
+ bne .L3875
+ b .L3872
+.L3876:
+ sub r3, r3, #1
+ cmp r3, #4096
+ bne .L3878
+ lsl r0, r0, #9
+ b .L3877
+.L3891:
.align 2
-.L3984:
- .word .LANCHOR4
+.L3890:
+ .word .LANCHOR2
.word -52655045
.word .LC185
.word .LANCHOR0
@@ -24016,281 +24546,381 @@
.size write_loader_lba, .-write_loader_lba
.align 2
.global FtlWrite
+ .syntax unified
+ .arm
+ .fpu softvfp
.type FtlWrite, %function
FtlWrite:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, lr}
+ push {r4, r5, r6, r7, r8, lr}
.save {r4, r5, r6, r7, r8, lr}
mov r6, r2
sub r2, r1, #64
mov r4, r1
cmp r2, #1984
- mov r5, r3
- mov r7, r0
+ mov r7, r3
movcs r2, #0
movcc r2, #1
cmp r0, #0
+ mov r5, r0
movne r2, #0
cmp r2, #0
- beq .L3987
- mov r0, r1
+ beq .L3893
mov r2, r3
mov r1, r6
+ mov r0, r4
bl write_loader_lba
-.L3987:
- mov r0, r7
- mov r1, r4
+.L3893:
+ mov r3, r7
mov r2, r6
- mov r3, r5
- ldmfd sp!, {r4, r5, r6, r7, r8, lr}
+ mov r1, r4
+ mov r0, r5
+ pop {r4, r5, r6, r7, r8, lr}
b ftl_write
.fnend
.size FtlWrite, .-FtlWrite
.align 2
.global rknand_sys_storage_ioctl
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rknand_sys_storage_ioctl, %function
rknand_sys_storage_ioctl:
.fnstart
@ args = 0, pretend = 0, frame = 520
@ frame_needed = 0, uses_anonymous_args = 0
- ldr r3, .L4049
- stmfd sp!, {r4, r5, r6, r7, lr}
+ ldr r3, .L3955
+ push {r4, r5, r6, r7, lr}
.save {r4, r5, r6, r7, lr}
- cmp r1, r3
+ mov r4, r1
.pad #524
sub sp, sp, #524
- mov r4, r1
mov r5, r2
- beq .L3994
- bhi .L3995
+ cmp r1, r3
+ beq .L3900
+ bhi .L3901
sub r3, r3, #2080
sub r3, r3, #6
cmp r1, r3
- beq .L3996
- bhi .L3997
+ beq .L3902
+ bhi .L3903
sub r3, r3, #238
cmp r1, r3
- beq .L3998
+ beq .L3904
add r3, r3, #237
cmp r1, r3
- beq .L3999
- b .L4029
-.L3997:
- ldr r3, .L4049+4
+ beq .L3905
+.L3935:
+ mvn r4, #21
+ b .L3898
+.L3903:
+ ldr r3, .L3955+4
cmp r1, r3
- beq .L4000
+ beq .L3906
add r3, r3, #1
cmp r1, r3
- beq .L4001
+ beq .L3907
sub r3, r3, #124
cmp r1, r3
- bne .L4029
- b .L4047
-.L3995:
- ldr r3, .L4049+8
- cmp r1, r3
- mov r6, r3
- beq .L4003
- bhi .L4004
- sub r3, r3, #2512
- sub r3, r3, #14
- cmp r1, r3
- beq .L3994
- add r3, r3, #10
- cmp r1, r3
- beq .L3994
- b .L4029
-.L4004:
- ldr r3, .L4049+12
- cmp r1, r3
- beq .L4003
- bcc .L4005
- add r3, r3, #1
- cmp r1, r3
- beq .L4005
- b .L4029
-.L3999:
- ldr r0, .L4049+16
+ bne .L3935
+ ldr r0, .L3955+8
bl printk
- mov r1, r5
mov r2, #520
+ mov r1, r5
mov r0, sp
bl rk_copy_from_user
cmp r0, #0
- beq .L4006
-.L4012:
- ldr r0, .L4049+20
- bl printk
- b .L4044
-.L4006:
+ bne .L3918
ldr r2, [sp]
- ldr r3, .L4049+24
+ ldr r3, .L3955+12
cmp r2, r3
- beq .L4007
-.L4009:
+ bne .L3915
+ ldr r2, [sp, #4]
+ cmp r2, #512
+ ldrls r1, .L3955+16
+ bhi .L3915
+.L3953:
+ add r0, sp, #8
+ bl memcpy
+ b .L3947
+.L3901:
+ ldr r3, .L3955+20
+ cmp r1, r3
+ mov r6, r3
+ beq .L3909
+ bhi .L3910
+ sub r3, r3, #2512
+ sub r3, r3, #14
+ cmp r1, r3
+ beq .L3900
+ add r3, r3, #10
+ cmp r1, r3
+ bne .L3935
+.L3900:
+ ldr r3, .L3955+24
+ cmp r4, r3
+ mov r7, r3
+ ldreq r0, .L3955+28
+ beq .L3949
+ ldr r3, .L3955+32
+ cmp r4, r3
+ ldreq r0, .L3955+36
+ ldrne r0, .L3955+40
+.L3949:
+ bl printk
+ mov r2, #520
+ mov r1, r5
+ mov r0, sp
+ bl rk_copy_from_user
+ cmp r0, #0
+ bne .L3918
+ ldr r2, [sp]
+ ldr r3, .L3955+44
+ cmp r2, r3
+ bne .L3952
+ ldr r3, .L3955+32
+ ldr r6, .L3955+48
+ cmp r4, r3
+ bne .L3928
+ ldr r3, [r6, #2032]
+ mov r2, #16
+ mov r1, sp
+ mov r0, r5
+ ldr r3, [r3, #20]
+ str r3, [sp, #4]
+ strb r3, [sp, #8]
+ bl rk_copy_to_user
+ cmp r0, #0
+ bne .L3952
+.L3919:
+ mov r4, #0
+.L3898:
+ mov r0, r4
+ add sp, sp, #524
+ @ sp needed
+ pop {r4, r5, r6, r7, pc}
+.L3910:
+ ldr r3, .L3955+52
+ cmp r1, r3
+ beq .L3909
+ bcc .L3911
+ add r3, r3, #1
+ cmp r1, r3
+ bne .L3935
+.L3911:
+ ldr r0, .L3955+56
+ bl printk
+ mov r2, #520
+ mov r1, r5
+ mov r0, sp
+ bl rk_copy_from_user
+ cmp r0, #0
+ bne .L3918
+ ldr r2, [sp]
+ ldr r3, .L3955+60
+ cmp r2, r3
+ bne .L3915
+ ldr r2, [sp, #4]
+ cmp r2, #504
+ bhi .L3915
+ ldr r3, .L3955+64
+ mov r1, sp
+ add r2, r2, #8
+ cmp r4, r3
+ ldr r4, .L3955+48
+ bne .L3934
+ ldr r0, [r4, #2564]
+ bl memcpy
+ ldr r1, [r4, #2564]
+ mov r0, #2
+ b .L3950
+.L3905:
+ ldr r0, .L3955+68
+ bl printk
+ mov r2, #520
+ mov r1, r5
+ mov r0, sp
+ bl rk_copy_from_user
+ cmp r0, #0
+ beq .L3912
+.L3918:
+ ldr r0, .L3955+72
+ bl printk
+.L3952:
+ mvn r4, #13
+ b .L3898
+.L3912:
+ ldr r2, [sp]
+ ldr r3, .L3955+76
+ cmp r2, r3
+ beq .L3913
+.L3915:
mvn r4, #0
- b .L4008
-.L4007:
+.L3914:
+ mov r1, r4
+ ldr r0, .L3955+80
+ bl printk
+ b .L3898
+.L3913:
ldr r3, [sp, #4]
cmp r3, #512
- bhi .L4009
- ldr r4, .L4049+28
+ bhi .L3915
+ ldr r4, .L3955+48
mov r2, #512
mov r0, sp
ldr r1, [r4, #2032]
bl memcpy
ldr r2, [r4, #2036]
- ldr r3, .L4049+32
+ ldr r3, .L3955+84
cmp r2, r3
- beq .L4010
+ beq .L3916
mov r1, #0
- add r0, sp, #64
mov r2, #128
+ add r0, sp, #64
str r1, [sp, #8]
str r1, [sp, #12]
bl memset
-.L4010:
- mov r1, #0
- add r0, sp, #256
+.L3916:
mov r2, #256
+ mov r1, #0
+ add r0, sp, r2
str r1, [sp, #16]
bl memset
-.L4039:
- mov r0, r5
- mov r1, sp
+.L3947:
mov r2, #520
+ mov r1, sp
+ mov r0, r5
bl rk_copy_to_user
cmp r0, #0
- bne .L4044
- b .L4043
-.L3996:
- ldr r0, .L4049+36
+ bne .L3952
+.L3951:
+ mov r4, #0
+ b .L3914
+.L3902:
+ ldr r0, .L3955+88
bl printk
- mov r1, r5
mov r2, #520
+ mov r1, r5
mov r0, sp
bl rk_copy_from_user
cmp r0, #0
- bne .L4012
+ bne .L3918
ldr r2, [sp]
- ldr r3, .L4049+24
+ ldr r3, .L3955+76
cmp r2, r3
- bne .L4009
+ bne .L3915
ldr r3, [sp, #4]
cmp r3, #512
- bhi .L4009
- ldr r2, .L4049+28
- ldr r3, .L4049+32
+ bhi .L3915
+ ldr r2, .L3955+48
+ ldr r3, .L3955+84
ldr r1, [r2, #2036]
cmp r1, r3
- mvnne r0, #1
- bne .L3993
+ mvnne r4, #1
+ bne .L3898
ldr r3, [sp, #12]
sub r1, r3, #1
cmp r1, #127
- mvnhi r0, #2
- bhi .L3993
+ mvnhi r4, #2
+ bhi .L3898
ldr r4, [r2, #2032]
add r1, sp, #64
- add r0, r4, #64
str r3, [r4, #12]
+ add r0, r4, #64
ldr r2, [sp, #12]
bl memcpy
- mov r0, #1
mov r1, r4
- b .L4042
-.L4001:
- ldr r0, .L4049+40
+ mov r0, #1
+.L3950:
+ bl StorageSysDataStore
+ mov r4, r0
+ b .L3914
+.L3907:
+ ldr r0, .L3955+92
bl printk
- mov r1, r5
mov r2, #520
+ mov r1, r5
mov r0, sp
bl rk_copy_from_user
cmp r0, #0
- bne .L4012
+ bne .L3918
ldr r2, [sp]
- ldr r3, .L4049+44
+ ldr r3, .L3955+96
cmp r2, r3
- bne .L4009
+ bne .L3915
ldr r3, [sp, #4]
cmp r3, #512
- bhi .L4009
- ldr r5, .L4049+28
+ bhi .L3915
+ ldr r5, .L3955+48
ldr r3, [r5, #2040]
cmp r3, #0
- bne .L4013
-.L4016:
- mov r0, #0
- b .L3993
-.L4013:
+ beq .L3919
ldr r3, [r5, #2044]
- ldr r2, .L4049+48
+ ldr r2, .L3955+100
ldr r1, [r3]
cmp r1, r2
- beq .L4014
+ beq .L3920
str r2, [r3]
mov r2, #504
- ldr r3, .L4049+28
- ldr r3, [r3, #2044]
+ ldr r3, [r5, #2044]
str r2, [r3, #4]
mov r2, #0
str r2, [r3, #8]
str r2, [r3, #12]
-.L4014:
+.L3920:
ldr r1, [r5, #2044]
mov r4, #0
mov r0, r4
str r4, [r1, #16]
bl StorageSysDataStore
ldr r3, [r5, #2032]
- ldr r2, .L4049+24
+ ldr r2, .L3955+76
ldr r1, [r3]
cmp r1, r2
strne r2, [r3]
- ldr r6, [r5, #2032]
- ldrne r3, .L4049+28
movne r2, #504
- add r0, r6, #64
- ldrne r3, [r3, #2032]
- stmneib r3, {r2, r4}
+ ldrne r3, [r5, #2032]
+ ldr r6, [r5, #2032]
+ stmibne r3, {r2, r4}
mov r4, #0
- mov r1, r4
mov r2, #128
+ mov r1, r4
str r4, [r6, #12]
+ add r0, r6, #64
bl memset
- mov r0, #1
mov r1, r6
+ mov r0, #1
bl StorageSysDataStore
str r4, [r5, #2040]
str r4, [r5, #2036]
- b .L4008
-.L4000:
- ldr r0, .L4049+52
+ b .L3914
+.L3906:
+ ldr r0, .L3955+104
bl printk
- mov r1, r5
mov r2, #520
+ mov r1, r5
mov r0, sp
bl rk_copy_from_user
cmp r0, #0
- bne .L4012
+ bne .L3918
ldr r2, [sp]
- ldr r3, .L4049+56
+ ldr r3, .L3955+108
cmp r2, r3
- bne .L4009
+ bne .L3915
ldr r3, [sp, #4]
cmp r3, #512
- bhi .L4009
- ldr r5, .L4049+28
+ bhi .L3915
+ ldr r5, .L3955+48
ldr r3, [r5, #2040]
cmp r3, #1
- beq .L4016
+ beq .L3919
ldr r2, [r5, #2044]
- ldr r3, .L4049+48
+ ldr r3, .L3955+100
ldr r1, [r2]
cmp r1, r3
- beq .L4017
+ beq .L3922
str r3, [r2]
mov r2, #504
ldr r3, [r5, #2044]
@@ -24298,7 +24928,7 @@
mov r2, #0
str r2, [r3, #8]
str r2, [r3, #12]
-.L4017:
+.L3922:
ldr r1, [r5, #2044]
mov r3, #1
mov r0, #0
@@ -24306,209 +24936,114 @@
str r3, [r1, #16]
bl StorageSysDataStore
ldr r3, [r5, #2032]
- ldr r2, .L4049+24
+ ldr r2, .L3955+76
ldr r1, [r3]
cmp r1, r2
strne r2, [r3]
- ldr r6, [r5, #2032]
- ldrne r3, .L4049+28
movne r1, #504
+ ldrne r3, [r5, #2032]
movne r2, #0
- add r0, r6, #64
- ldrne r3, [r3, #2032]
- stmneib r3, {r1, r2}
- mov r1, r4
+ ldr r6, [r5, #2032]
+ stmibne r3, {r1, r2}
mov r2, #128
+ mov r1, r4
str r4, [r6, #12]
+ add r0, r6, #64
bl memset
- mov r0, #1
mov r1, r6
+ mov r0, #1
bl StorageSysDataStore
mov r3, #1
str r3, [r5, #2040]
- b .L4008
-.L4047:
- ldr r0, .L4049+60
- bl printk
- mov r1, r5
- mov r2, #520
- mov r0, sp
- bl rk_copy_from_user
- cmp r0, #0
- bne .L4012
- ldr r2, [sp]
- ldr r3, .L4049+64
- cmp r2, r3
- bne .L4009
- ldr r2, [sp, #4]
- cmp r2, #512
- addls r0, sp, #8
- ldrls r1, .L4049+68
- bls .L4045
- b .L4009
-.L3994:
- ldr r0, .L4049+72
- cmp r4, r0
- mov r7, r0
- ldreq r0, .L4049+76
- beq .L4041
- ldr r3, .L4049+80
- cmp r4, r3
- ldreq r0, .L4049+84
- ldrne r0, .L4049+88
-.L4041:
- bl printk
- mov r1, r5
- mov r2, #520
- mov r0, sp
- bl rk_copy_from_user
- cmp r0, #0
- bne .L4012
- ldr r2, [sp]
- ldr r3, .L4049+92
- cmp r2, r3
- bne .L4044
- ldr r3, .L4049+80
- ldr r6, .L4049+28
- cmp r4, r3
- bne .L4023
- ldr r3, [r6, #2032]
- mov r0, r5
- mov r1, sp
- mov r2, #16
- ldr r3, [r3, #20]
- str r3, [sp, #4]
- strb r3, [sp, #8]
- bl rk_copy_to_user
- cmp r0, #0
- beq .L3993
- b .L4044
-.L4023:
+ b .L3914
+.L3928:
ldr r3, [r6, #2560]
cmp r3, #10
- bhi .L4044
- ldr r1, [r6, #2032]
- ldr r2, [sp, #4]
- ldr r3, [r1, #24]
- cmp r3, r2
+ bhi .L3952
+ ldr r2, [r6, #2032]
+ ldr r1, [sp, #4]
+ ldr r3, [r2, #24]
+ cmp r3, r1
cmpne r3, #0
movne r3, #1
moveq r3, #0
- beq .L4024
- ldr r0, .L4049+96
- mov r1, r2
+ beq .L3929
+ ldr r0, .L3955+112
bl printk
ldr r3, [r6, #2560]
add r3, r3, #1
str r3, [r6, #2560]
-.L4044:
- mvn r0, #13
- b .L3993
-.L4024:
+ b .L3952
+.L3929:
cmp r4, r7
str r3, [r6, #2560]
- mov r0, #1
- moveq r2, r3
movne r3, #1
- moveq r3, r2
- str r2, [r1, #24]
- str r3, [r1, #20]
+ strne r1, [r2, #24]
+ streq r3, [r2, #20]
+ mov r1, r2
+ streq r3, [r2, #24]
+ mov r0, #1
+ strne r3, [r2, #20]
bl StorageSysDataStore
cmn r0, #1
- bne .L4043
- b .L4048
-.L4003:
- ldr r0, .L4049+100
+ bne .L3951
+ mvn r4, #1
+ b .L3914
+.L3909:
+ ldr r0, .L3955+116
bl printk
- mov r1, r5
mov r2, #520
+ mov r1, r5
mov r0, sp
bl rk_copy_from_user
cmp r0, #0
- bne .L4012
+ bne .L3918
ldr r2, [sp]
- ldr r3, .L4049+104
+ ldr r3, .L3955+60
cmp r2, r3
- bne .L4009
+ bne .L3915
ldr r2, [sp, #4]
cmp r2, #504
- bhi .L4009
- ldr r3, .L4049+28
+ bhi .L3915
+ ldr r3, .L3955+48
cmp r4, r6
- add r0, sp, #8
ldreq r1, [r3, #2564]
ldrne r1, [r3, #2568]
add r1, r1, #8
-.L4045:
- bl memcpy
- b .L4039
-.L4005:
- ldr r0, .L4049+108
- bl printk
- mov r1, r5
- mov r2, #520
- mov r0, sp
- bl rk_copy_from_user
- cmp r0, #0
- bne .L4012
- ldr r2, [sp]
- ldr r3, .L4049+104
- cmp r2, r3
- bne .L4009
- ldr r2, [sp, #4]
- cmp r2, #504
- bhi .L4009
- ldr r3, .L4049+112
- add r2, r2, #8
- cmp r4, r3
- ldr r4, .L4049+28
- bne .L4028
- mov r1, sp
- ldr r0, [r4, #2564]
- bl memcpy
- mov r0, #2
- ldr r1, [r4, #2564]
- b .L4042
-.L4028:
- mov r1, sp
+ b .L3953
+.L3934:
ldr r0, [r4, #2568]
bl memcpy
ldr r1, [r4, #2568]
mov r0, #3
-.L4042:
- bl StorageSysDataStore
- mov r4, r0
- b .L4008
-.L3998:
+ b .L3950
+.L3904:
bl rknand_dev_flush
-.L4043:
- mov r4, #0
- b .L4008
-.L4048:
- mvn r4, #1
-.L4008:
- ldr r0, .L4049+116
- mov r1, r4
- bl printk
- mov r0, r4
- b .L3993
-.L4029:
- mvn r0, #21
-.L3993:
- add sp, sp, #524
- @ sp needed
- ldmfd sp!, {r4, r5, r6, r7, pc}
-.L4050:
+ b .L3951
+.L3956:
.align 2
-.L4049:
+.L3955:
.word 1074031656
.word 1074029694
+ .word .LC191
+ .word 1094995539
+ .word .LANCHOR2+2048
.word 1074034192
+ .word 1074031666
+ .word .LC192
+ .word 1074031676
+ .word .LC193
+ .word .LC194
+ .word 1280262987
+ .word .LANCHOR2
.word 1074034194
+ .word .LC197
+ .word 1145980246
+ .word 1074034193
.word .LC186
.word .LC187
.word 1263358532
- .word .LANCHOR4
+ .word .LC198
.word -1067903959
.word .LC188
.word .LC189
@@ -24516,46 +25051,36 @@
.word 1146313043
.word .LC190
.word 1112755781
- .word .LC191
- .word 1094995539
- .word .LANCHOR4+2048
- .word 1074031666
- .word .LC192
- .word 1074031676
- .word .LC193
- .word .LC194
- .word 1280262987
.word .LC195
.word .LC196
- .word 1145980246
- .word .LC197
- .word 1074034193
- .word .LC198
.fnend
.size rknand_sys_storage_ioctl, .-rknand_sys_storage_ioctl
.align 2
.global rk_ftl_storage_sys_init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_storage_sys_init, %function
rk_ftl_storage_sys_init:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, r6, r7, lr}
- .save {r3, r4, r5, r6, r7, lr}
- mov r2, #512
- ldr r4, .L4061
+ push {r4, r5, r6, r7, r8, lr}
+ .save {r4, r5, r6, r7, r8, lr}
mvn r3, #0
+ ldr r4, .L3967
mov r5, #0
- add r0, r4, #2048
+ mov r2, #512
ldr r1, [r4, #2004]
+ add r0, r4, #2048
str r3, [r4, #2028]
+ strb r5, [r4, #2020]
add r3, r1, #512
- str r3, [r4, #2032]
str r1, [r4, #2044]
+ str r3, [r4, #2032]
add r3, r1, #1024
add r1, r1, #1536
str r3, [r4, #2564]
- strb r5, [r4, #2020]
str r5, [r4, #2024]
str r5, [r4, #2572]
str r1, [r4, #2568]
@@ -24567,40 +25092,42 @@
ldr r3, [r6, #16]
cmp r7, r5
str r3, [r4, #2040]
- beq .L4052
- mov r0, r6
+ beq .L3958
mov r1, #508
+ mov r0, r6
bl js_hash
cmp r7, r0
- beq .L4052
+ beq .L3958
str r5, [r6, #16]
- ldr r0, .L4061+4
+ ldr r0, .L3967+4
str r5, [r4, #2040]
bl printk
-.L4052:
+.L3958:
ldr r3, [r4, #2040]
mov r0, #2
ldr r1, [r4, #2564]
cmp r3, #0
- ldrne r3, .L4061
- ldrne r2, .L4061+8
- strne r2, [r3, #2036]
+ ldrne r3, .L3967+8
+ strne r3, [r4, #2036]
bl StorageSysDataLoad
ldr r1, [r4, #2568]
mov r0, #3
bl StorageSysDataLoad
- ldmfd sp!, {r3, r4, r5, r6, r7, lr}
+ pop {r4, r5, r6, r7, r8, lr}
b rknand_sys_storage_init
-.L4062:
+.L3968:
.align 2
-.L4061:
- .word .LANCHOR4
+.L3967:
+ .word .LANCHOR2
.word .LC199
.word -1067903959
.fnend
.size rk_ftl_storage_sys_init, .-rk_ftl_storage_sys_init
.align 2
.global StorageSysDataDeInit
+ .syntax unified
+ .arm
+ .fpu softvfp
.type StorageSysDataDeInit, %function
StorageSysDataDeInit:
.fnstart
@@ -24613,269 +25140,269 @@
.size StorageSysDataDeInit, .-StorageSysDataDeInit
.align 2
.global rk_ftl_vendor_storage_init
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_vendor_storage_init, %function
rk_ftl_vendor_storage_init:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
+ push {r4, r5, r6, r7, r8, r9, r10, lr}
.save {r4, r5, r6, r7, r8, r9, r10, lr}
mov r0, #65536
+ ldr r6, .L3980
bl ftl_malloc
- ldr r6, .L4075
cmp r0, #0
str r0, [r6, #2576]
- beq .L4070
- ldr r9, .L4075+4
- mov r8, #0
- mov r4, r8
- mov r7, r8
- mov r10, r6
-.L4068:
- mov r0, r7, asl #7
- mov r1, #128
+ beq .L3976
+ ldr r10, .L3980+4
+ mov r7, #0
+ ldr r9, .L3980+8
+ mov r4, r7
+ mov r8, r7
+.L3974:
ldr r2, [r6, #2576]
+ mov r1, #128
+ lsl r0, r8, #7
bl FlashBootVendorRead
cmp r0, #0
- bne .L4066
- ldr r3, [r10, #2576]
- ldr r0, .L4075+8
- add r2, r3, #61440
- ldr r1, [r3]
+ bne .L3972
+ ldr r1, [r6, #2576]
+ mov r0, r10
+ add r2, r1, #61440
+ ldr r3, [r1, #4]
ldr r2, [r2, #4092]
- ldr r3, [r3, #4]
+ ldr r1, [r1]
bl printk
- ldr r5, [r10, #2576]
+ ldr r5, [r6, #2576]
ldr r3, [r5]
cmp r3, r9
- bne .L4067
+ bne .L3973
add r2, r5, #61440
ldr r3, [r5, #4]
- ldr r1, [r2, #4092]
- cmp r4, r3
- movcs r2, #0
- movcc r2, #1
- cmp r1, r3
- movne r2, #0
+ ldr r2, [r2, #4092]
+ cmp r3, r4
+ sub r2, r2, r3
+ clz r2, r2
+ lsr r2, r2, #5
+ movls r2, #0
cmp r2, #0
- movne r8, r7
+ movne r7, r8
movne r4, r3
-.L4067:
- cmp r7, #1
- movne r7, #1
- bne .L4068
-.L4074:
+.L3973:
+ add r8, r8, #1
+ cmp r8, #2
+ bne .L3974
cmp r4, #0
- beq .L4069
- mov r0, r8, asl #7
- mov r1, #128
+ beq .L3975
mov r2, r5
+ mov r1, #128
+ lsl r0, r7, #7
bl FlashBootVendorRead
cmp r0, #0
- bne .L4066
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L4069:
- mov r0, r5
- mov r1, r4
+ bne .L3972
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3975:
mov r2, #65536
+ mov r1, r4
+ mov r0, r5
bl memset
- ldr r3, .L4075+4
- str r7, [r5, #4]
+ mov r3, #1
+ add r2, r5, #61440
+ str r3, [r5, #4]
mov r0, r4
- str r3, [r5]
- add r3, r5, #61440
- str r7, [r3, #4092]
- ldr r3, .L4075+12
+ str r9, [r5]
+ str r3, [r2, #4092]
+ ldr r3, .L3980+12
strh r4, [r5, #12] @ movhi
strh r3, [r5, #14] @ movhi
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L4066:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3972:
ldr r0, [r6, #2576]
bl kfree
mov r3, #0
mvn r0, #0
str r3, [r6, #2576]
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L4070:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3976:
mvn r0, #11
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
-.L4076:
+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
+.L3981:
.align 2
-.L4075:
- .word .LANCHOR4
- .word 1380668996
+.L3980:
+ .word .LANCHOR2
.word .LC200
+ .word 1380668996
.word -1032
.fnend
.size rk_ftl_vendor_storage_init, .-rk_ftl_vendor_storage_init
.align 2
.global rk_ftl_vendor_read
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_vendor_read, %function
rk_ftl_vendor_read:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r3, r4, r5, lr}
- .save {r3, r4, r5, lr}
- ldr r3, .L4084
+ ldr r3, .L3992
ldr ip, [r3, #2576]
cmp ip, #0
- ldrneh r4, [ip, #10]
- movne r3, #0
- beq .L4082
-.L4079:
+ beq .L3987
+ push {r4, r5, r6, lr}
+ .save {r4, r5, r6, lr}
+ mov r3, #0
+ ldrh r4, [ip, #10]
+.L3984:
cmp r3, r4
- bcs .L4082
- add lr, ip, r3, asl #3
+ bcc .L3986
+ mvn r0, #0
+ pop {r4, r5, r6, pc}
+.L3986:
+ add lr, ip, r3, lsl #3
ldrh r5, [lr, #16]
cmp r5, r0
- bne .L4080
- ldrh r3, [lr, #20]
+ bne .L3985
+ ldrh r4, [lr, #20]
mov r0, r1
ldrh r1, [lr, #18]
- mov r4, r2
- cmp r2, r3
+ cmp r4, r2
+ movcs r4, r2
add r1, r1, #1024
- movcs r4, r3
- add r1, ip, r1
mov r2, r4
+ add r1, ip, r1
bl memcpy
mov r0, r4
- ldmfd sp!, {r3, r4, r5, pc}
-.L4080:
+ pop {r4, r5, r6, pc}
+.L3985:
add r3, r3, #1
- b .L4079
-.L4082:
+ b .L3984
+.L3987:
mvn r0, #0
- ldmfd sp!, {r3, r4, r5, pc}
-.L4085:
+ bx lr
+.L3993:
.align 2
-.L4084:
- .word .LANCHOR4
+.L3992:
+ .word .LANCHOR2
.fnend
.size rk_ftl_vendor_read, .-rk_ftl_vendor_read
.align 2
.global rk_ftl_vendor_write
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_vendor_write, %function
rk_ftl_vendor_write:
.fnstart
@ args = 0, pretend = 0, frame = 24
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ ldr r3, .L4015
+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
- mov r9, r2
- ldr r2, .L4109
.pad #28
sub sp, sp, #28
- ldr r4, [r2, #2576]
+ ldr r4, [r3, #2576]
cmp r4, #0
- beq .L4101
- mov r3, r1
- add r7, r9, #63
- ldrh r1, [r4, #8]
- bic r7, r7, #63
+ beq .L4009
+ mov r8, r2
ldrh r2, [r4, #10]
- mov ip, r0
- mov r6, #0
- str r1, [sp, #4]
-.L4088:
- cmp r6, r2
- bcs .L4107
- add r5, r4, r6, asl #3
- ldrh r1, [r5, #16]
- cmp r1, ip
- bne .L4089
- ldrh r1, [r5, #20]
- add fp, r4, #1024
- add r1, r1, #63
- bic r1, r1, #63
- str r1, [sp, #8]
- cmp r9, r1
- bls .L4090
+ add r6, r8, #63
+ ldrh r3, [r4, #8]
+ mov fp, r1
+ bic r6, r6, #63
+ mov r7, #0
+ str r3, [sp, #4]
+.L3996:
+ cmp r7, r2
+ bcc .L4004
ldrh r1, [r4, #14]
- cmp r1, r7
- subcs r2, r2, #1
- strcs r2, [sp, #12]
- ldrcsh r8, [r5, #18]
- bcc .L4101
-.L4091:
- ldr r2, [sp, #12]
- add r5, r5, #8
- cmp r6, r2
- bcs .L4108
- ldrh r10, [r5, #20]
- add r0, fp, r8
- ldrh r2, [r5, #16]
- add r6, r6, #1
- ldrh r1, [r5, #18]
- strh r10, [r5, #12] @ movhi
- add r10, r10, #63
- bic r10, r10, #63
- strh r2, [r5, #8] @ movhi
- strh r8, [r5, #10] @ movhi
- add r1, fp, r1
- mov r2, r10
- str r3, [sp, #20]
- str ip, [sp, #16]
- bl memcpy
- add r8, r8, r10
- ldr r3, [sp, #20]
- ldr ip, [sp, #16]
- b .L4091
-.L4108:
- add r6, r4, r6, asl #3
- uxth r8, r8
- add r0, fp, r8
- mov r1, r3
- strh r8, [r6, #18] @ movhi
- mov r2, r9
- strh ip, [r6, #16] @ movhi
- uxth r7, r7
- strh r9, [r6, #20] @ movhi
- add r8, r8, r7
- bl memcpy
- ldrh r5, [r4, #14]
- strh r8, [r4, #12] @ movhi
- ldr r3, [sp, #8]
- add r5, r3, r5
- rsb r7, r7, r5
- strh r7, [r4, #14] @ movhi
- b .L4106
-.L4090:
- ldrh r0, [r5, #18]
- mov r1, r3
- mov r2, r9
- add r0, fp, r0
- bl memcpy
- strh r9, [r5, #20] @ movhi
- b .L4106
-.L4089:
- add r6, r6, #1
- b .L4088
-.L4107:
- ldrh r1, [r4, #14]
- cmp r1, r7
- bcc .L4101
- add r2, r4, r2, asl #3
- uxth r7, r7
- rsb r1, r7, r1
- strh ip, [r2, #16] @ movhi
- ldrh r0, [r4, #12]
- strh r9, [r2, #20] @ movhi
- strh r0, [r2, #18] @ movhi
- add r0, r7, r0
- strh r1, [r4, #14] @ movhi
- mov r1, r3
- strh r0, [r4, #12] @ movhi
- ldrh r0, [r2, #18]
- mov r2, r9
+ cmp r6, r1
+ bhi .L4009
+ add r3, r4, r2, lsl #3
+ uxth r6, r6
+ strh r0, [r3, #16] @ movhi
+ ldrh r2, [r4, #12]
+ strh r8, [r3, #20] @ movhi
+ strh r2, [r3, #18] @ movhi
+ add r2, r2, r6
+ sub r6, r1, r6
+ strh r2, [r4, #12] @ movhi
+ strh r6, [r4, #14] @ movhi
+ mov r2, r8
+ ldrh r0, [r3, #18]
+ mov r1, fp
add r0, r0, #1024
add r0, r4, r0
bl memcpy
ldrh r3, [r4, #10]
add r3, r3, #1
strh r3, [r4, #10] @ movhi
-.L4106:
+ b .L4014
+.L4004:
+ add r5, r4, r7, lsl #3
+ ldrh r3, [r5, #16]
+ cmp r3, r0
+ str r3, [sp, #8]
+ bne .L3997
+ ldrh r1, [r5, #20]
+ add r3, r4, #1024
+ add r1, r1, #63
+ bic r1, r1, #63
+ cmp r8, r1
+ str r1, [sp, #12]
+ bls .L3998
+ ldrh r1, [r4, #14]
+ cmp r6, r1
+ subls r2, r2, #1
+ ldrhls r10, [r5, #18]
+ strls r2, [sp, #16]
+ bls .L3999
+.L4009:
+ mvn r0, #0
+ b .L3994
+.L4000:
+ ldrh r9, [r5, #20]
+ add r0, r3, r10
+ ldrh r2, [r5, #16]
+ add r7, r7, #1
+ ldrh r1, [r5, #18]
+ strh r9, [r5, #12] @ movhi
+ add r9, r9, #63
+ bic r9, r9, #63
+ strh r2, [r5, #8] @ movhi
+ strh r10, [r5, #10] @ movhi
+ add r1, r3, r1
+ mov r2, r9
+ str r3, [sp, #20]
+ bl memcpy
+ ldr r3, [sp, #20]
+ add r10, r10, r9
+.L3999:
+ ldr r2, [sp, #16]
+ add r5, r5, #8
+ cmp r7, r2
+ bcc .L4000
+ ldrh r2, [sp, #8]
+ add r7, r4, r7, lsl #3
+ uxth r5, r10
+ uxtah r0, r3, r10
+ strh r8, [r7, #20] @ movhi
+ strh r2, [r7, #16] @ movhi
+ mov r1, fp
+ strh r5, [r7, #18] @ movhi
+ mov r2, r8
+ bl memcpy
+ uxth r3, r6
+ ldrh r6, [r4, #14]
+ add r5, r5, r3
+ sub r6, r6, r3
+ ldr r3, [sp, #12]
+ strh r5, [r4, #12] @ movhi
+ add r6, r6, r3
+ strh r6, [r4, #14] @ movhi
+.L4014:
ldr r3, [r4, #4]
add r2, r4, #61440
mov r1, #128
@@ -24890,30 +25417,41 @@
movhi r3, #0
strh r3, [r4, #8] @ movhi
ldr r3, [sp, #4]
- mov r0, r3, asl #7
+ lsl r0, r3, #7
bl FlashBootVendorWrite
mov r0, #0
- b .L4087
-.L4101:
- mvn r0, #0
-.L4087:
+.L3994:
add sp, sp, #28
@ sp needed
- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
-.L4110:
+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
+.L3998:
+ ldrh r0, [r5, #18]
+ mov r2, r8
+ mov r1, fp
+ add r0, r3, r0
+ bl memcpy
+ strh r8, [r5, #20] @ movhi
+ b .L4014
+.L3997:
+ add r7, r7, #1
+ b .L3996
+.L4016:
.align 2
-.L4109:
- .word .LANCHOR4
+.L4015:
+ .word .LANCHOR2
.fnend
.size rk_ftl_vendor_write, .-rk_ftl_vendor_write
.align 2
.global rk_ftl_vendor_storage_ioctl
+ .syntax unified
+ .arm
+ .fpu softvfp
.type rk_ftl_vendor_storage_ioctl, %function
rk_ftl_vendor_storage_ioctl:
.fnstart
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
- stmfd sp!, {r4, r5, r6, lr}
+ push {r4, r5, r6, lr}
.save {r4, r5, r6, lr}
mov r0, #4096
mov r5, r2
@@ -24921,81 +25459,79 @@
bl ftl_malloc
subs r4, r0, #0
mvneq r5, #0
- beq .L4112
- ldr r3, .L4128
+ beq .L4017
+ ldr r3, .L4033
cmp r6, r3
- beq .L4114
+ beq .L4020
add r3, r3, #1
cmp r6, r3
- beq .L4115
- b .L4126
-.L4114:
- mov r1, r5
+ beq .L4021
+.L4031:
+ mvn r5, #13
+ b .L4019
+.L4020:
mov r2, #8
+ mov r1, r5
bl rk_copy_from_user
cmp r0, #0
- bne .L4126
+ bne .L4031
ldr r2, [r4]
- ldr r3, .L4128+4
+ ldr r3, .L4033+4
cmp r2, r3
- beq .L4117
-.L4118:
+ beq .L4023
+.L4024:
mvn r5, #0
- b .L4113
-.L4117:
- ldrh r0, [r4, #4]
- add r1, r4, #8
+.L4019:
+ mov r0, r4
+ bl kfree
+.L4017:
+ mov r0, r5
+ pop {r4, r5, r6, pc}
+.L4023:
ldrh r2, [r4, #6]
+ add r1, r4, #8
+ ldrh r0, [r4, #4]
bl rk_ftl_vendor_read
cmn r0, #1
- beq .L4118
+ beq .L4024
uxth r2, r0
strh r0, [r4, #6] @ movhi
mov r1, r4
mov r0, r5
add r2, r2, #8
bl rk_copy_to_user
- cmp r0, #0
- moveq r5, #0
- mvnne r5, #13
- b .L4113
-.L4115:
- mov r1, r5
+ subs r5, r0, #0
+ beq .L4019
+ b .L4031
+.L4021:
mov r2, #8
+ mov r1, r5
bl rk_copy_from_user
cmp r0, #0
- bne .L4126
+ bne .L4031
ldr r2, [r4]
- ldr r3, .L4128+4
+ ldr r3, .L4033+4
cmp r2, r3
- bne .L4118
+ bne .L4024
ldrh r2, [r4, #6]
movw r3, #4087
cmp r2, r3
- bhi .L4118
- mov r0, r4
- mov r1, r5
+ bhi .L4024
add r2, r2, #8
+ mov r1, r5
+ mov r0, r4
bl rk_copy_from_user
cmp r0, #0
- bne .L4126
- ldrh r0, [r4, #4]
- add r1, r4, #8
+ bne .L4031
ldrh r2, [r4, #6]
+ add r1, r4, #8
+ ldrh r0, [r4, #4]
bl rk_ftl_vendor_write
mov r5, r0
- b .L4113
-.L4126:
- mvn r5, #13
-.L4113:
- mov r0, r4
- bl kfree
-.L4112:
- mov r0, r5
- ldmfd sp!, {r4, r5, r6, pc}
-.L4129:
+ b .L4019
+.L4034:
.align 2
-.L4128:
+.L4033:
.word 1074034177
.word 1448232273
.fnend
@@ -25009,6 +25545,8 @@
.global gSnSectorData
.global gpDrmKeyInfo
.global gpBootConfig
+ .global ftl_dma32_buffer_size
+ .global ftl_dma32_buffer
.global gLoaderBootInfo
.global RK29_NANDC1_REG_BASE
.global RK29_NANDC_REG_BASE
@@ -25244,18 +25782,11 @@
.global IDByte
.global read_retry_cur_offset
.section .rodata
- .align 2
-.LANCHOR3 = . + 0
- .type __func__.20390, %object
- .size __func__.20390, 11
-__func__.20390:
+ .set .LANCHOR3,. + 0
+ .type __func__.23812, %object
+ .size __func__.23812, 11
+__func__.23812:
.ascii "FtlMemInit\000"
-.LC0:
- .byte 60
- .byte 40
- .byte 24
- .byte 16
- .space 1
.type samsung_14nm_slc_rr, %object
.size samsung_14nm_slc_rr, 26
samsung_14nm_slc_rr:
@@ -25285,7 +25816,6 @@
.byte -125
.byte -115
.byte 100
- .space 2
.type samsung_14nm_mlc_rr, %object
.size samsung_14nm_mlc_rr, 104
samsung_14nm_mlc_rr:
@@ -25393,452 +25923,33 @@
.byte 18
.byte 9
.byte 8
- .type __func__.21169, %object
- .size __func__.21169, 17
-__func__.21169:
+ .type __func__.24591, %object
+ .size __func__.24591, 17
+__func__.24591:
.ascii "FtlDumpBlockInfo\000"
- .space 3
- .type __func__.21188, %object
- .size __func__.21188, 16
-__func__.21188:
+ .type __func__.24610, %object
+ .size __func__.24610, 16
+__func__.24610:
.ascii "FtlScanAllBlock\000"
- .type __func__.21456, %object
- .size __func__.21456, 17
-__func__.21456:
+ .type __func__.24878, %object
+ .size __func__.24878, 17
+__func__.24878:
.ascii "ftl_scan_all_ppa\000"
- .space 3
- .type __func__.21137, %object
- .size __func__.21137, 12
-__func__.21137:
+ .type __func__.24559, %object
+ .size __func__.24559, 12
+__func__.24559:
.ascii "FtlCheckVpc\000"
- .type __func__.21436, %object
- .size __func__.21436, 21
-__func__.21436:
+ .type __func__.24858, %object
+ .size __func__.24858, 21
+__func__.24858:
.ascii "FtlVpcCheckAndModify\000"
- .space 3
- .type __func__.20463, %object
- .size __func__.20463, 8
-__func__.20463:
+ .type __func__.23885, %object
+ .size __func__.23885, 8
+__func__.23885:
.ascii "FtlInit\000"
- .section .rodata.str1.1,"aMS",%progbits,1
-.LC1:
- .ascii "FlashEraseBlocks pageAddr error %x\012\000"
-.LC2:
- .ascii "phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
- .ascii "\000"
-.LC3:
- .ascii "FtlFreeSysBlkQueueOut free count = %d\012\000"
-.LC4:
- .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
- .ascii "\000"
-.LC5:
- .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
-.LC6:
- .ascii "FLASH INFO:\012\000"
-.LC7:
- .ascii "FLASH ID: %x\012\000"
-.LC8:
- .ascii "Device Capacity: %d MB\012\000"
-.LC9:
- .ascii "FMWAIT: %x %x %x %x\012\000"
-.LC10:
- .ascii "FTL INFO:\012\000"
-.LC11:
- .ascii "g_MaxLpn = 0x%x\012\000"
-.LC12:
- .ascii "g_VaildLpn = 0x%x\012\000"
-.LC13:
- .ascii "read_page_count = 0x%x\012\000"
-.LC14:
- .ascii "discard_page_count = 0x%x\012\000"
-.LC15:
- .ascii "write_page_count = 0x%x\012\000"
-.LC16:
- .ascii "cache_write_count = 0x%x\012\000"
-.LC17:
- .ascii "l2p_write_count = 0x%x\012\000"
-.LC18:
- .ascii "gc_page_count = 0x%x\012\000"
-.LC19:
- .ascii "totle_write = %d MB\012\000"
-.LC20:
- .ascii "totle_read = %d MB\012\000"
-.LC21:
- .ascii "GSV = 0x%x\012\000"
-.LC22:
- .ascii "GDV = 0x%x\012\000"
-.LC23:
- .ascii "bad blk num = %d %d\012\000"
-.LC24:
- .ascii "free_superblocks = 0x%x\012\000"
-.LC25:
- .ascii "mlc_EC = 0x%x\012\000"
-.LC26:
- .ascii "slc_EC = 0x%x\012\000"
-.LC27:
- .ascii "avg_EC = 0x%x\012\000"
-.LC28:
- .ascii "sys_EC = 0x%x\012\000"
-.LC29:
- .ascii "max_EC = 0x%x\012\000"
-.LC30:
- .ascii "min_EC = 0x%x\012\000"
-.LC31:
- .ascii "PLT = 0x%x\012\000"
-.LC32:
- .ascii "POT = 0x%x\012\000"
-.LC33:
- .ascii "MaxSector = 0x%x\012\000"
-.LC34:
- .ascii "init_sys_blks_pp = 0x%x\012\000"
-.LC35:
- .ascii "sys_blks_pp = 0x%x\012\000"
-.LC36:
- .ascii "free sysblock = 0x%x\012\000"
-.LC37:
- .ascii "data_blks_pp = 0x%x\012\000"
-.LC38:
- .ascii "data_op_blks_pp = 0x%x\012\000"
-.LC39:
- .ascii "max_data_blks = 0x%x\012\000"
-.LC40:
- .ascii "Sys.id = 0x%x\012\000"
-.LC41:
- .ascii "Bbt.id = 0x%x\012\000"
-.LC42:
- .ascii "ACT.page = 0x%x\012\000"
-.LC43:
- .ascii "ACT.plane = 0x%x\012\000"
-.LC44:
- .ascii "ACT.id = 0x%x\012\000"
-.LC45:
- .ascii "ACT.mode = 0x%x\012\000"
-.LC46:
- .ascii "ACT.a_pages = 0x%x\012\000"
-.LC47:
- .ascii "ACT VPC = 0x%x\012\000"
-.LC48:
- .ascii "BUF.page = 0x%x\012\000"
-.LC49:
- .ascii "BUF.plane = 0x%x\012\000"
-.LC50:
- .ascii "BUF.id = 0x%x\012\000"
-.LC51:
- .ascii "BUF.mode = 0x%x\012\000"
-.LC52:
- .ascii "BUF.a_pages = 0x%x\012\000"
-.LC53:
- .ascii "BUF VPC = 0x%x\012\000"
-.LC54:
- .ascii "TMP.page = 0x%x\012\000"
-.LC55:
- .ascii "TMP.plane = 0x%x\012\000"
-.LC56:
- .ascii "TMP.id = 0x%x\012\000"
-.LC57:
- .ascii "TMP.mode = 0x%x\012\000"
-.LC58:
- .ascii "TMP.a_pages = 0x%x\012\000"
-.LC59:
- .ascii "GC.page = 0x%x\012\000"
-.LC60:
- .ascii "GC.plane = 0x%x\012\000"
-.LC61:
- .ascii "GC.id = 0x%x\012\000"
-.LC62:
- .ascii "GC.mode = 0x%x\012\000"
-.LC63:
- .ascii "GC.a_pages = 0x%x\012\000"
-.LC64:
- .ascii "WR_CHK = 0x%x %x %x %x\012\000"
-.LC65:
- .ascii "Read Err = 0x%x\012\000"
-.LC66:
- .ascii "Prog Err = 0x%x\012\000"
-.LC67:
- .ascii "gc_free_blk_th= 0x%x\012\000"
-.LC68:
- .ascii "gc_merge_free_blk_th= 0x%x\012\000"
-.LC69:
- .ascii "gc_skip_write_count= 0x%x\012\000"
-.LC70:
- .ascii "gc_blk_index= 0x%x\012\000"
-.LC71:
- .ascii "free min EC= 0x%x\012\000"
-.LC72:
- .ascii "free max EC= 0x%x\012\000"
-.LC73:
- .ascii "GC__SB VPC = 0x%x\012\000"
-.LC74:
- .ascii "%d. [0x%x]=0x%x 0x%x 0x%x\012\000"
-.LC75:
- .ascii "free %d. [0x%x] 0x%x 0x%x\012\000"
-.LC76:
- .ascii "%s\012\000"
-.LC77:
- .ascii "FTL version: 5.0.63 20200923\000"
-.LC78:
- .ascii "swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
- .ascii "\012\000"
-.LC79:
- .ascii "FtlGcRefreshBlock 0x%x\012\000"
-.LC80:
- .ascii "FtlGcMarkBadPhyBlk %d 0x%x\012\000"
-.LC81:
- .ascii "%s error allocating memory. return -1\012\000"
-.LC82:
- .ascii "%s %p:0x%x:\000"
-.LC83:
- .ascii "%x \000"
-.LC84:
- .ascii "\000"
-.LC85:
- .ascii "otp error! %d\000"
-.LC86:
- .ascii "rr\000"
-.LC87:
- .ascii "%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
- .ascii "\000"
-.LC88:
- .ascii "nandc:\000"
-.LC89:
- .ascii "%d flReg.d32=%x %x\012\000"
-.LC90:
- .ascii "sdr read ok %x ecc=%d\012\000"
-.LC91:
- .ascii "sync para %d\012\000"
-.LC92:
- .ascii "TOG mode Read error %x %x\012\000"
-.LC93:
- .ascii "read retry status %x %x %x\012\000"
-.LC94:
- .ascii "micron RR %d row=%x,count %d,status=%d\012\000"
-.LC95:
- .ascii "samsung RR %d row=%x,count %d,status=%d\012\000"
-.LC96:
- .ascii "ECC:%d\012\000"
-.LC97:
- .ascii "No.%d FLASH ID:%x %x %x %x %x %x\012\000"
-.LC98:
- .ascii "FlashLoadPhyInfo fail %x!!\012\000"
-.LC99:
- .ascii "Read pageadd=%x ecc=%x err=%x\012\000"
-.LC100:
- .ascii "data:\000"
-.LC101:
- .ascii "spare:\000"
-.LC102:
- .ascii "ReadRetry pageadd=%x ecc=%x err=%x\012\000"
-.LC103:
- .ascii "FLFB:%d %d\012\000"
-.LC104:
- .ascii "prog error: = %x\012\000"
-.LC105:
- .ascii "prog read error: = %x\012\000"
-.LC106:
- .ascii "prog read REFRESH: = %x\012\000"
-.LC107:
- .ascii "prog read s error: = %x %x %x\012\000"
-.LC108:
- .ascii "prog read d error: = %x %x %x\012\000"
-.LC109:
- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
- .ascii "\000"
-.LC110:
- .ascii "...%s enter...\012\000"
-.LC111:
- .ascii "superBlkID = %x vpc=%x\012\000"
-.LC112:
- .ascii "flashmode = %x pagenum = %x %x\012\000"
-.LC113:
- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
- .ascii "\000"
-.LC114:
- .ascii "blk = %x vpc=%x mode = %x\012\000"
-.LC115:
- .ascii "mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
- .ascii "%x\012\000"
-.LC116:
- .ascii "slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
- .ascii "%x\012\000"
-.LC117:
- .ascii "ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
-.LC118:
- .ascii "ftl_scan_all_ppa blk %x page %x flag: %x .........."
- .ascii "..... is bad block\012\000"
-.LC119:
- .ascii "addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
- .ascii "\000"
-.LC120:
- .ascii "%s finished\012\000"
-.LC121:
- .ascii "FlashMakeFactorBbt %d\012\000"
-.LC122:
- .ascii "bad block:%d %d\012\000"
-.LC123:
- .ascii "FMFB:%d %d\012\000"
-.LC124:
- .ascii "E:bad block:%d\012\000"
-.LC125:
- .ascii "FMFB:Save %d %d\012\000"
-.LC126:
- .ascii "FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
-.LC127:
- .ascii "FtlBbmTblFlush error:%x\012\000"
-.LC128:
- .ascii "FtlBbmTblFlush error = %x error count = %d\012\000"
-.LC129:
- .ascii "FtlGcFreeBadSuperBlk 0x%x\012\000"
-.LC130:
- .ascii "decrement_vpc_count %x = %d\012\000"
-.LC131:
- .ascii "decrement_vpc_count %x = %d in free list\012\000"
-.LC132:
- .ascii "FtlVpcTblFlush error = %x error count = %d\012\000"
-.LC133:
- .ascii "page map lost: %x %x\012\000"
-.LC134:
- .ascii "FtlMapWritePage error = %x\012\000"
-.LC135:
- .ascii "FtlMapWritePage error = %x error count = %d\012\000"
-.LC136:
- .ascii "FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
-.LC137:
- .ascii "no ect\000"
-.LC138:
- .ascii "slc mode\000"
-.LC139:
- .ascii "BBT:\000"
-.LC140:
- .ascii "region_id = %x phyAddr = %x\012\000"
-.LC141:
- .ascii "map_ppn:\000"
-.LC142:
- .ascii "load_l2p_region refresh = %x phyAddr = %x\012\000"
-.LC143:
- .ascii "FtlCheckVpc2 %x = %x %x\012\000"
-.LC144:
- .ascii "free blk vpc error %x = %x %x\012\000"
-.LC145:
- .ascii "error_flag %x\012\000"
-.LC146:
- .ascii "Ftlscanalldata = %x\012\000"
-.LC147:
- .ascii "scan lpa = %x ppa= %x\012\000"
-.LC148:
- .ascii "lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
- .ascii "\000"
-.LC149:
- .ascii "RSB refresh addr %x\012\000"
-.LC150:
- .ascii "spuer block %x vpn is 0\012 \000"
-.LC151:
- .ascii "g_recovery_ppa %x ver %x\012 \000"
-.LC152:
- .ascii "FtlCheckVpc %x = %x %x\012\000"
-.LC153:
- .ascii "FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
-.LC154:
- .ascii "FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
-.LC155:
- .ascii "GC des block %x done\012\000"
-.LC156:
- .ascii "too many bad block = %d %d\012\000"
-.LC157:
- .ascii "%d GC datablk = %x vpc %x %x\012\000"
-.LC158:
- .ascii "SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
-.LC159:
- .ascii "Ftlwrite decrement_vpc_count %x = %d\012\000"
-.LC160:
- .ascii "rk_ftl_de_init %x\012\000"
-.LC161:
- .ascii "...%s: no bad block mapping table, format device\012"
- .ascii "\000"
-.LC162:
- .ascii "...%s FtlSysBlkInit error ,format device!\012\000"
-.LC163:
- .ascii "FtlInit %x\012\000"
-.LC164:
- .ascii "fix power lost blk = %x vpc=%x\012\000"
-.LC165:
- .ascii "erase power lost blk = %x vpc=%x\012\000"
-.LC166:
- .ascii "FtlWrite: lpa error:%x %x\012\000"
-.LC167:
- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
- .ascii "\000"
-.LC168:
- .ascii ":\000"
-.LC169:
- .ascii "phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
- .ascii "\000"
-.LC170:
- .ascii "Mblk:\000"
-.LC171:
- .ascii "L2P:\000"
-.LC172:
- .ascii "L2PC:\000"
-.LC173:
- .ascii "write_idblock fix data %x %x\012\000"
-.LC174:
- .ascii "idblk:\000"
-.LC175:
- .ascii "idb reverse %x %x\012\000"
-.LC176:
- .ascii "write_idblock totle_sec %x %x %x %x\012\000"
-.LC177:
- .ascii "IDBlockWriteData %x %x\012\000"
-.LC178:
- .ascii "IDBlockWriteData %x %x ret= %x\012\000"
-.LC179:
- .ascii "IdBlockReadData %x %x\012\000"
-.LC180:
- .ascii "IdBlockReadData %x %x ret= %x\012\000"
-.LC181:
- .ascii "write and check error:%d idb=%x,offset=%x,r=%x,w=%x"
- .ascii "\012\000"
-.LC182:
- .ascii "write\000"
-.LC183:
- .ascii "read\000"
-.LC184:
- .ascii "write_idblock error %d\012\000"
-.LC185:
- .ascii "wl_lba %p %x %x %x\012\000"
-.LC186:
- .ascii "RKNAND_GET_DRM_KEY\012\000"
-.LC187:
- .ascii "rk_copy_from_user error\012\000"
-.LC188:
- .ascii "RKNAND_STORE_DRM_KEY\012\000"
-.LC189:
- .ascii "RKNAND_DIASBLE_SECURE_BOOT\012\000"
-.LC190:
- .ascii "RKNAND_ENASBLE_SECURE_BOOT\012\000"
-.LC191:
- .ascii "RKNAND_GET_SN_SECTOR\012\000"
-.LC192:
- .ascii "RKNAND_LOADER_UNLOCK\012\000"
-.LC193:
- .ascii "RKNAND_LOADER_STATUS\012\000"
-.LC194:
- .ascii "RKNAND_LOADER_LOCK\012\000"
-.LC195:
- .ascii "LockKey not match %d\012\000"
-.LC196:
- .ascii "RKNAND_GET_VENDOR_SECTOR\012\000"
-.LC197:
- .ascii "RKNAND_STORE_VENDOR_SECTOR\012\000"
-.LC198:
- .ascii "return ret = %lx\012\000"
-.LC199:
- .ascii "secureBootEn check error\012\000"
-.LC200:
- .ascii "\0013vendor storage %x,%x,%x\012\000"
.data
.align 2
-.LANCHOR1 = . + 0
+ .set .LANCHOR1,. + 0
.type random_seed, %object
.size random_seed, 256
random_seed:
@@ -26018,7 +26129,6 @@
.byte 126
.byte 124
.byte 0
- .space 3
.type Toshiba15RefValue, %object
.size Toshiba15RefValue, 95
Toshiba15RefValue:
@@ -26117,7 +26227,6 @@
.byte 116
.byte 114
.byte 0
- .space 1
.type ToshibaRefValue, %object
.size ToshibaRefValue, 8
ToshibaRefValue:
@@ -28614,9 +28723,16 @@
.word 1
.bss
.align 2
-.LANCHOR0 = . + 0
-.LANCHOR2 = . + 8184
-.LANCHOR4 = . + 16368
+ .set .LANCHOR0,. + 0
+ .set .LANCHOR2,. + 8184
+ .type gNandChipMap, %object
+ .size gNandChipMap, 32
+gNandChipMap:
+ .space 32
+ .type p_blk_mode_table, %object
+ .size p_blk_mode_table, 4
+p_blk_mode_table:
+ .space 4
.type g_slc2KBNand, %object
.size g_slc2KBNand, 1
g_slc2KBNand:
@@ -28635,10 +28751,6 @@
gNandRandomizer:
.space 1
.space 3
- .type gNandChipMap, %object
- .size gNandChipMap, 32
-gNandChipMap:
- .space 32
.type gpNandParaInfo, %object
.size gpNandParaInfo, 4
gpNandParaInfo:
@@ -28647,6 +28759,15 @@
.size gNandOptPara, 32
gNandOptPara:
.space 32
+ .type g_retryMode, %object
+ .size g_retryMode, 1
+g_retryMode:
+ .space 1
+ .type g_maxRegNum, %object
+ .size g_maxRegNum, 1
+g_maxRegNum:
+ .space 1
+ .space 2
.type gpNandc, %object
.size gpNandc, 4
gpNandc:
@@ -28704,19 +28825,10 @@
.size FlashWaitBusyScheduleEn, 4
FlashWaitBusyScheduleEn:
.space 4
- .type g_retryMode, %object
- .size g_retryMode, 1
-g_retryMode:
- .space 1
- .type g_maxRegNum, %object
- .size g_maxRegNum, 1
-g_maxRegNum:
- .space 1
.type gReadRetryInfo, %object
.size gReadRetryInfo, 852
gReadRetryInfo:
.space 852
- .space 2
.type read_retry_cur_offset, %object
.size read_retry_cur_offset, 4
read_retry_cur_offset:
@@ -28838,7 +28950,6 @@
.size c_ftl_nand_planes_per_die, 2
c_ftl_nand_planes_per_die:
.space 2
- .space 2
.type p_plane_order_table, %object
.size p_plane_order_table, 32
p_plane_order_table:
@@ -28890,6 +29001,7 @@
.type c_ftl_nand_reserved_blks, %object
.size c_ftl_nand_reserved_blks, 2
c_ftl_nand_reserved_blks:
+ .space 2
.space 2
.type DeviceCapacity, %object
.size DeviceCapacity, 4
@@ -29038,10 +29150,6 @@
.size g_VaildLpn, 4
g_VaildLpn:
.space 4
- .type p_blk_mode_table, %object
- .size p_blk_mode_table, 4
-p_blk_mode_table:
- .space 4
.type g_totle_read_page_count, %object
.size g_totle_read_page_count, 4
g_totle_read_page_count:
@@ -29115,14 +29223,14 @@
.size g_gc_superblock, 48
g_gc_superblock:
.space 48
- .type g_all_blk_used_slc_mode, %object
- .size g_all_blk_used_slc_mode, 4
-g_all_blk_used_slc_mode:
- .space 4
.type g_sys_ext_data, %object
.size g_sys_ext_data, 512
g_sys_ext_data:
.space 512
+ .type g_all_blk_used_slc_mode, %object
+ .size g_all_blk_used_slc_mode, 4
+g_all_blk_used_slc_mode:
+ .space 4
.type g_gc_free_blk_threshold, %object
.size g_gc_free_blk_threshold, 2
g_gc_free_blk_threshold:
@@ -29404,6 +29512,14 @@
.size RK29_NANDC_REG_BASE, 4
RK29_NANDC_REG_BASE:
.space 4
+ .type ftl_dma32_buffer_size, %object
+ .size ftl_dma32_buffer_size, 4
+ftl_dma32_buffer_size:
+ .space 4
+ .type ftl_dma32_buffer, %object
+ .size ftl_dma32_buffer, 4
+ftl_dma32_buffer:
+ .space 4
.type gFlashPageBuffer0, %object
.size gFlashPageBuffer0, 4
gFlashPageBuffer0:
@@ -29465,11 +29581,11 @@
.size gMultiPageReadEn, 1
gMultiPageReadEn:
.space 1
- .space 2
.type FbbtBlk, %object
.size FbbtBlk, 16
FbbtBlk:
.space 16
+ .space 2
.type req_sys, %object
.size req_sys, 36
req_sys:
@@ -29486,11 +29602,6 @@
.size g_ect_tbl_power_up_flush, 2
g_ect_tbl_power_up_flush:
.space 2
- .space 2
- .type check_valid_page_count_table, %object
- .size check_valid_page_count_table, 8192
-check_valid_page_count_table:
- .space 8192
.type g_power_lost_ecc_error_blk, %object
.size g_power_lost_ecc_error_blk, 2
g_power_lost_ecc_error_blk:
@@ -29498,6 +29609,7 @@
.type g_power_lost_recovery_flag, %object
.size g_power_lost_recovery_flag, 2
g_power_lost_recovery_flag:
+ .space 2
.space 2
.type g_recovery_page_num, %object
.size g_recovery_page_num, 4
@@ -29601,6 +29713,10 @@
.size g_vendor, 4
g_vendor:
.space 4
+ .type check_valid_page_count_table, %object
+ .size check_valid_page_count_table, 8192
+check_valid_page_count_table:
+ .space 8192
.type g_gc_refresh_block_temp_tbl, %object
.size g_gc_refresh_block_temp_tbl, 34
g_gc_refresh_block_temp_tbl:
@@ -29630,3 +29746,419 @@
.size gFlashSdrModeEn, 1
gFlashSdrModeEn:
.space 1
+ .section .rodata.str1.1,"aMS",%progbits,1
+.LC1:
+ .ascii "FlashEraseBlocks pageAddr error %x\012\000"
+.LC2:
+ .ascii "phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
+ .ascii "\000"
+.LC3:
+ .ascii "FtlFreeSysBlkQueueOut free count = %d\012\000"
+.LC4:
+ .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
+ .ascii "\000"
+.LC5:
+ .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
+.LC6:
+ .ascii "FLASH INFO:\012\000"
+.LC7:
+ .ascii "FLASH ID: %x\012\000"
+.LC8:
+ .ascii "Device Capacity: %d MB\012\000"
+.LC9:
+ .ascii "FMWAIT: %x %x %x %x\012\000"
+.LC10:
+ .ascii "FTL INFO:\012\000"
+.LC11:
+ .ascii "g_MaxLpn = 0x%x\012\000"
+.LC12:
+ .ascii "g_VaildLpn = 0x%x\012\000"
+.LC13:
+ .ascii "read_page_count = 0x%x\012\000"
+.LC14:
+ .ascii "discard_page_count = 0x%x\012\000"
+.LC15:
+ .ascii "write_page_count = 0x%x\012\000"
+.LC16:
+ .ascii "cache_write_count = 0x%x\012\000"
+.LC17:
+ .ascii "l2p_write_count = 0x%x\012\000"
+.LC18:
+ .ascii "gc_page_count = 0x%x\012\000"
+.LC19:
+ .ascii "totle_write = %d MB\012\000"
+.LC20:
+ .ascii "totle_read = %d MB\012\000"
+.LC21:
+ .ascii "GSV = 0x%x\012\000"
+.LC22:
+ .ascii "GDV = 0x%x\012\000"
+.LC23:
+ .ascii "bad blk num = %d %d\012\000"
+.LC24:
+ .ascii "free_superblocks = 0x%x\012\000"
+.LC25:
+ .ascii "mlc_EC = 0x%x\012\000"
+.LC26:
+ .ascii "slc_EC = 0x%x\012\000"
+.LC27:
+ .ascii "avg_EC = 0x%x\012\000"
+.LC28:
+ .ascii "sys_EC = 0x%x\012\000"
+.LC29:
+ .ascii "max_EC = 0x%x\012\000"
+.LC30:
+ .ascii "min_EC = 0x%x\012\000"
+.LC31:
+ .ascii "PLT = 0x%x\012\000"
+.LC32:
+ .ascii "POT = 0x%x\012\000"
+.LC33:
+ .ascii "MaxSector = 0x%x\012\000"
+.LC34:
+ .ascii "init_sys_blks_pp = 0x%x\012\000"
+.LC35:
+ .ascii "sys_blks_pp = 0x%x\012\000"
+.LC36:
+ .ascii "free sysblock = 0x%x\012\000"
+.LC37:
+ .ascii "data_blks_pp = 0x%x\012\000"
+.LC38:
+ .ascii "data_op_blks_pp = 0x%x\012\000"
+.LC39:
+ .ascii "max_data_blks = 0x%x\012\000"
+.LC40:
+ .ascii "Sys.id = 0x%x\012\000"
+.LC41:
+ .ascii "Bbt.id = 0x%x\012\000"
+.LC42:
+ .ascii "ACT.page = 0x%x\012\000"
+.LC43:
+ .ascii "ACT.plane = 0x%x\012\000"
+.LC44:
+ .ascii "ACT.id = 0x%x\012\000"
+.LC45:
+ .ascii "ACT.mode = 0x%x\012\000"
+.LC46:
+ .ascii "ACT.a_pages = 0x%x\012\000"
+.LC47:
+ .ascii "ACT VPC = 0x%x\012\000"
+.LC48:
+ .ascii "BUF.page = 0x%x\012\000"
+.LC49:
+ .ascii "BUF.plane = 0x%x\012\000"
+.LC50:
+ .ascii "BUF.id = 0x%x\012\000"
+.LC51:
+ .ascii "BUF.mode = 0x%x\012\000"
+.LC52:
+ .ascii "BUF.a_pages = 0x%x\012\000"
+.LC53:
+ .ascii "BUF VPC = 0x%x\012\000"
+.LC54:
+ .ascii "TMP.page = 0x%x\012\000"
+.LC55:
+ .ascii "TMP.plane = 0x%x\012\000"
+.LC56:
+ .ascii "TMP.id = 0x%x\012\000"
+.LC57:
+ .ascii "TMP.mode = 0x%x\012\000"
+.LC58:
+ .ascii "TMP.a_pages = 0x%x\012\000"
+.LC59:
+ .ascii "GC.page = 0x%x\012\000"
+.LC60:
+ .ascii "GC.plane = 0x%x\012\000"
+.LC61:
+ .ascii "GC.id = 0x%x\012\000"
+.LC62:
+ .ascii "GC.mode = 0x%x\012\000"
+.LC63:
+ .ascii "GC.a_pages = 0x%x\012\000"
+.LC64:
+ .ascii "WR_CHK = 0x%x %x %x %x\012\000"
+.LC65:
+ .ascii "Read Err = 0x%x\012\000"
+.LC66:
+ .ascii "Prog Err = 0x%x\012\000"
+.LC67:
+ .ascii "gc_free_blk_th= 0x%x\012\000"
+.LC68:
+ .ascii "gc_merge_free_blk_th= 0x%x\012\000"
+.LC69:
+ .ascii "gc_skip_write_count= 0x%x\012\000"
+.LC70:
+ .ascii "gc_blk_index= 0x%x\012\000"
+.LC71:
+ .ascii "free min EC= 0x%x\012\000"
+.LC72:
+ .ascii "free max EC= 0x%x\012\000"
+.LC73:
+ .ascii "GC__SB VPC = 0x%x\012\000"
+.LC74:
+ .ascii "%d. [0x%x]=0x%x 0x%x 0x%x\012\000"
+.LC75:
+ .ascii "free %d. [0x%x] 0x%x 0x%x\012\000"
+.LC76:
+ .ascii "FTL version: 5.0.63 20210616\000"
+.LC77:
+ .ascii "%s\012\000"
+.LC78:
+ .ascii "swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
+ .ascii "\012\000"
+.LC79:
+ .ascii "FtlGcRefreshBlock 0x%x\012\000"
+.LC80:
+ .ascii "FtlGcMarkBadPhyBlk %d 0x%x\012\000"
+.LC81:
+ .ascii "%s error allocating memory. return -1\012\000"
+.LC82:
+ .ascii "%s %p:0x%x:\000"
+.LC83:
+ .ascii "%x \000"
+.LC84:
+ .ascii "\000"
+.LC85:
+ .ascii "otp error! %d\000"
+.LC86:
+ .ascii "rr\000"
+.LC87:
+ .ascii "%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
+ .ascii "\000"
+.LC88:
+ .ascii "nandc:\000"
+.LC89:
+ .ascii "%d flReg.d32=%x %x\012\000"
+.LC90:
+ .ascii "sdr read ok %x ecc=%d\012\000"
+.LC91:
+ .ascii "sync para %d\012\000"
+.LC92:
+ .ascii "TOG mode Read error %x %x\012\000"
+.LC93:
+ .ascii "read retry status %x %x %x\012\000"
+.LC94:
+ .ascii "micron RR %d row=%x,count %d,status=%d\012\000"
+.LC95:
+ .ascii "samsung RR %d row=%x,count %d,status=%d\012\000"
+.LC96:
+ .ascii "ECC:%d\012\000"
+.LC97:
+ .ascii "No.%d FLASH ID:%x %x %x %x %x %x\012\000"
+.LC98:
+ .ascii "FlashLoadPhyInfo fail %x!!\012\000"
+.LC99:
+ .ascii "Read pageadd=%x ecc=%x err=%x\012\000"
+.LC100:
+ .ascii "data:\000"
+.LC101:
+ .ascii "spare:\000"
+.LC102:
+ .ascii "ReadRetry pageadd=%x ecc=%x err=%x\012\000"
+.LC103:
+ .ascii "FLFB:%d %d\012\000"
+.LC104:
+ .ascii "prog error: = %x\012\000"
+.LC105:
+ .ascii "prog read error: = %x\012\000"
+.LC106:
+ .ascii "prog read REFRESH: = %x\012\000"
+.LC107:
+ .ascii "prog read s error: = %x %x %x\012\000"
+.LC108:
+ .ascii "prog read d error: = %x %x %x\012\000"
+.LC109:
+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
+ .ascii "\000"
+.LC110:
+ .ascii "...%s enter...\012\000"
+.LC111:
+ .ascii "superBlkID = %x vpc=%x\012\000"
+.LC112:
+ .ascii "flashmode = %x pagenum = %x %x\012\000"
+.LC113:
+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
+ .ascii "\000"
+.LC114:
+ .ascii "blk = %x vpc=%x mode = %x\012\000"
+.LC115:
+ .ascii "mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
+ .ascii "%x\012\000"
+.LC116:
+ .ascii "slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
+ .ascii "%x\012\000"
+.LC117:
+ .ascii "ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
+.LC118:
+ .ascii "ftl_scan_all_ppa blk %x page %x flag: %x .........."
+ .ascii "..... is bad block\012\000"
+.LC119:
+ .ascii "addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
+ .ascii "\000"
+.LC120:
+ .ascii "%s finished\012\000"
+.LC121:
+ .ascii "FlashMakeFactorBbt %d\012\000"
+.LC122:
+ .ascii "bad block:%d %d\012\000"
+.LC123:
+ .ascii "FMFB:%d %d\012\000"
+.LC124:
+ .ascii "E:bad block:%d\012\000"
+.LC125:
+ .ascii "FMFB:Save %d %d\012\000"
+.LC126:
+ .ascii "FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
+.LC127:
+ .ascii "FtlBbmTblFlush error:%x\012\000"
+.LC128:
+ .ascii "FtlBbmTblFlush error = %x error count = %d\012\000"
+.LC129:
+ .ascii "FtlGcFreeBadSuperBlk 0x%x\012\000"
+.LC130:
+ .ascii "decrement_vpc_count %x = %d\012\000"
+.LC131:
+ .ascii "decrement_vpc_count %x = %d in free list\012\000"
+.LC132:
+ .ascii "FtlVpcTblFlush error = %x error count = %d\012\000"
+.LC133:
+ .ascii "page map lost: %x %x\012\000"
+.LC134:
+ .ascii "FtlMapWritePage error = %x\012\000"
+.LC135:
+ .ascii "FtlMapWritePage error = %x error count = %d\012\000"
+.LC136:
+ .ascii "FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
+.LC137:
+ .ascii "no ect\000"
+.LC138:
+ .ascii "slc mode\000"
+.LC139:
+ .ascii "BBT:\000"
+.LC140:
+ .ascii "region_id = %x phyAddr = %x\012\000"
+.LC141:
+ .ascii "map_ppn:\000"
+.LC142:
+ .ascii "load_l2p_region refresh = %x phyAddr = %x\012\000"
+.LC143:
+ .ascii "FtlCheckVpc2 %x = %x %x\012\000"
+.LC144:
+ .ascii "free blk vpc error %x = %x %x\012\000"
+.LC145:
+ .ascii "error_flag %x\012\000"
+.LC146:
+ .ascii "Ftlscanalldata = %x\012\000"
+.LC147:
+ .ascii "scan lpa = %x ppa= %x\012\000"
+.LC148:
+ .ascii "lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
+ .ascii "\000"
+.LC149:
+ .ascii "RSB refresh addr %x\012\000"
+.LC150:
+ .ascii "spuer block %x vpn is 0\012 \000"
+.LC151:
+ .ascii "g_recovery_ppa %x ver %x\012 \000"
+.LC152:
+ .ascii "FtlCheckVpc %x = %x %x\012\000"
+.LC153:
+ .ascii "FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
+.LC154:
+ .ascii "FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
+.LC155:
+ .ascii "GC des block %x done\012\000"
+.LC156:
+ .ascii "too many bad block = %d %d\012\000"
+.LC157:
+ .ascii "%d GC datablk = %x vpc %x %x\012\000"
+.LC158:
+ .ascii "SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
+.LC159:
+ .ascii "Ftlwrite decrement_vpc_count %x = %d\012\000"
+.LC160:
+ .ascii "rk_ftl_de_init %x\012\000"
+.LC161:
+ .ascii "...%s: no bad block mapping table, format device\012"
+ .ascii "\000"
+.LC162:
+ .ascii "...%s FtlSysBlkInit error ,format device!\012\000"
+.LC163:
+ .ascii "FtlInit %x\012\000"
+.LC164:
+ .ascii "fix power lost blk = %x vpc=%x\012\000"
+.LC165:
+ .ascii "erase power lost blk = %x vpc=%x\012\000"
+.LC166:
+ .ascii "FtlWrite: lpa error:%x %x\012\000"
+.LC167:
+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
+ .ascii "\000"
+.LC168:
+ .ascii ":\000"
+.LC169:
+ .ascii "phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
+ .ascii "\000"
+.LC170:
+ .ascii "Mblk:\000"
+.LC171:
+ .ascii "L2P:\000"
+.LC172:
+ .ascii "L2PC:\000"
+.LC173:
+ .ascii "write_idblock fix data %x %x\012\000"
+.LC174:
+ .ascii "idblk:\000"
+.LC175:
+ .ascii "idb reverse %x %x\012\000"
+.LC176:
+ .ascii "write_idblock totle_sec %x %x %x %x\012\000"
+.LC177:
+ .ascii "IDBlockWriteData %x %x\012\000"
+.LC178:
+ .ascii "IDBlockWriteData %x %x ret= %x\012\000"
+.LC179:
+ .ascii "IdBlockReadData %x %x\012\000"
+.LC180:
+ .ascii "IdBlockReadData %x %x ret= %x\012\000"
+.LC181:
+ .ascii "write and check error:%d idb=%x,offset=%x,r=%x,w=%x"
+ .ascii "\012\000"
+.LC182:
+ .ascii "write\000"
+.LC183:
+ .ascii "read\000"
+.LC184:
+ .ascii "write_idblock error %d\012\000"
+.LC185:
+ .ascii "wl_lba %p %x %x %x\012\000"
+.LC186:
+ .ascii "RKNAND_GET_DRM_KEY\012\000"
+.LC187:
+ .ascii "rk_copy_from_user error\012\000"
+.LC188:
+ .ascii "RKNAND_STORE_DRM_KEY\012\000"
+.LC189:
+ .ascii "RKNAND_DIASBLE_SECURE_BOOT\012\000"
+.LC190:
+ .ascii "RKNAND_ENASBLE_SECURE_BOOT\012\000"
+.LC191:
+ .ascii "RKNAND_GET_SN_SECTOR\012\000"
+.LC192:
+ .ascii "RKNAND_LOADER_UNLOCK\012\000"
+.LC193:
+ .ascii "RKNAND_LOADER_STATUS\012\000"
+.LC194:
+ .ascii "RKNAND_LOADER_LOCK\012\000"
+.LC195:
+ .ascii "LockKey not match %d\012\000"
+.LC196:
+ .ascii "RKNAND_GET_VENDOR_SECTOR\012\000"
+.LC197:
+ .ascii "RKNAND_STORE_VENDOR_SECTOR\012\000"
+.LC198:
+ .ascii "return ret = %lx\012\000"
+.LC199:
+ .ascii "secureBootEn check error\012\000"
+.LC200:
+ .ascii "\0013vendor storage %x,%x,%x\012\000"
--
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