From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h | 55 +++++++++++++++++++++++++++++++++++++------------------
1 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h b/kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h
index e05db6b..e624f69 100644
--- a/kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/kernel/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Free Electrons
* Copyright (C) 2015 NextThing Co
*
* Boris Brezillon <boris.brezillon@free-electrons.com>
* Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
*/
#ifndef __SUN4I_TCON_H__
@@ -37,18 +33,21 @@
#define SUN4I_TCON_GINT1_REG 0x8
#define SUN4I_TCON_FRM_CTL_REG 0x10
-#define SUN4I_TCON_FRM_CTL_EN BIT(31)
+#define SUN4I_TCON0_FRM_CTL_EN BIT(31)
+#define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6)
+#define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5)
+#define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4)
-#define SUN4I_TCON_FRM_SEED_PR_REG 0x14
-#define SUN4I_TCON_FRM_SEED_PG_REG 0x18
-#define SUN4I_TCON_FRM_SEED_PB_REG 0x1c
-#define SUN4I_TCON_FRM_SEED_LR_REG 0x20
-#define SUN4I_TCON_FRM_SEED_LG_REG 0x24
-#define SUN4I_TCON_FRM_SEED_LB_REG 0x28
-#define SUN4I_TCON_FRM_TBL0_REG 0x2c
-#define SUN4I_TCON_FRM_TBL1_REG 0x30
-#define SUN4I_TCON_FRM_TBL2_REG 0x34
-#define SUN4I_TCON_FRM_TBL3_REG 0x38
+#define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
+#define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
+#define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
+#define SUN4I_TCON0_FRM_SEED_LR_REG 0x20
+#define SUN4I_TCON0_FRM_SEED_LG_REG 0x24
+#define SUN4I_TCON0_FRM_SEED_LB_REG 0x28
+#define SUN4I_TCON0_FRM_TBL0_REG 0x2c
+#define SUN4I_TCON0_FRM_TBL1_REG 0x30
+#define SUN4I_TCON0_FRM_TBL2_REG 0x34
+#define SUN4I_TCON0_FRM_TBL3_REG 0x38
#define SUN4I_TCON0_CTL_REG 0x40
#define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31)
@@ -113,6 +112,8 @@
#define SUN4I_TCON0_IO_POL_REG 0x88
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
+#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
+#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
@@ -153,6 +154,11 @@
#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
#define SUN4I_TCON1_IO_POL_REG 0xf0
+/* there is no documentation about this bit */
+#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
+#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
+#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
+
#define SUN4I_TCON1_IO_TRI_REG 0xf4
#define SUN4I_TCON_ECC_FIFO_REG 0xf8
@@ -193,6 +199,13 @@
#define SUN4I_TCON_MUX_CTRL_REG 0x200
#define SUN4I_TCON0_LVDS_ANA0_REG 0x220
+#define SUN4I_TCON0_LVDS_ANA0_DCHS BIT(16)
+#define SUN4I_TCON0_LVDS_ANA0_PD (BIT(20) | BIT(21))
+#define SUN4I_TCON0_LVDS_ANA0_EN_MB BIT(22)
+#define SUN4I_TCON0_LVDS_ANA0_REG_C (BIT(24) | BIT(25))
+#define SUN4I_TCON0_LVDS_ANA0_REG_V (BIT(26) | BIT(27))
+#define SUN4I_TCON0_LVDS_ANA0_CK_EN (BIT(29) | BIT(28))
+
#define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31)
#define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
#define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
@@ -200,6 +213,10 @@
#define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17)
#define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
#define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4)
+
+#define SUN4I_TCON0_LVDS_ANA1_REG 0x224
+#define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f << 10)
+#define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f << 00)
#define SUN4I_TCON1_FILL_CTL_REG 0x300
#define SUN4I_TCON1_FILL_BEG0_REG 0x304
@@ -224,10 +241,14 @@
bool needs_de_be_mux; /* sun6i needs mux to select backend */
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
bool supports_lvds; /* Does the TCON support an LVDS output? */
+ bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
+ /* handler for LVDS setup routine */
+ void (*setup_lvds_phy)(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder);
};
struct sun4i_tcon {
@@ -253,8 +274,6 @@
/* Reset control */
struct reset_control *lcd_rst;
struct reset_control *lvds_rst;
-
- struct drm_panel *panel;
/* Platform adjustments */
const struct sun4i_tcon_quirks *quirks;
--
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