From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 328 +++++++++++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 294 insertions(+), 34 deletions(-)
diff --git a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index a0677dd..5f72a76 100644
--- a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -1,42 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author:Mark Yao <mark.yao@rock-chips.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H
+
+#include <drm/drm_plane.h>
+#include <drm/drm_modes.h>
+
#include "rockchip_drm_drv.h"
/*
* major: IP major version, used for IP structure
* minor: big feature change under same structure
+ * build: RTL current SVN number
*/
#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
#define VOP_MAJOR(version) ((version) >> 8)
#define VOP_MINOR(version) ((version) & 0xff)
-#define VOP_VERSION_RK3528 VOP_VERSION(0x50, 0x17)
-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
+#define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
+#define VOP2_BUILD(version) ((version) & 0xffff)
+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
+
+/* register one connector */
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
+/* register one connector */
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
+/* MIPI DSI DataStream(cmd) mode on rk3588 */
+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
+/* register two connector */
+#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
#define AFBDC_FMT_RGB565 0x0
#define AFBDC_FMT_U8U8U8U8 0x5
#define AFBDC_FMT_U8U8U8 0x4
-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
-#define VOP_FEATURE_AFBDC BIT(1)
+
+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
#define VOP_FEATURE_ALPHA_SCALE BIT(2)
#define VOP_FEATURE_HDR10 BIT(3)
#define VOP_FEATURE_NEXT_HDR BIT(4)
@@ -47,12 +57,17 @@
#define VOP_FEATURE_POST_ACM BIT(8)
#define VOP_FEATURE_POST_CSC BIT(9)
+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
+
+
#define WIN_FEATURE_HDR2SDR BIT(0)
#define WIN_FEATURE_SDR2HDR BIT(1)
#define WIN_FEATURE_PRE_OVERLAY BIT(2)
#define WIN_FEATURE_AFBDC BIT(3)
#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
#define WIN_FEATURE_CLUSTER_SUB BIT(5)
+/* Left win in splice mode */
+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
/* a mirror win can only get fb address
* from source win:
* Cluster1---->Cluster0
@@ -66,6 +81,15 @@
#define VOP2_SOC_VARIANT 4
+
+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
+
+enum vop_vp_id {
+ ROCKCHIP_VOP_VP0 = 0,
+ ROCKCHIP_VOP_VP1,
+ ROCKCHIP_VOP_VP2,
+ ROCKCHIP_VOP_VP3,
+};
enum bcsh_out_mode {
BCSH_OUT_MODE_BLACK,
@@ -88,7 +112,7 @@
/*
* the delay number of a window in different mode.
*/
-enum win_dly_mode {
+enum vop2_win_dly_mode {
VOP2_DLY_MODE_DEFAULT, /**< default mode */
VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
@@ -101,6 +125,39 @@
VOP3_ESMART_4K_2K_2K_MODE,
VOP3_ESMART_2K_2K_2K_2K_MODE,
};
+
+/*
+ * vop2 dsc id
+ */
+#define ROCKCHIP_VOP2_DSC_8K 0
+#define ROCKCHIP_VOP2_DSC_4K 1
+
+/*
+ * vop2 internal power domain id,
+ * should be all none zero, 0 will be
+ * treat as invalid;
+ */
+#define VOP2_PD_CLUSTER0 BIT(0)
+#define VOP2_PD_CLUSTER1 BIT(1)
+#define VOP2_PD_CLUSTER2 BIT(2)
+#define VOP2_PD_CLUSTER3 BIT(3)
+#define VOP2_PD_DSC_8K BIT(5)
+#define VOP2_PD_DSC_4K BIT(6)
+#define VOP2_PD_ESMART BIT(7)
+
+/*
+ * vop2 submem power gate,
+ * should be all none zero, 0 will be
+ * treat as invalid;
+ */
+#define VOP2_MEM_PG_VP0 BIT(0)
+#define VOP2_MEM_PG_VP1 BIT(1)
+#define VOP2_MEM_PG_VP2 BIT(2)
+#define VOP2_MEM_PG_VP3 BIT(3)
+#define VOP2_MEM_PG_DB0 BIT(4)
+#define VOP2_MEM_PG_DB1 BIT(5)
+#define VOP2_MEM_PG_DB2 BIT(6)
+#define VOP2_MEM_PG_WB BIT(7)
#define DSP_BG_SWAP 0x1
#define DSP_RB_SWAP 0x2
@@ -139,6 +196,13 @@
VOP_FMT_YUV420SP = 4,
VOP_FMT_YUV422SP,
VOP_FMT_YUV444SP,
+};
+
+enum vop_dsc_interface_mode {
+ VOP_DSC_IF_DISABLE = 0,
+ VOP_DSC_IF_HDMI = 1,
+ VOP_DSC_IF_MIPI_DS_MODE = 2,
+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
};
struct vop_reg_data {
@@ -191,6 +255,7 @@
struct vop_reg post_scl_factor;
struct vop_reg post_scl_ctrl;
struct vop_reg dsp_interlace;
+ struct vop_reg dsp_interlace_pol;
struct vop_reg global_regdone_en;
struct vop_reg auto_gate_en;
struct vop_reg post_lb_mode;
@@ -236,6 +301,11 @@
struct vop_reg sw_uv_offset_en;
struct vop_reg dsp_out_yuv;
struct vop_reg dsp_data_swap;
+ struct vop_reg dsp_bg_swap;
+ struct vop_reg dsp_rb_swap;
+ struct vop_reg dsp_rg_swap;
+ struct vop_reg dsp_delta_swap;
+ struct vop_reg dsp_dummy_swap;
struct vop_reg yuv_clip;
struct vop_reg dsp_ccir656_avg;
struct vop_reg dsp_black;
@@ -582,6 +652,7 @@
struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format;
+ struct vop_reg interlace_read;
struct vop_reg fmt_10;
struct vop_reg fmt_yuyv;
struct vop_reg csc_mode;
@@ -605,6 +676,17 @@
struct vop_reg global_alpha_val;
struct vop_reg color_key;
struct vop_reg color_key_en;
+};
+
+struct vop_win_data {
+ uint32_t base;
+ enum drm_plane_type type;
+ const struct vop_win_phy *phy;
+ const struct vop_win_phy **area;
+ const uint64_t *format_modifiers;
+ const struct vop_csc *csc;
+ unsigned int area_size;
+ u64 feature;
};
struct vop2_cluster_regs {
@@ -701,7 +783,9 @@
struct vop_reg pre_scan_htiming;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
- struct vop_reg vtotal_pw;
+ struct vop_reg dsp_vtotal;
+ struct vop_reg sw_dsp_vtotal_imd;
+ struct vop_reg dsp_vs_end;
struct vop_reg vact_st_end;
struct vop_reg vact_st_end_f1;
struct vop_reg vs_st_end_f1;
@@ -719,8 +803,8 @@
struct vop_reg core_dclk_div;
struct vop_reg p2i_en;
- struct vop_reg mipi_dual_en;
- struct vop_reg mipi_dual_channel_swap;
+ struct vop_reg dual_channel_en;
+ struct vop_reg dual_channel_swap;
struct vop_reg dsp_lut_en;
struct vop_reg dclk_div2;
@@ -783,11 +867,37 @@
struct vop_reg cubic_lut_update_en;
struct vop_reg cubic_lut_mst;
+ /* cru */
+ struct vop_reg dclk_core_div;
+ struct vop_reg dclk_out_div;
+ struct vop_reg dclk_src_sel;
+
+ struct vop_reg splice_en;
+
struct vop_reg edpi_wms_hold_en;
struct vop_reg edpi_te_en;
struct vop_reg edpi_wms_fs;
struct vop_reg gamma_update_en;
struct vop_reg lut_dma_rid;
+
+ /* MCU output */
+ struct vop_reg mcu_pix_total;
+ struct vop_reg mcu_cs_pst;
+ struct vop_reg mcu_cs_pend;
+ struct vop_reg mcu_rw_pst;
+ struct vop_reg mcu_rw_pend;
+ struct vop_reg mcu_clk_sel;
+ struct vop_reg mcu_hold_mode;
+ struct vop_reg mcu_frame_st;
+ struct vop_reg mcu_rs;
+ struct vop_reg mcu_bypass;
+ struct vop_reg mcu_type;
+ struct vop_reg mcu_rw_bypass_port;
+
+ /* for DCF */
+ struct vop_reg line_flag_or_en;
+ struct vop_reg dsp_hold_or_en;
+ struct vop_reg almost_full_or_en;
/* CSC */
struct vop_reg acm_bypass_en;
@@ -807,6 +917,58 @@
struct vop_reg csc_offset0;
struct vop_reg csc_offset1;
struct vop_reg csc_offset2;
+
+ /* color bar */
+ struct vop_reg color_bar_en;
+ struct vop_reg color_bar_mode;
+};
+
+struct vop2_power_domain_regs {
+ struct vop_reg pd;
+ struct vop_reg status;
+ struct vop_reg bisr_en_status;
+ struct vop_reg pmu_status;
+};
+
+struct vop2_dsc_regs {
+ /* DSC SYS CTRL */
+ struct vop_reg dsc_port_sel;
+ struct vop_reg dsc_man_mode;
+ struct vop_reg dsc_interface_mode;
+ struct vop_reg dsc_pixel_num;
+ struct vop_reg dsc_pxl_clk_div;
+ struct vop_reg dsc_cds_clk_div;
+ struct vop_reg dsc_txp_clk_div;
+ struct vop_reg dsc_init_dly_mode;
+ struct vop_reg dsc_scan_en;
+ struct vop_reg dsc_halt_en;
+ struct vop_reg rst_deassert;
+ struct vop_reg dsc_flush;
+ struct vop_reg dsc_cfg_done;
+ struct vop_reg dsc_init_dly_num;
+ struct vop_reg scan_timing_para_imd_en;
+ struct vop_reg dsc_htotal_pw;
+ struct vop_reg dsc_hact_st_end;
+ struct vop_reg dsc_vtotal;
+ struct vop_reg dsc_vs_end;
+ struct vop_reg dsc_vact_st_end;
+ struct vop_reg dsc_error_status;
+
+ /* DSC encoder */
+ struct vop_reg dsc_pps0_3;
+ struct vop_reg dsc_en;
+ struct vop_reg dsc_rbit;
+ struct vop_reg dsc_rbyt;
+ struct vop_reg dsc_flal;
+ struct vop_reg dsc_mer;
+ struct vop_reg dsc_epb;
+ struct vop_reg dsc_epl;
+ struct vop_reg dsc_nslc;
+ struct vop_reg dsc_sbo;
+ struct vop_reg dsc_ifep;
+ struct vop_reg dsc_pps_upd;
+ struct vop_reg dsc_status;
+ struct vop_reg dsc_ecw;
};
struct vop2_wb_regs {
@@ -825,19 +987,39 @@
struct vop_reg axi_uv_id;
};
-struct vop_win_data {
- uint32_t base;
- enum drm_plane_type type;
- const struct vop_win_phy *phy;
- const struct vop_win_phy **area;
- const struct vop_csc *csc;
- unsigned int area_size;
- u64 feature;
+struct vop2_power_domain_data {
+ uint8_t id;
+ uint8_t parent_id;
+ /*
+ * @module_id_mask: module id of which module this power domain is belongs to.
+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
+ */
+ uint32_t module_id_mask;
+
+ const struct vop2_power_domain_regs *regs;
+};
+
+/*
+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
+ */
+struct vop2_connector_if_data {
+ u32 id;
+ const char *clk_src_name;
+ const char *clk_parent_name;
+ const char *pixclk_name;
+ const char *dclk_name;
+ u32 post_proc_div_shift;
+ u32 if_div_shift;
+ u32 if_div_yuv420_shift;
+ u32 bus_div_shift;
+ u32 pixel_clk_div_shift;
};
struct vop2_win_data {
const char *name;
uint8_t phys_id;
+ uint8_t splice_win_id;
+ uint8_t pd_id;
uint8_t axi_id;
uint8_t axi_yrgb_id;
uint8_t axi_uv_id;
@@ -875,6 +1057,24 @@
const uint8_t dly[VOP2_DLY_MODE_MAX];
};
+struct dsc_error_info {
+ u32 dsc_error_val;
+ char dsc_error_info[50];
+};
+
+struct vop2_dsc_data {
+ uint8_t id;
+ uint8_t pd_id;
+ uint8_t max_slice_num;
+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
+ const char *dsc_txp_clk_src_name;
+ const char *dsc_txp_clk_name;
+ const char *dsc_pxl_clk_name;
+ const char *dsc_cds_clk_name;
+ const struct vop2_dsc_regs *regs;
+};
+
struct vop2_wb_data {
uint32_t nformats;
const uint32_t *formats;
@@ -897,11 +1097,13 @@
struct vop2_video_port_data {
char id;
+ uint8_t splice_vp_id;
uint16_t lut_dma_rid;
uint32_t feature;
uint64_t soc_id[VOP2_SOC_VARIANT];
uint16_t gamma_lut_len;
uint16_t cubic_lut_len;
+ unsigned long dclk_max;
struct vop_rect max_output;
const u8 pre_scan_max_dly[4];
const u8 hdrvivid_dly[10];
@@ -952,6 +1154,14 @@
struct vop_reg grf_dclk_inv;
struct vop_reg grf_bt1120_clk_inv;
struct vop_reg grf_bt656_clk_inv;
+ struct vop_reg grf_edp0_en;
+ struct vop_reg grf_edp1_en;
+ struct vop_reg grf_hdmi0_en;
+ struct vop_reg grf_hdmi1_en;
+ struct vop_reg grf_hdmi0_dsc_en;
+ struct vop_reg grf_hdmi1_dsc_en;
+ struct vop_reg grf_hdmi0_pin_pol;
+ struct vop_reg grf_hdmi1_pin_pol;
};
struct vop_data {
@@ -969,6 +1179,7 @@
struct vop_rect max_output;
u64 feature;
u64 soc_id;
+ u8 vop_id;
};
struct vop2_ctrl {
@@ -976,6 +1187,9 @@
struct vop_reg wb_cfg_done;
struct vop_reg auto_gating_en;
struct vop_reg aclk_pre_auto_gating_en;
+ struct vop_reg dma_finish_mode;
+ struct vop_reg axi_dma_finish_and_en;
+ struct vop_reg wb_dma_finish_and_en;
struct vop_reg ovl_cfg_done_port;
struct vop_reg ovl_port_mux_cfg_done_imd;
struct vop_reg ovl_port_mux_cfg;
@@ -1015,9 +1229,12 @@
struct vop_reg edp_pin_pol;
struct vop_reg mipi_dclk_pol;
struct vop_reg mipi_pin_pol;
- struct vop_reg dp_dclk_pol;
- struct vop_reg dp_pin_pol;
+ struct vop_reg dp0_dclk_pol;
+ struct vop_reg dp0_pin_pol;
+ struct vop_reg dp1_dclk_pol;
+ struct vop_reg dp1_pin_pol;
+ /* This will be reference by win_phy_id */
struct vop_reg win_vp_id[16];
struct vop_reg win_dly[16];
@@ -1038,10 +1255,25 @@
struct vop_reg lvds_dual_mode;
struct vop_reg lvds_dual_channel_swap;
- struct vop_reg cluster0_src_color_ctrl;
- struct vop_reg cluster0_dst_color_ctrl;
- struct vop_reg cluster0_src_alpha_ctrl;
- struct vop_reg cluster0_dst_alpha_ctrl;
+ struct vop_reg dp_dual_en;
+ struct vop_reg edp_dual_en;
+ struct vop_reg hdmi_dual_en;
+ struct vop_reg mipi_dual_en;
+
+ struct vop_reg hdmi0_dclk_div;
+ struct vop_reg hdmi0_pixclk_div;
+ struct vop_reg edp0_dclk_div;
+ struct vop_reg edp0_pixclk_div;
+
+ struct vop_reg hdmi1_dclk_div;
+ struct vop_reg hdmi1_pixclk_div;
+ struct vop_reg edp1_dclk_div;
+ struct vop_reg edp1_pixclk_div;
+
+ struct vop_reg mipi0_pixclk_div;
+ struct vop_reg mipi1_pixclk_div;
+ struct vop_reg mipi0_ds_mode;
+ struct vop_reg mipi1_ds_mode;
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
@@ -1051,6 +1283,7 @@
struct vop_reg bt1120_yc_swap;
struct vop_reg bt656_yc_swap;
struct vop_reg gamma_port_sel;
+ struct vop_reg pd_off_imd;
struct vop_reg otp_en;
struct vop_reg esmart_lb_mode;
@@ -1065,6 +1298,12 @@
bool enable_state;
};
+struct vop2_vp_plane_mask {
+ u8 primary_plane_id;
+ u8 attached_layers_nr;
+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
+};
+
/**
* VOP2 data structe
*
@@ -1074,25 +1313,43 @@
struct vop2_data {
uint32_t version;
uint32_t feature;
+ uint8_t nr_dscs;
+ uint8_t nr_dsc_ecw;
+ uint8_t nr_dsc_buffer_flow;
uint8_t nr_vps;
uint8_t nr_mixers;
uint8_t nr_layers;
uint8_t nr_axi_intr;
uint8_t nr_gammas;
+ uint8_t nr_conns;
+ uint8_t nr_pds;
+ uint8_t nr_mem_pgs;
uint8_t esmart_lb_mode;
+ bool delayed_pd;
const struct vop_intr *axi_intr;
const struct vop2_ctrl *ctrl;
+ const struct vop2_dsc_data *dsc;
+ const struct dsc_error_info *dsc_error_ecw;
+ const struct dsc_error_info *dsc_error_buffer_flow;
const struct vop2_win_data *win;
const struct vop2_video_port_data *vp;
+ const struct vop2_connector_if_data *conn;
const struct vop2_wb_data *wb;
const struct vop2_layer_data *layer;
+ const struct vop2_power_domain_data *pd;
+ const struct vop2_power_domain_data *mem_pg;
const struct vop_csc_table *csc_table;
const struct vop_hdr_table *hdr_table;
- const struct vop_grf_ctrl *grf_ctrl;
+ const struct vop_grf_ctrl *sys_grf;
+ const struct vop_grf_ctrl *grf;
+ const struct vop_grf_ctrl *vo0_grf;
+ const struct vop_grf_ctrl *vo1_grf;
const struct vop_dump_regs *dump_regs;
uint32_t dump_regs_size;
struct vop_rect max_input;
struct vop_rect max_output;
+ const struct vop2_vp_plane_mask *plane_mask;
+ uint32_t plane_mask_base;
unsigned int win_size;
};
@@ -1169,6 +1426,9 @@
#define ROCKCHIP_OUT_MODE_P565 2
#define ROCKCHIP_OUT_MODE_BT656 5
#define ROCKCHIP_OUT_MODE_S888 8
+#define ROCKCHIP_OUT_MODE_S666 9
+#define ROCKCHIP_OUT_MODE_YUV422 9
+#define ROCKCHIP_OUT_MODE_S565 10
#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
#define ROCKCHIP_OUT_MODE_YUV420 14
/* for use special outface */
@@ -1285,6 +1545,7 @@
DCLK_INVERT = 3
};
+
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
#define SCL_MAX_VSKIPLINES 4
@@ -1369,7 +1630,6 @@
return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
}
-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
extern const struct component_ops vop_component_ops;
extern const struct component_ops vop2_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */
--
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