From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Wed, 31 Jan 2024 03:29:01 +0000 Subject: [PATCH] add lvds1024*800 --- kernel/drivers/gpu/drm/rcar-du/rcar_du_regs.h | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/kernel/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/kernel/drivers/gpu/drm/rcar-du/rcar_du_regs.h index 9dfd220..fb99649 100644 --- a/kernel/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/kernel/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * rcar_du_regs.h -- R-Car Display Unit Registers Definitions * * Copyright (C) 2013-2015 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. */ #ifndef __RCAR_DU_REGS_H__ @@ -199,6 +196,11 @@ #define DEFR6_TCNE0 (1 << 4) #define DEFR6_MLOS1 (1 << 2) #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) + +#define DEFR7 0x000ec +#define DEFR7_CODE (0x7779 << 16) +#define DEFR7_CMME1 BIT(6) +#define DEFR7_CMME0 BIT(4) /* ----------------------------------------------------------------------------- * R8A7790-only Control Registers @@ -492,8 +494,8 @@ * External Synchronization Control Registers */ -#define ESCR 0x10000 -#define ESCR2 0x31000 +#define ESCR02 0x10000 +#define ESCR13 0x01000 #define ESCR_DCLKOINV (1 << 25) #define ESCR_DCLKSEL_DCLKIN (0 << 20) #define ESCR_DCLKSEL_CLKS (1 << 20) @@ -504,8 +506,8 @@ #define ESCR_SYNCSEL_EXHSYNC (3 << 8) #define ESCR_FRQSEL_MASK (0x3f << 0) -#define OTAR 0x10004 -#define OTAR2 0x31004 +#define OTAR02 0x10004 +#define OTAR13 0x01004 /* ----------------------------------------------------------------------------- * Dual Display Output Control Registers -- Gitblit v1.6.2