From f70575805708cabdedea7498aaa3f710fde4d920 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 31 Jan 2024 03:29:01 +0000
Subject: [PATCH] add lvds1024*800
---
kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h | 403 +++++++++++++++++++++++++++++++++++++++++++++-----------
1 files changed, 320 insertions(+), 83 deletions(-)
diff --git a/kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h
index 182d37f..346cc6f 100644
--- a/kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h
+++ b/kernel/drivers/gpu/drm/msm/adreno/a5xx.xml.h
@@ -8,19 +8,21 @@
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
+- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
-Copyright (C) 2013-2018 by the following authors:
+Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -91,6 +93,7 @@
RB5_R32G32B32A32_FLOAT = 130,
RB5_R32G32B32A32_UINT = 131,
RB5_R32G32B32A32_SINT = 132,
+ RB5_NONE = 255,
};
enum a5xx_tile_mode {
@@ -165,6 +168,7 @@
VFMT5_32_32_32_32_UINT = 131,
VFMT5_32_32_32_32_SINT = 132,
VFMT5_32_32_32_32_FIXED = 133,
+ VFMT5_NONE = 255,
};
enum a5xx_tex_fmt {
@@ -250,14 +254,7 @@
TFMT5_ASTC_10x10 = 204,
TFMT5_ASTC_12x10 = 205,
TFMT5_ASTC_12x12 = 206,
-};
-
-enum a5xx_tex_fetchsize {
- TFETCH5_1_BYTE = 0,
- TFETCH5_2_BYTE = 1,
- TFETCH5_4_BYTE = 2,
- TFETCH5_8_BYTE = 3,
- TFETCH5_16_BYTE = 4,
+ TFMT5_NONE = 255,
};
enum a5xx_depth_format {
@@ -1052,8 +1049,18 @@
{
return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
-#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
-#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
+#define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
+#define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
+static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
+{
+ return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
+}
+#define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
+#define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
+static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
+{
+ return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
+}
#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
@@ -1825,37 +1832,192 @@
#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
#define REG_A5XX_RBBM_STATUS 0x000004f5
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
-#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
-#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
-#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
-#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
-#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
-#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
-#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
-#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
-#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
-#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
-#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
-#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
-#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
-#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
-#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
-#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
-#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
-#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
-#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
-#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
-#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
-#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
-#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
-#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
-#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
-#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
-#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
-#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
+}
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
+}
+#define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000
+#define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29
+static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000
+#define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28
+static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000
+#define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27
+static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000
+#define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26
+static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000
+#define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25
+static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000
+#define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24
+static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000
+#define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23
+static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000
+#define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22
+static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000
+#define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21
+static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000
+#define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20
+static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000
+#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19
+static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000
+#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18
+static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000
+#define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17
+static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000
+#define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16
+static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000
+#define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15
+static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
+}
+#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000
+#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14
+static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000
+#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13
+static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000
+#define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12
+static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800
+#define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11
+static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400
+#define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10
+static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200
+#define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9
+static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8
+static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080
+#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7
+static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040
+#define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6
+static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020
+#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5
+static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010
+#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4
+static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008
+#define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3
+static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004
+#define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2
+static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
+}
+#define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002
+#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
+static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
+{
+ return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
+}
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
#define REG_A5XX_RBBM_STATUS3 0x00000530
@@ -1883,14 +2045,6 @@
#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
@@ -2147,6 +2301,8 @@
#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
+
+#define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
@@ -2453,8 +2609,6 @@
#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
-#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
-
#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
@@ -2657,12 +2811,16 @@
#define REG_A5XX_UNKNOWN_E004 0x0000e004
#define REG_A5XX_GRAS_CNTL 0x0000e005
-#define A5XX_GRAS_CNTL_VARYING 0x00000001
-#define A5XX_GRAS_CNTL_UNK3 0x00000008
-#define A5XX_GRAS_CNTL_XCOORD 0x00000040
-#define A5XX_GRAS_CNTL_YCOORD 0x00000080
-#define A5XX_GRAS_CNTL_ZCOORD 0x00000100
-#define A5XX_GRAS_CNTL_WCOORD 0x00000200
+#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
+#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
+#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
+#define A5XX_GRAS_CNTL_SIZE 0x00000008
+#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
+#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
+static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
+{
+ return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
+}
#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
@@ -2989,12 +3147,16 @@
#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
-#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
-#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
-#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
-#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
-#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
-#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
+#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
+#define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
+#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
+#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
+static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
+{
+ return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
+}
#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
@@ -4448,16 +4610,52 @@
{
return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
}
+#define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
+#define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
+static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
+}
#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
-#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
-#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
{
- return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
+ return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
+}
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
+}
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
+}
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
+#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
+static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
}
#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
+static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
+}
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
+#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
+static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
+{
+ return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
+}
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
@@ -4853,9 +5051,25 @@
#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
+#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
+#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
+#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
+static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
+{
+ return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
+}
+
#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
+
+#define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
+#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
+#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
+static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
+{
+ return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
+}
#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
@@ -5057,11 +5271,11 @@
}
#define REG_A5XX_TEX_CONST_2 0x00000002
-#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
-#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
+#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
+#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
+static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
{
- return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
+ return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
}
#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
@@ -5083,6 +5297,13 @@
{
return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
}
+#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
+#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
+static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
+{
+ return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
+}
+#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
#define A5XX_TEX_CONST_3_FLAG 0x10000000
#define REG_A5XX_TEX_CONST_4 0x00000004
@@ -5195,5 +5416,21 @@
return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
}
+#define REG_A5XX_UBO_0 0x00000000
+#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
+#define A5XX_UBO_0_BASE_LO__SHIFT 0
+static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
+{
+ return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
+}
+
+#define REG_A5XX_UBO_1 0x00000001
+#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
+#define A5XX_UBO_1_BASE_HI__SHIFT 0
+static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
+{
+ return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
+}
+
#endif /* A5XX_XML */
--
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