From f45e756958099c35d6afb746df1d40a1c6302cfc Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 07 Nov 2023 06:20:23 +0000
Subject: [PATCH] enable wifi gpio
---
kernel/include/uapi/linux/rk-pcie-ep.h | 67 +++++++++++++++++++++++++++++++++
1 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/kernel/include/uapi/linux/rk-pcie-ep.h b/kernel/include/uapi/linux/rk-pcie-ep.h
index 37726a6..b6e3ac0 100644
--- a/kernel/include/uapi/linux/rk-pcie-ep.h
+++ b/kernel/include/uapi/linux/rk-pcie-ep.h
@@ -8,13 +8,77 @@
#include <linux/types.h>
+/* rkep device mode status definition */
+#define RKEP_MODE_BOOTROM 1
+#define RKEP_MODE_LOADER 2
+#define RKEP_MODE_KERNEL 3
+#define RKEP_MODE_FUN0 4
+/* Common status */
+#define RKEP_SMODE_INIT 0
+#define RKEP_SMODE_LNKRDY 1
+#define RKEP_SMODE_LNKUP 2
+#define RKEP_SMODE_ERR 0xff
+/* Firmware download status */
+#define RKEP_SMODE_FWDLRDY 0x10
+#define RKEP_SMODE_FWDLDONE 0x11
+/* Application status*/
+#define RKEP_SMODE_APPRDY 0x20
+
+/*
+ * rockchip pcie driver elbi ioctrl output data
+ */
struct pcie_ep_user_data {
+ __u64 bar0_phys_addr;
__u32 elbi_app_user[11];
};
+/*
+ * rockchip driver cache ioctrl input param
+ */
struct pcie_ep_dma_cache_cfg {
__u64 addr;
__u32 size;
+};
+
+#define PCIE_EP_OBJ_INFO_MAGIC 0x524B4550
+
+enum pcie_ep_obj_irq_type {
+ OBJ_IRQ_UNKNOWN,
+ OBJ_IRQ_DMA,
+ OBJ_IRQ_USER,
+ OBJ_IRQ_ELBI,
+};
+
+struct pcie_ep_obj_irq_dma_status {
+ __u32 wr;
+ __u32 rd;
+};
+
+enum pcie_ep_mmap_resource {
+ PCIE_EP_MMAP_RESOURCE_DBI,
+ PCIE_EP_MMAP_RESOURCE_BAR0,
+ PCIE_EP_MMAP_RESOURCE_BAR2,
+ PCIE_EP_MMAP_RESOURCE_BAR4,
+ PCIE_EP_MMAP_RESOURCE_MAX,
+};
+
+/*
+ * rockchip ep device information which is store in BAR0
+ */
+struct pcie_ep_obj_info {
+ __u32 magic;
+ __u32 version;
+ struct {
+ __u16 mode;
+ __u16 submode;
+ } devmode;
+ __u8 reserved[0x1F4];
+
+ __u32 irq_type_rc; /* Generate in ep isr, valid only for rc, clear in rc */
+ struct pcie_ep_obj_irq_dma_status dma_status_rc; /* Generate in ep isr, valid only for rc, clear in rc */
+ __u32 irq_type_ep; /* Generate in ep isr, valid only for ep, clear in ep */
+ struct pcie_ep_obj_irq_dma_status dma_status_ep; /* Generate in ep isr, valid only for ep, clear in ep */
+ __u32 obj_irq_user_data; /* OBJ_IRQ_USER userspace data */
};
#define PCIE_BASE 'P'
@@ -22,5 +86,8 @@
#define PCIE_DMA_CACHE_INVALIDE _IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg)
#define PCIE_DMA_CACHE_FLUSH _IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg)
#define PCIE_DMA_IRQ_MASK_ALL _IOW(PCIE_BASE, 3, int)
+#define PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER _IOW(PCIE_BASE, 4, int)
+#define PCIE_EP_GET_USER_INFO _IOR(PCIE_BASE, 5, struct pcie_ep_user_data)
+#define PCIE_EP_SET_MMAP_RESOURCE _IOW(PCIE_BASE, 6, enum pcie_ep_mmap_resource)
#endif
--
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